JP4688724B2 - Functional block test circuit and integrated circuit device - Google Patents

Description

  The present invention relates to a test circuit for a functional block of an integrated circuit device and an integrated circuit device provided with the test circuit.

  In general, a functional block including a logic circuit in an integrated circuit device is provided with a register in which parameters unique to the functional block are set. There is also a proposal of an integrated circuit device having a function of switching a test mode of a functional block of the integrated circuit device (see, for example, Patent Document 1). This integrated circuit device has a functional block, a test mode setting terminal, and a logic circuit for setting a test mode. A signal is input from an external terminal to set a register in the functional block to a predetermined state, and a test is performed. By inputting a test mode setting signal to the logic circuit from the mode setting terminal, the functional block is set to the test mode.

JP-A-6-27204 (paragraphs 0006 and 0010, FIG. 1)

  However, Patent Document 1 does not have a specific description regarding external terminals for setting a register in a functional block. Therefore, in this integrated circuit device, in order to be able to change the set value of the register in the functional block, an input terminal corresponding to the number of registers is required, and the scale of the integrated circuit device is proportional to the number of registers. The problem of increasing is caused.

  In addition, since the logic circuit whose circuit scale increases with the increase in the number of registers is added to the integrated circuit device disclosed in Patent Document 1, the integrated circuit device has an increase in the number of registers. There is a problem that the scale increases.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to perform a plurality of types of functional block tests while suppressing an increase in circuit scale of the integrated circuit device. A functional block test circuit and an integrated circuit device including the test circuit are provided.

A functional block test circuit according to the present invention is a test circuit for testing a functional block in an integrated circuit device having arithmetic means, a functional block including a register, and a bus to which the arithmetic means and the functional block are connected. A serial data signal input terminal to which a serial data signal is input; a serial data control signal input terminal to which a serial data control signal is input; the serial data signal and the serial data control signal are input; Serial-parallel conversion means for converting the serial data signal into a parallel data signal in accordance with a data control signal, bus control means connected to the bus, and a parallel data signal output from the bus control means are input, and the parallel Convert data signals to serial data signals Serial data indicating the state of the serial data signal output from the serial data signal output terminal, a serial data signal output terminal for outputting the serial data signal output from the parallel serial conversion means, and the serial data signal to the outside A serial data status signal output terminal for outputting a status signal to the outside; other test means for performing another test in the integrated circuit device; and the serial data signal and the other test means output from the parallel-serial conversion means. Selection means for outputting any one of the test result signals output from the serial data signal output terminal, and a terminal switching signal input terminal to which a switching signal of the selection means is input , and the bus control means, When writing data to the function block registers, A bus control signal for data write is generated in response to the output of the real conversion means, and the generated bus control signal for data write is output to the functional block via the bus, and from the register of the functional block At the time of data read, the output of the serial-parallel conversion means is received to generate a data read bus control signal, and the generated data read bus control signal is output to the functional block via the bus, The parallel data signal output from the functional block is output to the parallel-serial conversion means, and the serial data status signal is output to the serial data status signal output terminal.

The integrated circuit device of the present invention includes a computing unit, a functional block including a register, and a bus for connecting the operation means and the function block, which is connected to the bus, a test circuit for testing of the function block The test circuit includes a serial data signal input terminal to which a serial data signal is input, a serial data control signal input terminal to which a serial data control signal is input, the serial data signal and The serial data control signal is input, serial / parallel conversion means for converting the serial data signal into a parallel data signal according to the serial data control signal, bus control means connected to the bus, and output from the bus control means The parallel data signal is input and the parallel data signal is serialized. Parallel serial conversion means for converting to a serial data signal, a serial data signal output terminal for outputting a serial data signal output from the parallel serial conversion means to the outside, and the serial data signal output from the serial data signal output terminal A serial data status signal output terminal for outputting a serial data status signal indicating the status to the outside, other test means for performing other tests, the serial data signal output from the parallel serial conversion means and the other test means Selection means for outputting any one of the test result signals output from the serial data signal output terminal, and a terminal switching signal input terminal to which a switching signal of the selection means is input , and the bus control means, When writing data to the function block registers, A bus control signal for data write is generated in response to the output of the real conversion means, and the generated bus control signal for data write is output to the functional block via the bus, and from the register of the functional block At the time of data read, the output of the serial-parallel conversion means is received to generate a data read bus control signal, and the generated data read bus control signal is output to the functional block via the bus, The parallel data signal output from the functional block is output to the parallel-serial conversion means, and the serial data status signal is output to the serial data status signal output terminal.

  According to the present invention, the set value change in the register of the functional block of the semiconductor integrated circuit can be designated by the input of the serial data signal and the serial data control signal, so that no test register is necessary and the number of test terminals is increased. Can be suppressed. Therefore, there is an effect that a plurality of types of functional block tests can be performed while suppressing an increase in circuit scale of the integrated circuit device.

Embodiment 1 FIG.
[Configuration of Integrated Circuit Device 100]
FIG. 1 is a block diagram schematically showing a configuration of an integrated circuit device 100 according to the first embodiment of the present invention.

  As shown in FIG. 1, the integrated circuit device 100 according to the first embodiment includes a central processing unit (CPU) 110, a CPU bus 111, a functional block 120 having a register, and a test circuit 130. The CPU 110, the functional block 120, and the test circuit 130 are connected by a CPU bus 111 that is an on-chip bus.

  In normal use, the function block 120 executes a predetermined process on the external input from the external data input terminal 112, changes the set value of the register in the function block 120 according to the process result, and then The value of the register in the function block 120 is read (that is, read) by the CPU 110.

  As shown in FIG. 1, the functional block 120 includes a bus slave interface circuit 121, a CPU register control circuit 122, a register A (reference numeral 123), a register B (reference numeral 124), and a register C (reference numeral 125). And register D (reference numeral 126). However, the number of registers is not limited to the number shown.

  As shown in FIG. 1, the test circuit 130 includes a serial / parallel conversion circuit 131, a parallel / serial conversion circuit 132, and a bus master interface circuit 133 connected to the CPU bus 111. The test circuit 130 has a serial data signal input terminal 134a to which a serial data signal is input, a serial data control signal input terminal 134b to which a serial data control signal is input, and serial data that is an output of the parallel-serial conversion circuit 132. A serial data signal output terminal 135a for outputting a signal to the outside, a serial data control signal output terminal 135b, and a bus master for outputting a serial data state signal indicating the state of the serial data signal output from the serial data signal output terminal 135a to the outside Interface circuit status signal output terminal 136. The serial-parallel conversion circuit 131 receives the serial data signal input from the serial data signal input terminal 134a and the serial data control signal input from the serial data control signal input terminal 134b, and converts the serial data signal according to the serial data control signal. Convert to parallel data signal. The parallel / serial conversion circuit 132 receives the parallel data signal output from the bus master interface circuit 133 and converts the parallel data signal into a serial data signal.

[Operation during normal use]
Next, operations of the CPU 110 and the functional block 120 of the integrated circuit device 100 during normal use will be described.

  The CPU 110 is connected to the CPU bus 111 as a master. For example, the CPU 110 has a 32-bit width, and the entire address space is 2 32 words (32 bits). The functional block 120 is connected to the CPU bus 111 as a slave, and a certain address space is allocated. The CPU 110 can perform write and read operations on the registers A, B, and C held by the functional block 120 via the CPU bus 111.

  The CPU bus 111 is actually a signal line for write data (wdata), read data (rdata), control signal input accompanying them, control signals outputted accompanying them, and the like. It consists of The output control signal includes an address signal, an access request signal (request signal), a read / write control signal, and the like. The input control signal includes a response signal to the access request signal (ACK (Acknowledgement) signal or BUSY signal). In the first embodiment, when the read / write control signal is “0”, a read operation is indicated, and when it is “1”, a write operation is indicated.

  The function block 120 needs to set a parameter P that determines a condition, a mode, and the like when executing a process that fulfills the function. In the first embodiment, the value stored in the register A is used as the parameter P, and the operation is started by setting the value “1” in the register B. In the first embodiment, the status information S indicating the state in which the functional block 120 is in operation, in an idle state, or abnormally terminated is written to the register C as needed. Update.

  In the first embodiment, the status information S of the functional block 120 held in the register C is composed of 2 bits. When the lower bit is “0”, an idle state is performed, and when the lower bit is “1”, a process is performed. When the upper bit is “1” in the execution state, it indicates that the process has ended abnormally.

  In the function block 120, the processing result for the data input from the external data input terminal 112 is written into the register D. The CPU 110 can obtain the processing result information by the functional block 120 by reading the register D.

  In normal use, first, the CPU 110 outputs a request signal for the register A to the CPU bus 111 together with an address signal and a read / write control signal in order to confirm the parameter P set in the functional block 120. The read / write control signal at this time is “0” indicating a read operation.

  The bus slave interface circuit 121 in the functional block 120 receives a request signal from the CPU 110, determines that it is a read request for the register A, and if the read request from the CPU 110 is available, an ACK signal is sent from the CPU 110. If the read request is not satisfied, a BUSY signal is returned to the CPU 110. Along with the operation in which the bus slave interface circuit 121 returns an ACK signal to the CPU 110, the CPU register control circuit 122 passes the value held in the register A to the bus slave interface circuit 121. In response to this, the bus slave interface circuit 121 outputs the value held in the register A to the CPU bus 111 as read data. CPU 110 determines that the value of register A is output based on the previously returned ACK signal, and receives the value of register A as read data.

  The CPU 110 determines whether or not the received value of the register A is appropriate, and outputs a request signal to the register A to the CPU bus 111 again together with the address signal and the read / write control signal if necessary. The read / write control signal at this time is “1” indicating a write operation. As in the case of the read access described above, the bus slave interface circuit 121 receives a request signal from the CPU 110, determines that it is a write request for the register A, and if it is in a state that can respond to the write request from the CPU 110, ACK. If the signal is in a state where it cannot respond to the write request from the CPU 110, a BUSY signal is returned to the CPU 110. CPU 110 continues to output write data to CPU bus 111 as write data until it receives an ACK signal. The bus slave interface circuit 121 receives the write data, passes it to the CPU register control circuit 122, and the CPU register control circuit 122 rewrites the value of the register A.

  Next, the CPU 110 generates a write request signal for the register B, and sets a value “1” indicating the start of calculation in the register B, similarly to the write operation for the register A. In response to setting the value “1” in the register B, the function block 120 refers to the value held in the register A, and processes the data input from the external data input terminal 112 by the function block 120. And the value of the processing result is written to the register D.

  At this time, the CPU register control circuit 122 writes the value “1” indicating the processing execution state in the lower bits of the register C, and when the processing in the function block 120 is normally completed, the value “1” indicating the idle state in the lower bits of the register C. Write 0 ".

  The CPU 110 receives an interrupt signal (not shown) from the functional block 120, or reads the value of the register C as appropriate by polling to determine whether the processing in the functional block 120 has been completed normally. If so, processing result information is obtained by reading the register D.

  In the above description of the operation, it is assumed that the functional block 120 is initially in the idle state, and when the CPU 110 executes the operation by rewriting the register A or writing the value “1” to the register B, Although description of the operation for confirming the status of the functional block 120 is omitted, when the functional block 120 is operated continuously, an operation for confirming the status of the functional block 120 is also necessary.

  In the above description of the operation, the calculation result is written in the register D, and the CPU 110 reads the value of the calculation result written in the register D. However, the calculation result value is stored in the external terminal ( It is also possible to adopt a configuration in which the data is directly output to (not shown).

  In the above description of the operation, the case where the read operation and the write operation with respect to the registers A to D are individually performed has been described. However, in general, a program that continuously performs a series of operations is prepared as an instruction code for the CPU 110. To do.

[Operation of Test Circuit 130]
Next, an operation when the functional block 120 is tested using the test circuit 130 in the integrated circuit device 100 will be described.

  In normal operation, the CPU 110 determines a parameter P according to a program and executes a read operation and a write operation on registers A to D (hereinafter also collectively referred to as “register group”) of the functional block 120. When testing the block, the function block 120 may be operated under conditions that are not performed in normal operation, and the parameter P corresponding to the condition is written to the register group or the value of the register group is read.

  At this time, since the required function is only the read and write operations for the register group, the CPU 110 is stopped and the test circuit 130 is used instead.

  In the first embodiment, the serial data signal input terminal 134a and the serial data signal output terminal 135a in the test circuit 130 each have a 1-bit width. The serial data control signal input terminal 134b is 1 bit for the reset signal RST_N. Further, the data input enable signal DINENA_N is 1 bit, and the write signal WR_N is 1 bit, and the total width is 3 bits. Further, the serial data control signal output terminal 135b is 1 bit wide for the serial data control signal DOUTENA_N, and the bus master interface circuit status signal output terminal 136 is 1 bit wide for the bus master interface circuit status signal STAT_N.

  In the first embodiment, each of the reset signal RST_N, the data input enable signal DINENA_N, and the write signal WR_N input from the serial data control signal input terminal 134b is valid at “0”. The reset signal RST_N is “0” and resets the flip-flop in the serial / parallel conversion circuit 131. During the period when the data input enable signal DINENA_N is “0”, the signal input to the serial data signal input terminal 134a is valid. When the write signal WR_N is “0”, it is a write access to the register, and when the write signal WR_N is “1”, it is a read access to the register.

  Similarly, in the first embodiment, the signal output from the serial data signal output terminal 135a is valid during the period when the serial data control signal DOUTENA_N output from the serial data control signal output terminal 135b is “0”. If the bus master interface circuit status signal STAT_N output from the bus master interface circuit status signal output terminal 136 is “0”, it means that the register access to the function block 120 via the CPU bus 111 in the bus master interface circuit 133 has been normally completed. Show.

[Write operation during test]
FIG. 2 is a timing chart showing a register write operation by the test circuit 130 of the integrated circuit device 100 according to the first embodiment.

  In FIG. 2, a serial data signal DIN indicates a state at the serial data signal input terminal 134a, and a serial data signal DOUT indicates a state at the serial data signal output terminal 135a. The reset signal RST_N, the data input enable signal DINENA_N, and the write signal WR_N are signals input to the serial data control signal input terminal 134b. Further, the serial data output control signal DOUTENA_N is a signal output to the serial data control signal output terminal 135b, and the bus master interface circuit status signal STAT_N is a signal output to the bus master interface circuit status signal output terminal 136.

When writing the data _{D A} in the register A, from the serial data signal input terminals 134a, each 32-bit address _{A A} and data _{D A} in the register A, along with input from the MSB, the serial data control signal input terminal 134b, Input serial data control signal. Since the write operation is performed here, “0” is input as the write signal WR_N.

Serial-parallel conversion circuit 131 rearranges the addresses A _A and data D _A input is converted into parallel data signals of 32 bits wide, and outputs to the bus master interface circuit 133.

Bus master interface circuit 133 receives an address _{A A} and data _{D A,} a write operation and to determine since the write signal WR_N is "0", similarly to the CPU110 in normal operation, the bus of the write request or the like to the CPU bus 111 Output a control signal.

Bus slave interface circuit 121 of the functional block 120 receives the bus control signals from the CPU bus 111, it is determined that the write request to the register A by decoding the address _{A A,} and returns an ACK signal to the CPU110 together, pass information that the CPU register control circuit 122 is a write operation of the data _{D a} for the address _{a a.} CPU register control circuit 122 writes the data _{D A} to the register A. When the write operation on the register A is normally completed, the bus slave interface circuit 121 outputs a status signal indicating that the write operation is normally completed to the CPU bus 111 as a bus control signal.

  The test circuit 130 determines from the bus control signal output from the functional block 120 to the CPU bus 111 that the bus master interface circuit 133 has normally performed the write operation to the register A, and the value of the bus master interface circuit status signal STAT_N. "0" is output.

  Since the value of the bus master interface circuit status signal STAT_N is output to the output terminal 136, it is possible to know whether or not the write operation to the register A has been normally performed by monitoring the state of the output terminal 136.

[Read operation during test]
FIG. 3 is a timing chart showing a register read operation by the test circuit 130 of the integrated circuit device 100 according to the first embodiment.

Similarly to the write operation, 32-bit data, which is the address AC of the register _C , is input from the MSB from the serial data signal input terminal 134a, and a control signal is input to the serial data control signal input terminal 134b. However, since it is a read operation, data is not input and “1” is input as the write signal WR_N.

Serial-parallel conversion circuit 131 rearranges the addresses A _C input is converted into parallel data signals 32-bit wide, and outputs to the bus master interface circuit 133.

Bus master interface circuit 133 determines that the read operation to the address _{A C,} the CPU bus 111, outputs a bus control signals such as a read request.

Bus slave interface circuit 121 of the functional block 120 receives the bus control signals from the CPU bus 111, decodes the address _{A C,} determines that a read request to the register C, and ACK signal to the CPU110 with return, pass information that it is a read operation to the CPU register control circuit 122 to the address _{a C,} CPU register control circuit 122 reads the value held in the register C. If the read operation for the register C is normally completed, the bus slave interface circuit 121 outputs a read data and a status signal indicating that the read operation is normally completed to the CPU bus 111 as a bus control signal.

The bus master interface circuit 133 in the test circuit 130 determines from the bus control signal output from the functional block 120 to the CPU bus 111 that the read operation for the register C has been normally performed, and the bus master interface circuit status signal STAT_N outputs a "0" as the value, receives the read data _{D C} from the CPU bus 111, and outputs the parallel-serial conversion circuit 132.

Parallel-serial conversion circuit 132 converts the read data _{D C} to a serial data signal 32 bits long in order from the MSB, with a "0" to the serial data output control signal DOUTENA_N only output is enabled period, the serial data signal output terminal To 135a. The serial data output control signal DOUTENA_N is output from the serial data control signal output terminal 135b.

Therefore, as in the case of a write operation, by monitoring the state of the external test terminals 135a, 135b, 136, the read operation for the register C is carried out normally, it is possible to obtain a read value of the read data D _C .

  In the above description, the serial data signal input terminal 134a and the serial data signal output terminal 135a have been described as having a 1-bit width. However, if a terminal of 2 bits or more can be used for testing, it should be a multi-bit input / output. Is also possible.

  If the address space can be limited, it is not necessary to set all 32 bits as address information, and it is not necessary to input a part of the address data according to the target address space, and the bits of the address data to be input It is also possible to reduce the length.

[Effect of Embodiment 1]
As described above, according to the first embodiment, it is possible to perform register access using a small number of external terminals even for a functional block that does not have a mechanism for switching register values for testing in advance. . Therefore, the required number of test terminals may be a fixed number regardless of the number of registers to be tested, and the number of terminals used for testing and the increase in circuit scale are constant regardless of the number of registers to be tested. It can be. For this reason, the setting value change in the functional block to be tested can be specified by test input, so the addition of test registers and the increase in the number of test terminals can be suppressed, and the increase in the circuit scale of the integrated circuit device can be suppressed. However, it is possible to test a plurality of types of functional blocks.

  In addition, since it is not necessary to start the CPU during the test, register access to the functional block 120 can be realized with a small number of steps.

Embodiment 2. FIG.
[Configuration of Integrated Circuit Device 200]
FIG. 4 is a block diagram schematically showing the configuration of the integrated circuit device 200 according to the second embodiment of the present invention.

  In the integrated circuit device 200, components that are the same as or correspond to the components of the integrated circuit device 100 shown in FIG. As shown in FIG. 4, in the integrated circuit device 200 according to the second embodiment, the configuration of the test circuit 230 is different from the configuration of the test circuit 130 of the integrated circuit device 100 according to the first embodiment. The test circuit 230 according to the second embodiment is output from the JTAG circuit 140 as another test means for performing another test in the integrated circuit device 200, the serial data signal output from the parallel-serial conversion circuit 132, and the JTAG circuit 140. The point of having multiplexers (MUX) 141a and 141b as selection means for outputting any one of the test result signals from the serial data signal output terminal is different from that of the first embodiment. Here, the JTAG circuit 140 has a function for debugging the terminal switching signal input terminal 142 and the CPU 110. The multiplexers 141a and 141b are for switching the output signals of the JTAG circuit 140 and the test circuit 230 by a signal input from the terminal switching signal input terminal 142. The other configuration of the integrated circuit device according to the second embodiment is the same as that of the integrated circuit device according to the first embodiment.

[Operation of Test Circuit 230]
In the second embodiment, the switching signal SEL input to the terminal switching signal input terminal 142 is a 1-bit signal. If “0”, the JTAG circuit 140 is used, and if “1”, the test is performed. Circuit 230 is used. When the CPU 110 is activated to perform a test, a serial data signal input terminal 134a, a serial data control signal input terminal 134b, a serial data signal output terminal 135a, and a serial data control signal output terminal which are external terminals used in the test circuit 230 are used. 135b is input as a switching signal SEL from the terminal switching signal input terminal 142 so that it can be used in the JTAG circuit 140. On the other hand, when the test of the functional block 120 is performed by the test circuit 230, “1” is input as the switching signal SEL from the terminal switching signal input terminal 142, and the multiplexers 141a and 141b are switched.

[Effect of Embodiment 2]
As described above, according to the second embodiment, the test circuit 230 can be used as both an external terminal used when the functional block 130 is tested and an external terminal used when the JTAG circuit 140 is tested. The test circuit 230 can be configured without multiplexing with external terminals used for actual functions. Therefore, an increase in the number of test terminals can be suppressed, and an increase in the circuit scale of the integrated circuit device can be suppressed.

1 is a block diagram schematically showing a configuration of an integrated circuit device according to a first embodiment of the present invention. 6 is a timing diagram illustrating a register write operation by the test circuit of the integrated circuit device according to the first embodiment. FIG. 6 is a timing diagram illustrating a register read operation by the test circuit of the integrated circuit device according to the first embodiment. It is a block diagram which shows roughly the structure of the integrated circuit device which concerns on Embodiment 2 of this invention.

Explanation of symbols

100, 200 integrated circuit device, 110 CPU, 111 CPU bus, 112 external data input terminal, 120 functional block, 121 bus slave interface circuit, 122 CPU register control circuit, 123 register A, 124 register B, 125 register C, 126 register D, 130, 230 test circuit, 131 serial parallel conversion circuit, 132 parallel serial conversion circuit, 133 bus master interface circuit, 134a serial data signal input terminal, 134b serial data control signal input terminal, 135a serial data signal output terminal, 135b serial data Control signal output terminal, 136 Bus master interface circuit status signal output terminal, 140 JTAG circuit, 141a, 141b Multiplex 142 Terminal switching signal input terminal.

Claims (6)

A test circuit for testing the functional block in an integrated circuit device having an arithmetic means, a functional block including a register, and a bus to which the arithmetic means and the functional block are connected,
A serial data signal input terminal to which a serial data signal is input;
A serial data control signal input terminal to which a serial data control signal is input;
Serial-parallel conversion means for inputting the serial data signal and the serial data control signal and converting the serial data signal into a parallel data signal according to the serial data control signal;
Bus control means connected to the bus;
A parallel data signal outputted from the bus control means, and a parallel / serial conversion means for converting the parallel data signal into a serial data signal;
A serial data signal output terminal for outputting a serial data signal output from the parallel-serial conversion means to the outside;
A serial data status signal output terminal for outputting a serial data status signal indicating the status of the serial data signal output from the serial data signal output terminal ;
Other test means for performing other tests in the integrated circuit device;
Selection means for outputting from the serial data signal output terminal either the serial data signal output from the parallel-serial conversion means or the test result signal output from the other test means;
A terminal switching signal input terminal to which the switching signal of the selection means is input ;
The bus control means includes
At the time of data writing to the register of the functional block, the output of the serial / parallel conversion means is received to generate a bus control signal for data write, and the generated bus control signal for data write is sent to the bus via the bus. Output to the functional block,
At the time of data read from the register of the functional block, the output of the serial-parallel conversion means is received to generate a bus control signal for data read, and the generated bus control signal for data read is sent via the bus A function that outputs to the functional block, outputs the parallel data signal output from the functional block to the parallel-serial conversion means, and outputs the serial data status signal to the serial data status signal output terminal. Block test circuit. Serial data input to the serial data signal input terminal when writing data to the register of the functional block includes address data of the register and write data corresponding to the address data,
Serial data input to the serial data signal input terminal at the time of data reading from the register of the functional block includes address data of the register,
2. The functional block test circuit according to claim 1, wherein serial data output from the serial data signal output terminal when data is read from the register of the functional block includes read data from the register. 3. 3. The functional block test circuit according to claim 1, wherein the other test means is a JTAG circuit. Computing means;
A functional block including a register;
A bus connecting the computing means and the functional block;
Connected to said bus, an integrated circuit device having a test circuit for testing of the functional blocks,
The test circuit includes:
A serial data signal input terminal to which a serial data signal is input;
A serial data control signal input terminal to which a serial data control signal is input;
Serial-parallel conversion means for inputting the serial data signal and the serial data control signal and converting the serial data signal into a parallel data signal according to the serial data control signal;
Bus control means connected to the bus;
A parallel data signal outputted from the bus control means, and a parallel / serial conversion means for converting the parallel data signal into a serial data signal;
A serial data signal output terminal for outputting a serial data signal output from the parallel-serial conversion means to the outside;
A serial data status signal output terminal for outputting a serial data status signal indicating the status of the serial data signal output from the serial data signal output terminal ;
Other testing means to do other tests,
Selection means for outputting from the serial data signal output terminal either the serial data signal output from the parallel-serial conversion means or the test result signal output from the other test means;
A terminal switching signal input terminal to which the switching signal of the selection means is input ;
The bus control means includes
At the time of data writing to the register of the functional block, the output of the serial / parallel conversion means is received to generate a bus control signal for data write, and the generated bus control signal for data write is sent to the bus via the bus. Output to the functional block,
At the time of data read from the register of the functional block, the output of the serial-parallel conversion means is received to generate a bus control signal for data read, and the generated bus control signal for data read is sent via the bus An integrated circuit that outputs to the functional block, outputs the parallel data signal output from the functional block to the parallel-serial conversion means, and outputs the serial data status signal to the serial data status signal output terminal. Circuit device. Serial data input to the serial data signal input terminal when writing data to the register of the functional block includes address data of the register and write data corresponding to the address data,
Serial data input to the serial data signal input terminal at the time of data reading from the register of the functional block includes address data of the register,
The integrated circuit device according to claim 4 , wherein serial data output from the serial data signal output terminal when data is read from the register of the functional block includes read data from the register. 6. The integrated circuit device according to claim 4 , wherein the other test means is a JTAG circuit.

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