JP3024310B2 - Logic circuit inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for a logic circuit used in an arithmetic unit of a computer or the like, and more particularly to an inspection apparatus for inspecting a scan path register as a component of the logic circuit.

[0002]

2. Description of the Related Art A logic circuit used for an arithmetic unit or the like of a computer is composed of a sequential circuit and a combinational circuit. Among them, a conventional inspection apparatus for inspecting a scan path register constituting a sequential circuit is known. The individual flip-flops constituting each scan path register included in the circuit under test and individually operating during normal operation are connected in series to form a continuous scan path register, and the continuous scan path A register having a bit string of the same length as the bit string of the register is connected in series to the circuit under test, a specific test pattern is written in the register, and the pattern is read out through a continuous scan path register, thereby making each scan path register Examination of the normality of
Analysis of the location of the fault when there is a fault.

[0003]

The conventional inspection apparatus for scan path registers of a logic circuit as described above requires a register having a bit string of a length in which the scan path registers of the circuit under test are continuous. Specific test data of the same length to be written is required. In general, the length of a continuous scan path register of a logic circuit differs depending on the type of the logic circuit. Accordingly, the conventional inspection apparatus for scan path registers of a logic circuit requires a register and test data corresponding to each type of logic circuit to be prepared, which causes a considerable burden on both software and hardware. However, there is a drawback in that Further, at the time of the test, since all bits of the continuous scan path register are compared, it is difficult to speed up the test.

[0004]

SUMMARY OF THE INVENTION According to the present invention, there is provided a logic circuit testing apparatus for transmitting a clock signal and inputting a stop signal to stop the operation, and for setting a value for starting the operation to an arbitrary value. Can be set to a value (-1) for each clock of the clock signal from the clock generator.
Counter, which detects when the content of the subtraction counter becomes "0" and sends the stop signal to the clock generator, and stores test data in advance. In addition, a write register that shifts one bit at a time by the clock signal and sends its output signal to a scan path register of the circuit under test, and the test data via the scan path register of the circuit under test. A read register for reading and storing the clock signal and transmitting the clock signal to the host device when the transmission of the clock signal is stopped; and an input setting circuit for setting the scan path register of the circuit under test to a test mode.

[0005]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, an input setting circuit 7 is provided for each flip-flop constituting each scan path register included in a circuit under test 8 which operates individually during normal operation (normal mode). This is a circuit for setting the scan path register to the test mode by connecting it in series to form a continuous scan path register. The circuit under test 8 has a scan path register 10 therein, and sets the scan path register 10 to a test mode in accordance with a command from the input setting circuit 7.

The write register 5 usually has a length of about 16 to 32 bits, and is pre-written with test data via the data bus 6. The subtraction counter 2 is set to a value obtained by adding the length of the scan path register 10 of the circuit under test 8 and the length of the write register 5, and performs subtraction by the clock signal 4 from the clock generator 1. In the detector 3, the content of the subtraction counter 2 is "0".
Is detected, and a stop signal 10 is sent to the clock generator 1. The read register 9 reads the test data of the write register 5 via the scan path register 10 of the circuit under test 8 and temporarily stores the read data.

When the clock generator 1 starts operating, the inspection apparatus for a logic circuit configured as described above receives the clock signal 4 from the subtraction counter 2, the write register 5, the scan path register 10, and the read register 9.
Is sent. The subtraction counter 2 outputs 1 of the clock signal 4
Subtraction of (-1) is performed for each clock. Write register 5
Shifts the clock signal 4 by one bit every one clock and outputs the output signal 11 to the scan path register 1
Send for 0. Since the output terminal of the scan path register 10 is connected to the input terminal of the read register 9, the read signal 12 output from the scan path register 10 is sequentially input to the read register 9. Therefore, the contents of the write register 5 are transmitted to the read register 9 via the scan path register 10.

When the content of the subtraction counter 2 becomes "0",
The detector 3 operates and sends a stop signal 13 to the clock generator 1. As a result, the operation of the clock generator 1 stops, and accordingly, the operations of the write register 5, the scan path register 10, and the read register 9 also stop. At this point, the entire contents of the write register 5 have been transferred to the read register 9. Therefore, the contents of the read register 9 are sent to the host device via the data bus 6 and compared with the contents written to the write register 5 to check whether the operation of the scan path register 10 is normal. .

By preparing a plurality of types of test data to be written in the write register 5 and sequentially executing them, the dependence of the operation of the scan path register 10 on the pattern of the test data can also be examined.

[0012]

As described above, in the logic circuit testing apparatus of the present invention, test data is stored in the write register, and the read data is read out via the scan path register of the circuit under test. The test hardware and the software for creating the test data are stored in a register, and when the reading of the test data is completed, the read data is compared with the contents written in the write register. This has the effect of reducing the burden on the user. There is also an effect that the test can be sped up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock generator 2 Subtraction counter 3 Detector 4 Clock signal 5 Write register 6 Data bus 7 Input setting circuit 8 Circuit under test 9 Read register 10 Scan path register 11 Output signal 12 Read signal 13 Stop signal

Claims (2)

(57) [Claims] 1. A clock generator for transmitting a clock signal and inputting a stop signal to stop the operation, and a value at which the operation is started can be set to an arbitrary value. A subtraction counter for subtracting (-1) for each clock of the clock signal; detecting when the content of the subtraction counter becomes "0" and transmitting the stop signal to the clock generator; A write register that stores test data in advance, shifts one bit at a time by the clock signal, and sends an output signal to a scan path register of the circuit under test, A read register for reading out and storing via the scan path register of the circuit under test and transmitting it to the host device when the transmission of the clock signal is stopped; And a logic circuit inspection device. 2. A clock generator for transmitting a clock signal and inputting a stop signal to stop the operation, and a value for starting the operation can be set to an arbitrary value. A subtraction counter for subtracting (-1) for each clock of the clock signal; detecting when the content of the subtraction counter becomes "0" and transmitting the stop signal to the clock generator; A write register that stores test data in advance, shifts one bit at a time by the clock signal, and sends an output signal to a scan path register of the circuit under test, A read register for reading out and storing via the scan path register of the circuit under test and transmitting it to the host device when the transmission of the clock signal is stopped; A test circuit for setting the scan path register of the circuit to be tested to a test mode.