JPH09159698A - Waveform memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the circuitry by a constitution wherein a peak value detection circuit, being used as a peak value detection circuit and a data com pression means, also serves as a clock control circuit. SOLUTION: In a sampling operation, an analog signal 50 from an input terminal 1 is converted 3 into a digital signal 52 and inputted to a peak value detection circuit 4. The detection circuit 4 compares the data within the period of a clock 57 at the period of a clock 56 and stores the comparison data 53 of maximum and minimum values thereof in a first memory 5 at the period of a clock 62. In a compression operation, the data stored in the first memory 5 is inputted to the detection circuit 4 by applying the clocks 56, 62 of same period to the CK of first memory 5 and the CK1 of detection circuit 4 by means of a read clock 63 from a direct memory access 12. The detection circuit 4 performs comparison at the period of clock 56 and stores the compressed data of maximum and minimum values internally. Consequently, the peak value detection circuit can also serve as a clock control circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform storage device such as a digital oscilloscope.

[0002]

2. Description of the Related Art An analog input signal is sampled at high speed and AD-converted into digital data, and the peak values (that is, maximum and minimum values: hereinafter referred to as peak values) of the digital data within an arbitrary time are successively detected. By storing and displaying, so-called glitch extraction for extracting extremely high-speed noise that cannot be extracted by normal sampling, or envelope measurement and aliasing can be extracted. Such a well-known technique is disclosed in, for example, Japanese Patent Publication Sho 58.
-47661.

Further, by using a large-capacity memory in the above storage, the input signal can be stored for a longer time, and a necessary portion can be selected and displayed on the display. However, when the selected data has a large capacity, it takes time to transfer and display the data. Therefore, by compressing the data during the data transfer, the data transfer and display can be completed in a short time. As a data compression method, it is known to extract the maximum value and the minimum value for each unit time in the data to be compressed and display this as compressed data. That is, the same processing peak value detection as described above is performed.

FIG. 4 shows the configuration of a conventional waveform storage device.

1 is an input terminal for an analog input waveform signal, 2
Is an amplifier that amplifies the analog input waveform signal to a predetermined level. 3 is an AD converter for converting an analog input waveform signal of a predetermined level into digital data 52 at the timing of the clock 56, and 4 is the period of the clock 56 (CK1 input) for the data 52 within the period of the clock 57 (CK2 input). (See FIG. 5), and the maximum and minimum value data 53
A well-known peak value detection circuit (for example, Japanese Patent Application No. 5-266269) that alternately outputs the data 5 stores the data 53 at the timing of the clock 87 when the enable signal 60 is in the enabled state with respect to the write enable (WE) input. , The first memory which outputs the data 80 at the timing of the clock 87 when the output enable (OE) input is enabled.
A peak value detection circuit, which is a data compression circuit that alternately outputs the maximum value / minimum value data 81 by the clock 82 by comparing in the cycle of (CK1 input), 6 is a write clock 65
Is input, the data 81 is stored at this timing, and when the read clock 66 is input, the second memory outputs data 54 at this timing. The address for writing is set by the DMA controller 12 and the address for writing is set. The address is set by the microprocessor 13.
7 is a display circuit for processing and outputting a signal to the display 8, 14 is an oscillator of a clock used at the time of sampling, 16 is a time base for outputting a clock 56 and a clock 62,
17 is counted at the timing of the clock 62, and the carry signal 61 is counted after the predetermined count by the input of the trigger signal 18.
Is a switch for turning on by the microprocessor 13 and turning off by the carry signal 61, 9 is a frequency dividing circuit for outputting a clock 57 obtained by dividing the clock 62 by half, and 20 is used during data compression. A clock oscillator, a counter 21 that outputs a carry signal 83 after a predetermined count, a switch 22 that is turned on by a clock 82 and turned off by a carry signal 83, and a clock 24 that divides the clock 63 by half Frequency divider circuit, 12 clocks 63, 65,
And DM for outputting the address 67 and controlling data transfer
A controller, 13 is the cycle of the output clock 62 of the time base 16, the count value 70 of the trigger counter 17,
It is a microprocessor that sets the count value 86 of the counter 83 and controls the DMA controller 12, the display circuit, and the like.

Next, this operation will be described with reference to FIGS.

First, the sampling operation will be described.

Analog signal 5 input from the input terminal 1
0 is converted to a predetermined level by the amplifier 2 and input to the analog-digital converter 3 (ADC). The digital signal 52 converted by the conversion clock 56 is input to the peak value detection circuit 4 which is a glitch extraction circuit. The peak value detection circuit 4 compares the data within the period of the comparison range clock 57 (CK2 input) with the period of the clock 56 (CK1 input), and alternately outputs the comparison result data 53 of the maximum value and the minimum value. The comparison result data 53 is stored in the first memory 5 at the cycle of the clock 87. At this time, the write enable (WE) input of the first memory 5 is enabled and the output enable (OE) input of the first memory 5 is disabled.

Next, the data compression, transfer, and display operations will be described.

For the data stored in the first memory 5, the DMA controller (direct memory access) 12 controlled by the microprocessor 13 outputs the read clock 63 (ACK) for two clocks, and the switch 22 is turned on at the second clock. Clocks 84 and 87 are applied to CK of the first memory 5 and CK1 of the peak value detection circuit 23, and are input to the peak value detection circuit 23. The peak value detection circuit 23, which is a data compression means for equalization, uses a clock 84.
The comparison is performed in the cycle of (CK1 input), and the carry signal 83 of the counter 21 which internally stores the compressed data of the maximum value and the minimum value and counts with the same clock 84 turns off the switch 22 to stop the comparison operation. The carry signal 83 of the counter 21 is also sent to the REQ (DM
A request signal) to notify that the compression of one display data has been completed. The maximum value and the minimum value of the compressed data 81 in the data for the number of counts are transferred by the two clocks of the read clock 63 (ACK) and are stored in the second memory 6. Then, similarly to the above, the switch 22 is turned on at the second clock and the comparison operation and the data transfer are repeated until the transfer of the number of data set in the DMA controller 12 by the microprocessor 13 is completed. The data stored in the second memory 6 is sent to the display circuit 7 by the microprocessor 13 and displayed as a waveform by the display 8.

[0011]

In the above-mentioned conventional system,
It has the following disadvantages.

First, it is necessary to insert the peak value detection circuit and the peak value detection circuit, which is the data compression means, in two places, between the AD converter and the first memory and between the first memory and the second memory. The clock control counter and the like are also required in two circuits, and the circuit becomes large in scale.

Secondly, the peak value detection circuit and the data compression means normally use a gate array or the like. The peak value detection circuit uses an expensive high speed device according to the sampling speed, and the data compression means uses the data transfer speed. You are using the appropriate device. Here, if the data compression means is operated at a higher speed, the time for data compression is reduced, data can be transferred at high speed, and the display can be updated quickly. However, it still requires the use of expensive high speed devices.

Thirdly, as the comparison clock (CLK1), in the case of the peak value detection circuit, a high speed clock at the time of maximum sampling is usually used, and in the case of the data compression means, a clock by an oscillator different from the sampling is used. Therefore,
The number of clocks increases and the generation of unnecessary radio waves increases.

[0015]

According to the present invention, one peak value detection circuit is used, and during sampling, the maximum and minimum values of the output data of the AD converter are extracted and stored in the first memory for glitch extraction. During data transfer, the maximum value and the minimum value of the output data of the first memory are extracted and the data is compressed. Further, a clock control counter or the like is commonly used by a time base and a trigger counter used at the time of sampling.

That is, according to the present invention, the peak value detection circuit and the peak value detection circuit and the clock control circuit used as the data compression means are commonly used.

As a result, only one peak value detection circuit and clock control circuit are needed, and high-speed transfer of large-capacity data using a high-speed sampling clock is possible.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment of the present invention is shown in FIG.
This will be described with reference to 2 and 3.

1 is an input terminal for an analog input waveform signal, 2
Is an amplifier which amplifies the analog input waveform signal to a predetermined level, and 3 is an A which converts the analog input waveform signal of the predetermined level into digital data 52 at the timing of a clock 56.
The D converter 4 outputs the output data 52 of the AD converter within the cycle of the clock 57 (CK2 input) to the clock 56 (CK
It is a peak value detection circuit that is a peak value detection circuit that alternately outputs the maximum value and the minimum value data 53 by comparing the output data 52 of the first memory 5 with the clock 56 (CK1 input). ), The peak value detection circuit serves as a data compression means for alternately outputting the maximum value / minimum value data 53 by the clock 57. When the enable signal 60 is in the enable state for the write enable (WE) input, data 53 is stored at the timing of the clock 62, and when the enable signal 60 is in the enable state for the output enable (OE) input, the data 52 is stored at the timing of the clock 62. The first memory, which outputs the data, 6 receives the data 53 at this timing when the write clock 65 is input.
Is stored and the data 54 is output at this timing when the read clock 66 is input, and the write address is set by the DMA controller 12 and the read address is set by the microprocessor 13. 7 is a display circuit for processing and outputting a signal to the display 8, 14 is an oscillator of a clock used at the time of sampling and data compression, 16 is a clock 56 and a clock 6.
2 is a time base that outputs 2, and 17 is a trigger counter that counts at the timing of the clock 62 at the time of sampling and outputs the carry signal 61 after a predetermined count when the trigger signal 18 is input. Operates as a counter that outputs. 15 is the microprocessor 13 or the clock 57
Is turned on by the carry signal 61 and turned off by the carry signal 61.
A frequency divider circuit that outputs a clock 57 divided by 2, 12 is a DMA controller that outputs clocks 63 and 65, and an address 67 to control data transfer, 13 is a period of the output clock 62 of the time base 16, a trigger counter 1
7 is a microprocessor that sets the count value 70 of 7, the count value 86 of the counter 83, and controls the DMA controller 12, the display circuit, and the like.

Next, this operation will be described with reference to FIGS.

First, the sampling operation will be described.

Analog signal 5 input from input terminal 1
0 is converted to a predetermined level by the amplifier 2 and input to the analog-digital converter 3. The digital signal 52 converted by the conversion clock 56 is input to the peak value detection circuit 4, which is a peak value detection circuit. At this time, the output enable (OE) of the ADC 3 is in the enabled state and the first
The output enable (OE) of the memory 5 is in a disabled state. The peak value detection circuit 4 compares the data within the period of the comparison range clock 57 (CK2 input) with the period of the clock 56 (CK1 input), and alternately outputs the comparison result data 53 of the maximum value and the minimum value. The comparison result data 53 is stored in the first memory 5 at the cycle of the clock 62. At this time, the write enable (WE) input of the first memory 5 is in the enable state.

Next, regarding data compression, transfer, and display operation, at this time, the output enable (OE) of the ADC 3 is performed.
Is disabled and the output enable (OE) of the first memory 5 is enabled. As for the data stored in the first memory 5, the DMA controller (direct memory access) 12 controlled by the microprocessor 13 outputs the read clock 63 (ACK) for two clocks, and the switch 15 is turned on at the second clock to turn on the first memory. Clocks 56 and 62 are applied to the CK of No. 5 and CK1 of the peak value detection circuit 4 and input to the peak value detection circuit 4. At this time, the clocks 56 and 62 have the same cycle.
The peak value detection circuit 4 serving as the data compression means is switched by the carry signal 61 of the counter 17 which compares the data in the cycle of the clock 56 (input of CK1) and stores the compressed data of the maximum value and the minimum value internally and counts the clock 62. 15 is turned off and the comparison operation is stopped. The carry signal 61 of the counter 17 is also sent to the REQ (DM
A request signal) to notify that the compression of one display data has been completed.

Compressed data 53 in the data for the number of counts
The maximum value and the minimum value are transferred by the two clocks of the read clock 63 (ACK) and stored in the second memory 6. Then, again, similarly to the above, the switch 15 is turned on at the second clock and the comparison operation and the data transfer are repeated until the transfer of the number of data set in the DMA controller 12 by the microprocessor 13 is completed. The data stored in the second memory 6 is sent to the display circuit 7 by the microprocessor 13.
And is displayed on the display 8 as a waveform.

[0025]

According to the present invention, glitch extraction and data compression can be performed without using a plurality of peak value detection circuits, clock oscillation circuits, clock control counters, etc., and the circuit can be simplified. Furthermore, this reduces the clock frequency and minimizes the generation of unnecessary radio waves. Also, data compression can be done by a high-speed sampling clock,
It enables high-speed transfer of large amounts of data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a sequence chart at the time of sampling according to an embodiment of the present invention.

FIG. 3 is a sequence chart at the time of data compression and transfer according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional method.

FIG. 5 is a sequence chart of a conventional method during sampling.

FIG. 6 is a sequence chart of data compression and transfer in the conventional method.

[Explanation of symbols]

3 ADC, 4 peak value detection circuit, 5 1st memory,
6 second memory, 7 display circuit, 8 display device, 12 D
MA controller, 13 microprocessors, 14
Oscillator, 16 time base, 17 trigger counter

Claims (1)

[Claims] 1. In a waveform storage device, an AD converter for converting an input signal into digital data, and a peak value for detecting a peak value within a unit time from the input signal converted into digital data by the AD converter. A detector and at least two first and second memories connected in parallel to the next stage to store the peak value detected by the peak value detector, and the output of the first memory is A waveform storage device characterized in that the peak value in a unit time is detected again from the output value from the first memory by inputting again to the peak value detector, and stored in the second memory.