JP2714535B2 - Digital waveform recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording device such as a digital oscilloscope for recording a waveform of an observed signal as a digital signal.

[0002]

2. Description of the Related Art A main component of a device for digitally recording a waveform, such as a digital oscilloscope, is an IC memory.
An address circuit is indispensable for a memory used in a conventional recording apparatus, and an address circuit is always required when writing and reading waveform data, and these circuit scales occupy a large proportion. To solve this problem, a serial memory such as a line memory or a field memory related to television is used instead of the memory. These memories have built-in address circuits, and do not require a write / read address circuit for writing and reading waveform data. This makes it possible to reduce the circuit scale and simplify control.

FIG. 4 shows an example of a conventional digital recording apparatus for waveforms. In the figure, 1 is an input waveform signal, 2 is A /
D converter, 3 is a waveform data memory, 4 is a μCPU, 5 is a display memory, 6 is a clock generator, 7 is a sampling counter, 8 is a trigger signal, 9 is a trigger circuit, 10
Is a sampling counter clock gate, 11 is a memory write clock gate, 12 is an address counter, 13
Is an address output buffer, 14 is an address counter data input buffer, and 15 is an address output buffer select gate.

In this operation, the number of data to be sampled is set in a sampling counter 7 in preparation for recording waveform data. An address counter 12 controls the write address of the memory 3 and an address output buffer 13 controls the gate 1
5 to turn off. Next, the trigger circuit 9 is enabled. All of the above settings are made from the μCPU 4. After the above preparation, when the trigger signal 8 is input, the trigger circuit 9 is triggered, the gate 10 is turned on, the clock from the clock generator 6 is transmitted to the sampling counter 7, and the sampling counter 7 counts down. During this time, the A / D converter 2 performs analog-to-digital conversion using the clock from the clock generator 6 and transmits digital data to the memory 3. The write clock is transmitted to the memory 3 through the gate 11, and the digital data is written to the memory 3. On the other hand, memory 3
The address is counted up by the address counter 12 by the clock passed through the gate 11 and transmitted to the memory 3. Digital recording of waveform data is performed by a series of operations as described above. Next, when the sampling counter 7 reaches the terminal count, the clock gate 1
1 is turned off, and the write operation of the memory 3 is stopped. Further, the clock of the address counter 12 also stops. In this state, the μCPU 4 reads the status of the sampling counter 7 and detects the end of writing. μCP
When U4 detects the end of writing, the address counter 12
Is read through the input buffer 14. Next, the output of the address counter 12 is turned off and the output buffer 13 is turned on so that the address of the memory 3 is controlled by the μCPU 4. In this state, the μCPU 4 transmits a predetermined address and a data read clock to the memory 3, reads digital waveform data, and transfers the digital waveform data to the display memory 5. As described above, the address control of the memory 3 is complicated.
Yes, it takes time to read and write
Instead, the control circuit had a large circuit scale.

[0005]

The above-mentioned prior art has the disadvantage that the scale of the address control circuit of the memory becomes large and the control becomes complicated. An object of the present invention is to simplify the address control circuit to solve this drawback and to simplify the control.

[0006]

In order to achieve the above object, the present invention focuses on the fact that a serial access memory such as a line memory or a field memory for television has an address control circuit built therein, and It is used in place of a conventional waveform data memory, simplifies an address control circuit, and simplifies control.

[0007]

As a result, the memory address control circuit of the waveform data recording circuit becomes unnecessary, and the circuit scale can be reduced and the memory control can be simplified.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below using a digital storage oscilloscope as an example with reference to FIGS.

FIG. 1 is a block diagram of an embodiment, FIG. 2 is a block diagram of a serial memory, and FIG. 3 is a flowchart of a CPU.

1 is an input waveform signal to be observed, 2 is an A / D converter, 15 is a serial memory, 4 is a μCPU, and 5 is a display memory, which is connected to a display such as a CRT (not shown).
Reference numeral 6 denotes a clock generator, 7 denotes a sampling counter, 8 denotes a trigger signal, 9 denotes a trigger circuit, 10 denotes a sampling counter clock gate, 11 denotes a serial memory write clock gate, and 12 denotes a serial memory read clock gate.

In this operation, first, the number of data to be sampled is set in the sampling counter 7 in preparation for recording waveform data. Next, as shown in the flowchart of FIG.
U4 enables the trigger circuit 9 as a trigger enable. This and
As shown in the flowchart of FIG.
15 resets the write and read / write addresses to "0"
And the write clock from the clock generator 6 is
The data is supplied to the serial memory 15 through the gate 11 and
Start writing data. The above settings are made from the μCPU 4.

After the above preparation, when the trigger signal 8 is input, the trigger circuit 9 is triggered, turns on the gate 10, and the clock from the clock generator 6 is transmitted to the sampling counter 7 to start counting down. During this period the A / D converter 2 is clocked by the input waveform signal A / D converted from the clock generator 6, digital
The data 1 ′ is transmitted to the serial memory 15.
During this time, as shown in the flowchart of FIG.
Write clock to serial memory 15 through gate 11
And the serial memory 15 stores the data
Writing continues (see the operation of the serial memory in FIG. 3).
See). On the other hand, the write address of the serial memory 15 is
Count up by the storage counter.

Since the write clock is transmitted through the gate 12 for the read address, the read address is also counted up simultaneously with the write operation.

Next, when the sampling counter 7 reaches the terminal count, the clock gate 11 is turned off, and the write operation of the serial memory 15 stops. In this state, the μCPU 4 reads the status of the sampling counter 7 and detects the end of writing. And μ
From this state, the CPU 4 transfers a predetermined number of read clocks of the serial memory 15 to the display memory 5 by transmitting the read clock to the serial memory 15 through the gate 12.
FIG. 3 is a flowchart showing the processing of the μCPU 4 and the serial
4 shows an operation flowchart of the memory 15. You
That is, the serial memory 15 has read and write addresses.
After reset, as described above, the trigger enable
Sampling starts from before, and both addresses are
I'm up. For this reason, the write
Read the data sequentially from the address following the dress
Display waveform data can be obtained in chronological order from old data.
Wear. With the above series of operations, waveform data is recorded,
It can be moved to the display memory.

The structure of the serial memory 15 is as shown in FIG. 2, where 1 'is digital input data and 16 is an input buffer.
17 is a memory, 18 is its output buffer, and 19 is a
20 is the write address counter, 21 is the write clock
The read clock 22 is a read address counter, 23
Is output data.

A feature of such a known serial memory is that it has a built-in write address counter 20 and a read address counter 22, each of which has a write clock 1.
9 or serially independently operated by the read clock 21. That is, read while writing
Can be served.

In a write clock operation of the serial memory, a write address counter 20 is operated by a write clock 19, a write address is designated for the memory 17, and input data 1 'is transmitted to the memory 17 through the input buffer 16 to write data. . When the write clock 19 is input again, the write address counter 20 increments the write address of the memory 17. In this manner, the time-series data is sequentially stored in the memory 17.

On the other hand, in the read operation, similarly, the read address counter 22 is operated by the read clock 21 to designate a read address for the memory 17, and the read data is output as output data 23 through the output buffer 18. When the read clock 21 is input again, the read address counter 22 increments the read address of the memory 17. In this manner, the time-series data of the memory 17 is sequentially read by the read clock 21.

As described above, because of the operation,
One of the well-known oscilloscope operating modes
In one roll mode, the present invention
The control process has the feature that it can be read.
Easy to read data without interruption
This is particularly effective. The serial memory is a well-known memory that has been developed for storing and reading out television signals at high speed, and is suitable for storing time-series data in order.

The serial memory includes a line memory for storing data for one scanning line for a digital television or a VTR, and a field memory for storing data for one screen.

[0021]

According to the present invention, the address control circuit of the waveform memory becomes unnecessary, the circuit scale around the waveform memory can be reduced, the control is simple, and the write and read operations are simple.
Time can also be reduced. As a result, the digital strike
A waveform data recording and playback device such as a radio oscilloscope
Value, light weight, small size, and high speed.
it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a serial memory used in an embodiment of the present invention;

FIG. 3 is an operation flowchart of a μCPU used in an embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

2 A / D converter, 3 memory, 4 μCPU, 5 display memory, 7 sampling counter, 12 address counter, 13 address output buffer gate, 14
Address counter value input buffer gate, 15 serial memory

Claims (1)

(57) [Claims] 1. An A / D converter for converting an input signal into a digital signal.
A D conversion circuit, a serial memory having a write address counter and a read address counter to which a digital signal from the A / D conversion circuit is applied, and a sampling counter for setting a sample amount of the digital signal to be taken into the serial memory A trigger circuit that responds to the input signal and controls the start of counting by the sampling counter; a display memory that stores the digital signal read from the serial memory; and a display memory that stores the digital signal. A digital recording device for waveforms, comprising: a write address counter and a read address counter; and a control device for controlling the sampling counter and the trigger circuit.