JPH09146779A - 改善されたタイマ能力を有する集積回路入力／出力プロセッサ - Google Patents

改善されたタイマ能力を有する集積回路入力／出力プロセッサ

Info

Publication number
JPH09146779A
JPH09146779A JP8315630A JP31563096A JPH09146779A JP H09146779 A JPH09146779 A JP H09146779A JP 8315630 A JP8315630 A JP 8315630A JP 31563096 A JP31563096 A JP 31563096A JP H09146779 A JPH09146779 A JP H09146779A
Authority
JP
Japan
Prior art keywords
channel
timer
bus
pin
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8315630A
Other languages
English (en)
Japanese (ja)
Inventor
Vernon B Goler
バーノン・バーナード・ゴーラー
Gary L Miller
ゲイリー・リン・ミラー
David Rivera
デービッド・リベラ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH09146779A publication Critical patent/JPH09146779A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Electronic Switches (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
JP8315630A 1995-11-13 1996-11-12 改善されたタイマ能力を有する集積回路入力／出力プロセッサ Pending JPH09146779A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/555,456 US5634045A (en) 1995-11-13 1995-11-13 Integrated circuit input/output processor having improved timer capability
US08/555,456 1995-11-13

Publications (1)

Publication Number Publication Date
JPH09146779A true JPH09146779A (ja) 1997-06-06

Family

ID=24217325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8315630A Pending JPH09146779A (ja) 1995-11-13 1996-11-12 改善されたタイマ能力を有する集積回路入力／出力プロセッサ

Country Status (6)

Country Link
US (1) US5634045A (enExample)
EP (1) EP0773491A3 (enExample)
JP (1) JPH09146779A (enExample)
KR (1) KR100459738B1 (enExample)
CN (1) CN1159619A (enExample)
TW (1) TW309603B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812833A (en) * 1995-11-13 1998-09-22 Motorola, Inc. Timer bus structure for an integrated circuit
US6233636B1 (en) 1998-12-03 2001-05-15 International Business Machines Corporation Method and system for allowing PCI bus transactions to be performed at higher operating frequencies
GB2369751A (en) * 2000-11-30 2002-06-05 Nokia Mobile Phones Ltd Communication of data
US7024579B2 (en) * 2002-08-27 2006-04-04 Stmicroelectronics S.R.L. Configurable timing system having a plurality of timing units interconnected via software programmable registers
JP4994254B2 (ja) * 2007-03-08 2012-08-08 ルネサスエレクトロニクス株式会社 データプロセッサ及び制御システム
KR102683747B1 (ko) * 2019-01-22 2024-07-11 에스케이하이닉스 주식회사 반도체 메모리 장치
US11366488B1 (en) 2021-05-20 2022-06-21 Nxp Usa, Inc. Timer for use in an asymmetric mutli-core system
CN115047852A (zh) * 2022-06-16 2022-09-13 神龙汽车有限公司 一种车辆软件刷写方法和系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103507B2 (ja) * 1984-11-02 1994-12-14 株式会社日立製作所 パルス入出力プロセッサ及びそれを用いたマイクロコンピュータ
US4926319A (en) * 1988-08-19 1990-05-15 Motorola Inc. Integrated circuit timer with multiple channels and dedicated service processor
US5042005A (en) * 1988-08-19 1991-08-20 Motorola, Inc. Timer channel with match recognition features
US5129078A (en) * 1988-08-19 1992-07-07 Groves Stanley E Dedicated service processor with inter-channel communication features
US4942522A (en) * 1988-08-19 1990-07-17 Motorola, Inc. Timer channel with multiple timer reference features
US5117498A (en) * 1988-08-19 1992-05-26 Motorola, Inc. Processer with flexible return from subroutine
US4952367A (en) * 1988-08-19 1990-08-28 Motorola, Inc. Timer channel for use in a multiple channel timer system
US5535376A (en) * 1993-05-18 1996-07-09 Motorola, Inc. Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor

Also Published As

Publication number Publication date
EP0773491A3 (en) 1998-11-04
EP0773491A2 (en) 1997-05-14
KR100459738B1 (ko) 2005-04-19
KR970028966A (ko) 1997-06-26
CN1159619A (zh) 1997-09-17
TW309603B (enExample) 1997-07-01
US5634045A (en) 1997-05-27

Similar Documents

Publication Publication Date Title
US5434996A (en) Synchronous/asynchronous clock net with autosense
US5469548A (en) Disk array controller having internal protocol for sending address/transfer count information during first/second load cycles and transferring data after receiving an acknowldgement
EP1124179B1 (en) An apparatus for signal synchronization between two clock domains
JP4384819B2 (ja) 弾性インターフェース装置およびそのための方法
EP0664907B1 (en) Disk array controller utilizing command descriptor blocks for control information
US5822381A (en) Distributed global clock system
EP0453199A2 (en) Computer system with synchronous bus
CA2291276A1 (en) Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method
US5729721A (en) Timebase synchronization in separate integrated circuits or separate modules
US6055597A (en) Bi-directional synchronizing buffer system
US5422914A (en) System and method for synchronizing data communications between two devices operating at different clock frequencies
JP2002539526A (ja) 動的ウェーブパイプライン式インターフェース装置およびその方法
EP0980040B1 (en) Pseudo lockstep data processing system
US5812833A (en) Timer bus structure for an integrated circuit
WO2001093052A2 (en) Multiprotocol computer bus interface adapter and method
US5699529A (en) Work station or similar data processing system including interfacing means to a data channel
JPH09146779A (ja) 改善されたタイマ能力を有する集積回路入力／出力プロセッサ
EP0463775B1 (en) Multiple speed expansion card
EP1396786A1 (en) Bridge circuit for use in retiming in a semiconductor integrated circuit
Yun et al. A high-performance asynchronous SCSI controller
US6675249B2 (en) Information processing equipment and information processing system
US5721889A (en) Data transfer between integrated circuit timer channels
US7100065B2 (en) Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller
US5631853A (en) Flexible configuration of timebases in a timer system
KR100963706B1 (ko) 데이터 전송 방법, 데이터 전송 브리지 및 고속 데이터전송 장치

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20041217

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050324

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050906

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20051206

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20051214

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060704