JPH09146498A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display image data formed out of a smaller number of horizontal scanning lines than the horizontal scanning lines of a liquid crystal display panel without any deterioration of image quality by making a selection between an output signal from an image processing circuit and an output signal from a margin part display data generation circuit. SOLUTION: Regarding an image signal fed to an input terminal 11, an image data processing circuit 21 converts the image signal to such data as suitable for drive with a signal line driver 3. A margin part display data generation circuit 22 generates a margin part display image data, when image data with a smaller number of horizontal scanning lines than the horizontal scanning lines of a liquid crystal display panel is inputted. Furthermore, an output selector circuit 23 selects output signals between the circuits 21 and 22, on the basis of a control signal from a control circuit 25. Also, a weighting circuit 24 applies the prescribed amount of weight to data outputted from the circuit 22. According to this construction, a correction is made for the change of display color resulting from a shortage of time for writing on a liquid crystal cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a device capable of displaying video signals of a plurality of signal standards, such as a multi-scan type display device. The present invention relates to a liquid crystal display device capable of displaying a video signal composed of the number of lines without variation in luminance.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been put to practical use in personal computers, word processors, color televisions, etc., taking advantage of their features such as thinness, low voltage, and low power consumption as substitutes for CRT displays.

For this reason, in order to make the active matrix type display device more general-purpose, it is necessary that one liquid crystal display device can display various video signals generally used at present.

When one liquid crystal display device supports two or more kinds of video signals, the signal format of the video signal having the largest image data amount is determined by the difference in the image data amount of the video signal.
The pixel size of a liquid crystal display panel is often matched.

However, when the pixel size of the liquid crystal display panel is adjusted to the video signal having the largest amount of image data, when other video signals are displayed on the liquid crystal display panel, effective image data of the video signal is allocated. In other words, there is a case where a blank portion is generated, and the same image is displayed more than once on the same screen.

Therefore, conventionally, the following method has been reported as a method for displaying the blank portion, particularly as a processing method in the scanning line direction.

Conventionally known means for displaying a blank portion uses data of a vertical blanking period of a video signal, and the scanning speed of a scanning line driver for the blank portion is increased by several times that of a normal scanning line. A driving method is reported in JP-A-1-158490. However, in this method, since the scanning speed of the scanning line driver is several times, the data writing time to the liquid crystal cell is shortened, and there is a problem that the display color is changed depending on the response of the liquid crystal cell.

Therefore, as a countermeasure for this, the following prior art, Japanese Patent Laid-Open No. Hei 5-188885, has been reported.
FIG. 7 is a block diagram showing the entire circuit configuration of the conventional liquid crystal display device.

As an example of a signal processing circuit of a conventional liquid crystal display device, a configuration shown in FIG. 7 is known. As shown in the figure, a signal processing circuit of a conventional liquid crystal display device includes a scan driver 81 for driving gate pulses 12-1 to 12 -M of a liquid crystal display panel 71 and a data bus 13-of the liquid crystal display panel 71. 1 to 13-N.

The data driver 91 holds digital image data for one horizontal line, selects a voltage corresponding to the digital image data, and supplies the selected voltage to data buses 13-1 to 13-N connected to the drains of the TFTs in the liquid crystal display panel 71. And a voltage selector 92, a data holding unit 93, a latch 94, and a control unit 95.

The voltage selector 92 includes a data driver 91
The voltage level corresponding to the digital data DATA input to the plurality of data voltages dat
a and outputs the data to the data buses 13-1 to 13-N.

The data holding unit 93 includes a liquid crystal display panel 71
, And controls ON / OFF of the output of the data voltage to the data buses 13-1 to 13-N. The latch 94 latches the digital data DATA input to the data driver 91 by being divided into several bits at a corresponding position (pixel) on one line, and holds the data when one line is completed. Output to the unit 93 at once.

The control unit 95 controls the operation of the latch 94 when latching the input digital image data DATA in the latch 94.

The scan driver 81 has gate buses 12-1 to 12-1 connected to the gates of TFTs arranged on a horizontal line.
2-M, the TFT is turned on, and the data bus 13-
The data voltage data applied to the liquid crystal cells is supplied to the liquid crystal cells.
And a control unit 84.

The output circuit 82 level-shifts the ON / OFF data of each of the gate buses 12-1 to 12-M input from the latch 83 to a separately input voltage of Vgon and Vgoff, and outputs an output enable signal. / OE controls the output. Latch 83 is connected to all gate buses 12-
The ON / OFF data of 1 to 12-M is held by the latch enable signal / LE. Further, the control unit 84 converts ON / OFF data of the gate buses 12-1 to 12-M input as serial data from the serial input terminal SI into
The shift registers from the upper side to the lower side of the screen having the same number of bits as all the gate buses 12-1 to 12-M are held by the rising edge of the clock signal CLK and latched at once.
Output to 3. The output enable signal / OE and the latch enable signal / LE are signals generated by the timing controller (not shown) by the horizontal synchronization signal Hsync and the dot clock signal DCLK.
As a signal notation, a negative logic signal is prefixed with "/".

To explain the operation of this conventional example, for example,
It is assumed that 400 lines of image data are displayed on the 480 line liquid crystal display panel 71. As shown in FIGS. 8A and 8B, the specification of the display image data is such that, during one cycle of the vertical synchronization signal Vsync, the horizontal synchronization signal DHsync is used only for 24 periods as one screen data. It is assumed that the blank data Bl is transferred, followed by the image data A for 400 periods, and the blank data B2 is transferred for the next 16 periods. FIG. 8 (a)
On the liquid crystal display panel 71, 40 horizontal lines from the top are displayed in the non-display area D1 (blank data is displayed), and then 400 horizontal lines are displayed in the image data display area C on the liquid crystal display panel 71, as shown in FIG. Subsequently, 40 horizontal lines are displayed as the non-display area D2.

For such a display image, the signal processing circuit of this conventional liquid crystal display device uses a liquid crystal display panel 71.
When displaying image data having a smaller number of horizontal lines than the number of horizontal scanning lines included in the image data, an attempt is made to use a blanking data area of the image data and display the data by interlace driving.

In this conventional example, horizontal synchronization is performed on a data portion A of image data (horizontal synchronization signal Hs).
The image data is displayed in the display area C of the liquid crystal display panel 71 (assuming that “sync = DHsync”).
And B2 are displayed in the non-display areas Dl and D2 at the timing shown in FIG.

That is, the frequency and phase of the horizontal scanning of the non-display area Dl or D2 are adjusted so that the vertical synchronization of the image data and the vertical synchronization of the liquid crystal display panel 71 coincide with the time of the blank portion Bl or B2 of the image data. Drive. However, the horizontal synchronization signals H in the non-display areas Dl and D2
If the frequency of the sync becomes too fast, the data voltage da
Since the charging of the liquid crystal cell by ta cannot be made in time,
The non-display areas Dl and D2 are driven by the horizontal synchronization signal Hsy.
One line (j-th line) in time for two cycles of nc '
Is displayed, the next line is skipped, and the next line (j
(Twelfth line) is displayed. Then, after displaying one frame, in the next frame, the line jumped over in the previous frame is displayed, and the line displayed in the previous frame is jumped over for screen display.

By this means, the scanning speed of the scanning line driver in the non-display areas D1 and D2 becomes the same as that of the ordinary scanning line C, and the writing time to the liquid crystal cell is improved. However, on the other hand, due to the use of a driving method called interlacing, charge exchange in one pixel is 2
Since the time required for DC charges to accumulate in the pixel becomes longer for each frame, a problem of causing image quality deterioration such as a change in display color is expected. Also, this means limits the data format of the video signal because it uses data in the blanking period of the video signal, as in the general conventional example, and is disadvantageous in practice.

[0021]

Conventionally, when a single liquid crystal display device responds to a plurality of input signals, for example, when image data having a smaller number of horizontal lines than the number of horizontal scanning lines of the liquid crystal display panel is displayed. The liquid crystal display panel is displayed by utilizing the data of the blanking period of the video signal as the display signal in the blank area, and adopting interlace driving so that electric charges can be sufficiently accumulated in the liquid crystal cell.

However, according to this means, data is restricted in the blanking period of the video signal, and since the driving method called interlacing is used, the exchange of the electric charge in one pixel becomes every two frames, and the DC electric charge in the pixel is reduced. However, there is a problem that image quality is degraded because the time required for the image data to be stored becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. Even when displaying image data having a smaller number of horizontal lines than the number of horizontal scanning lines of the liquid crystal display panel, the liquid crystal in the margin area is displayed. For the cell, without using the data of the blanking period of the video signal, cover the display of the part by the data generation circuit dedicated to the margin part, furthermore, if there is a possibility that a problem occurs during the writing time, It is an object of the present invention to provide a liquid crystal display device that prevents a change in display color due to a shortage of writing time by weighting data from a data generating circuit dedicated to the margin.

[0024]

In order to solve the above-mentioned problems, a liquid crystal display device of the present invention includes an active matrix liquid crystal display panel, a scanning line driver for driving a gate bus of the liquid crystal display panel, and a liquid crystal display. A signal line driver that drives a data bus of a display panel, a display signal control circuit that converts a video signal into a signal that can be driven by the signal line driver, and generates a timing signal necessary for the scanning line driver and the signal line driver. In a liquid crystal display device including: a display signal control circuit, an image data processing circuit that performs data processing of a video signal; and a blank area display that generates data that covers the display of the blank area when the blank area occurs. The data generation circuit and the data from the margin display data generation circuit can be weighted according to the scanning speed of the scanning line driver. A weighting circuit, an output switching circuit that switches the outputs of the image data processing circuit and the weighting circuit, and a control circuit that controls the timing of the image data processing circuit, the margin display data generating circuit, and the output switching circuit. By displaying the number of horizontal lines less than the number of horizontal scanning lines of the liquid crystal display panel, the output from the image data processing circuit that processes the video signal and the extra horizontal scanning lines (Margin area) The output from the blank space display data generating circuit for display is switched to perform display on the liquid crystal display panel. Further, the second feature of the present invention is that when the scanning speed of the scanning line driver is increased for display, the writing time to the liquid crystal cell is shortened and a change in display color is expected depending on the response speed of the liquid crystal cell. The output data from the blank space display data generating circuit is weighted and the liquid crystal display panel is displayed so as to correct the change in display color.

A third feature of the present invention is that a margin display data generation circuit is provided as a margin display means, and the margin display data generation circuit is constituted by, for example, a memory. The data written in the memory is read out in synchronization with the vertical synchronizing signal, so that the display of the blank area can be displayed in a specific color or pattern.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the overall configuration of a liquid crystal display device according to a first embodiment of the present invention. As shown in the figure, an active matrix type liquid crystal display panel 1 to be driven is composed of a TFT array.
The voltage applied between the drain line of the FT and the common electrode is
Applying to the liquid crystal cell by turning on the TFT,
The amount of light passing through the liquid crystal cell is selectively blocked by the amount of the applied voltage.

In the present invention, as an example, 480 scan lines are used.
A case where the entire system is processed by analog signals using a liquid crystal display panel of a line will be described.

In contrast to the liquid crystal display panel 1, the liquid crystal display device of the present embodiment includes a scanning line driver 2 for driving a gate bus of the liquid crystal display panel 1 and a liquid crystal display panel 1.
And a display signal control circuit 4 that outputs data to the signal line driver 3 and controls the timing of the scanning line driver 2 and the signal line driver 3. .

The scanning line driver 2 uses a gate bus connected to the gates of the TFTs arranged on the horizontal scanning line to control the TFTs.
Is turned on, and the data voltage applied to the drain bus is supplied to the liquid crystal cell. The timing for turning on the TFT is controlled by a timing signal from the display signal control circuit 4.

When the analog driver is used, the signal line driver 3 holds the image data for one horizontal scanning line as an analog amount.
The held voltage is directly applied to the drain bus connected to the drain of T.

The timing of supply to the drain bus of the TFT is controlled by the timing signal from the display signal control circuit 4.

The display signal control circuit 4 converts a video signal supplied to the input terminal I1 (generally, a video signal supplied from the system side) into data that can be driven by the signal driver 3 in the subsequent stage. The timing control of the scanning line driver 2 and the signal line driver 3 is performed.

FIG. 2 is a detailed block diagram of the display signal control circuit. As shown in FIG. 2, the display signal control circuit includes an image data processing circuit 21, a margin display data generation circuit 22, an output switching circuit 23, and a weighting circuit 2.
4 and a control circuit 25. In addition, FIG.
It is described assuming that signal processing is performed using analog signals.

The image data processing circuit 21 has an input terminal Il
Is converted into data that can be driven by the signal line driver 3 at the subsequent stage. For example, in this case, the supplied video signal is expanded to a half frequency to reduce the operating frequency. ing. When image data having a smaller number of horizontal lines than the number of horizontal scanning lines of the liquid crystal display panel 1 is input, the margin display data generating circuit 22 generates the margin display image data, and performs output switching at a subsequent stage. When the data becomes valid in the circuit 23, the data is output to the signal line driver. The output switching circuit 23 enables the output of the image data processing circuit 21 or the output of the margin display data generation circuit 22 according to a control signal from a control circuit 25 in the display signal control circuit 4. Is switched.

The weighting circuit 24 weights the data output from the margin display data generating circuit 22 by an amount of 10.alpha., And writes the data into the liquid crystal cells when the scanning speed of the scanning line driver increases. A change in display color due to a shortage of time is corrected (see FIG. 5).

The control circuit 25 includes the scanning line drivers 2 and
The horizontal synchronizing signal (Hsync) to be input is provided when the timing control of the image data processing circuit 21, the margin display data generating circuit 22, the output switching circuit 23 and the weighting circuit 24 in the signal line driver 3, the display signal control circuit 4 is performed. ),
Vertical sync signal (Vsync) and dot clock (DC
LK) signal to generate timing signals for all the blocks.

In describing the operation of the present embodiment, a case where 400 lines of image data are displayed on the 480 line liquid crystal display panel 1, for example, is considered.

As shown in FIG. 3A, the specification of the display image data is the vertical synchronization signal Vsy as one screen data.
It is assumed that blank data Bl of 33 horizontal lines are sent in one cycle period of nc, image data Dl are sent for a period of 400 horizontal lines, and blank data B2 of 7 horizontal lines are sent subsequently.

Further, as shown in FIG. 3C, the image data of FIG.
The horizontal lines are displayed as a blank area Hl, the 400 horizontal lines are displayed as an image data area El, and the 40 horizontal lines are subsequently displayed as a blank area H2. For the input image data as shown in FIG. 3A, the liquid crystal display device of the present embodiment displays the image data with the number of horizontal lines smaller than the number of horizontal scanning lines of the liquid crystal display panel 1 when displaying the liquid crystal display. Display data of the margin area of panel 1 (Hl, H2 in FIG. 3C)
As an area, data of the margin display data generating circuit 22 is to be used.

That is, in this embodiment, as shown in FIG. 3 (c), first, the 40 horizontal lines (Hl area) from the top are output by the output switching circuit 23 at the timing synchronized with the horizontal and vertical synchronizing signals of the image data. The data from the margin display data generating circuit 22 is controlled so as to be output to the signal line driver 3, and the H1 region is displayed.

Subsequently, on the 400 horizontal lines (El area) shown in FIG. 3C, the data of the image data D1 (FIG. 3A) input to the input terminal Il is displayed.
The output switching circuit 23 controls the data from the image data processing circuit 21 to be output to the signal line driver 3.

Subsequently, the remaining 40 horizontal lines (H2 area)
Is displayed by the same means as the method of displaying the Hl region. This output switching is controlled by an output switching signal SE shown in FIG.

When the H1 and H2 areas are displayed, if the scanning speed of the scanning line driver needs to be doubled or several times faster than the El area (FIG. 3B), FIG.
As shown in (1), the output data from the margin display data generating circuit 22 is weighted in advance by the weighting circuit 24 by an amount of 10α, and the insufficient writing to the liquid crystal cell due to the reduction of the writing time is corrected by the weighted data. Control.

By the above means, the input image data becomes 4
Even if there are only 00 horizontal lines, it is possible to display the entire liquid crystal display panel 1 having 480 horizontal scanning lines, without using blanking portions of input image data, and without causing a change in display color. Thus, the margin areas Hl and H2 of the liquid crystal display panel 1 can be displayed.

Although the above description has been made on the premise that all processing is performed by analog processing, the circuit configuration may be performed by digital processing. Also, the output switching circuit 23
By adding a circuit in which the polarity of the output signal alternates for each line and for each frame at the subsequent stage, AC drive for each line can be realized.

(Second Embodiment) FIG. 6 is a block diagram showing another specific example in which a margin display data generating circuit for generating data in a margin area is constituted by a storage unit.

In this embodiment, when displaying image data having a smaller number of horizontal lines than the number of horizontal scanning lines of the liquid crystal display panel 1, a means for displaying the Hl and H2 areas shown in FIG. The configuration of the margin display data generating circuit 22 according to one embodiment is performed using a data storage unit 61 capable of storing arbitrary data as shown in FIG. The data storage unit 6 in the margin display data generation circuit 22
Reference numeral 1 denotes a storage circuit such as a ROM, and a data storage unit 61 when the system is a digital signal processing.
The D / A converter 62 is provided at the subsequent stage of the data storage unit 61 when the system performs analog signal processing, and the signal from the D / A converter 62 is output. The configuration other than the margin display data generating circuit of the present embodiment is the same as that of the first embodiment, and the present embodiment also considers the display image data shown in FIG. 3 as in the first embodiment.

As shown in FIG. 6, by configuring the blank space display data generation circuit 22 of FIG. 2 as described above, the data that can be generated depends on the storage capacity of the storage unit, but is arbitrary (free). Accordingly, it is possible to display a plurality of colors or a specific pattern from a single color display.
The contents stored in the data storage unit 61 are controlled by a control signal from the control circuit 25.

[0050]

As described above, according to the present invention, when displaying image data having a smaller number of horizontal lines than the number of horizontal scanning lines of the liquid crystal display panel, the display of the margin area of the liquid crystal display panel is performed. By using the output from the margin display data generation circuit provided inside the display signal control circuit in advance, the display can be performed without using the blanking period data of the input video signal. .

Also, the output data of the margin display data generating circuit can be weighted, so that even if the scanning speed of the scanning line driver is several times as fast as that of a normal scanning line for displaying the margin area, the liquid crystal display The margin area of the panel can be displayed without changing the display color.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall circuit configuration of a first embodiment of the present invention.

FIG. 2 is a detailed block diagram of a display signal control circuit according to the first embodiment.

FIG. 3A shows the specifications of display image data according to the present invention, and FIG.
One scanning example, (c) a diagram for explaining a display configuration on a liquid crystal display panel

FIG. 4 is a timing chart for explaining an operation in a blank area of the liquid crystal display device of the first embodiment.

FIG. 5 is an operation explanatory diagram of a weighting circuit of the liquid crystal display device of the first embodiment.

FIG. 6 is a circuit block diagram for generating data in a blank area of the liquid crystal display device according to the second embodiment.

FIG. 7 is a block diagram showing the overall circuit configuration of a conventional liquid crystal display device.

FIGS. 8A and 8B are explanatory diagrams of a specification of display image data in a conventional signal processing circuit, and FIG. 8C is a diagram illustrating a display configuration of image data on a liquid crystal display panel.

FIG. 9 is a timing diagram illustrating an operation of a signal processing circuit of a conventional liquid crystal display device in a non-display area.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Scan line driver 3 Signal line driver 4 Display signal control circuit 21 Image data processing circuit 22 Margin display data generation circuit 23 Output switching circuit 24 Weighting circuit 25 Control circuit 61 Data storage part (ROM etc.) 62 D / A conversion unit 71 liquid crystal display panel 81 scan driver 91 data driver 121-12M gate bus 131-13N data bus

Claims (5)

[Claims] 1. An active matrix type liquid crystal display panel, a scanning line driver for driving a gate bus of the liquid crystal display panel, a signal line driver for driving a data bus of the liquid crystal display panel, and a video signal for the signal line driver. And a display signal control circuit for generating timing signals necessary for the scanning line driver and the signal line driver, and the number of horizontal scanning lines is smaller than that of the liquid crystal display panel. In a liquid crystal display device for displaying video signals of the number of horizontal lines in a blank area of an extra horizontal line, the display signal control circuit includes an image data processing circuit for performing data processing of video signals, and a horizontal line of the liquid crystal display panel. When displaying video signals with a horizontal line number that is less than the scan line number, the writing time to the liquid crystal element may change. And a margin part image data generation circuit part capable of controlling the voltage applied to the liquid crystal element so that the display color does not change, and outputs of the margin part image data generation circuit part and the image data processing circuit. The liquid crystal display device is characterized in that the entire liquid crystal display panel can be driven in an AC manner without deterioration of image quality by switching among the above in a vertical blanking period. 2. The display signal control circuit, an image data processing circuit for performing data processing of a video signal, and a display dedicated to a blank area without using a signal of a blanking period of the video signal as a display signal of the blank area. A blank area display data generating circuit that self-generates a signal, a weighting circuit that can change the weighting amount of data from the blank area display data generating circuit according to the scanning speed of the scanning line driver, and the image data processing circuit. And an output switching circuit for selecting the output of the weighting circuit, the image data processing circuit, the margin display data generating circuit, the weighting circuit, the output switching circuit, the scanning line driver, and the signal line driver. With a control circuit for supplying various timing signals, and the number of horizontal lines is less than the number of horizontal scanning lines of the liquid crystal display panel. When displaying the video signal of, by switching the data from the image data processing circuit and the weighting circuit within the vertical blanking period by the output switching circuit, without using the video signal in the vertical blanking period, The liquid crystal display device according to claim 1, wherein display of all lines of the liquid crystal display panel is possible. 3. The display signal control circuit is provided with the weighting circuit, and when the scanning speed of the scanning line driver is increased only during the display of the blank area, the display signal control circuit is for displaying the blank area according to the scanning speed. 3. The liquid crystal display device according to claim 1, wherein the output data from the data generating circuit is weighted so that the display color of the blank area does not change. 4. The display signal control circuit includes the blank space display data generation circuit, and the blank space display data generation circuit is configured to be RGB independent, so that the color tone of the blank area is optimized. The liquid crystal display device according to claim 1, 2 or 3, wherein the liquid crystal display device is controllable. 5. The display signal control circuit includes the blank space display data generation circuit, and the blank space display data generation circuit is configured by a memory or the like to display a blank area in a single color. 4. The display can be displayed in a plurality of colors or patterns.
Or the liquid crystal display device according to item 4.