JPH0519719A - Driving control circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To drive a liquid crystal display panel having large-screen constitution by applying a necessary voltage to a liquid crystal cell within specific driving time period as for the driving control circuit of the liquid crystal display device which can drive the liquid crystal cell of an active matrix type liquid crystal display panel at a high speed. CONSTITUTION:The driving control circuit of the liquid crystal display device is equipped with the active matrix type liquid crystal display panel 1, a gate driving part 2 which drives gate lines (12-1)-(12-M) of the liquid crystal display panel 1, and data driving part 3 which drives data lines (13-1)-(13-N) of the liquid crystal panel 1; and this liquid crystal display device is provided with a switching signal generation part 4 which generates a switching signal 11 for dividing the period wherein the gate line 12-j is driven by the gate driving part 2 into two periods and a driving voltage control part 5 which boosts the driving voltage (absolute value) in the 1st period of the data lines (13-1)-(13-N) to a larger voltage with the control of the switching signal 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control circuit of a liquid crystal display device, and more particularly to a drive control circuit of a liquid crystal display device for applying a required voltage to a liquid crystal cell of an active matrix type liquid crystal display panel in a short time. .

As computer systems have become more sophisticated in recent years, liquid crystal display devices are also required to have multiple colors. Therefore, there is provided a liquid crystal display device using an active matrix type liquid crystal panel instead of the conventional simple matrix type liquid crystal. This liquid crystal display device requires a high-speed drive circuit as the screen becomes larger (higher definition).

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a drive circuit of a conventional liquid crystal display device. Active matrix liquid crystal display panel 1, and gate lines 12-1 to 12-1 of the liquid crystal display panel 1
2-M for driving the gate drive unit 2 and the liquid crystal display panel 1
And the data driving unit 3 for driving the data lines 13-1 to 13-N. FIG. 7 is a configuration diagram of the liquid crystal display panel 1. In each pixel, an active element (TFT or the like) 71 is added as a switch to the liquid crystal cell 72 in a one-to-one correspondence, and data lines 13-i and gate lines 12 are provided. Driven by connecting to -j.

In this conventional small-sized liquid crystal display device, a low-speed drive circuit was used for driving, but when the screen becomes large (high definition), the low-speed drive circuit cannot keep up with the drive speed. High-speed drive circuits have been developed.

However, the width of the data line becomes narrower and the length thereof becomes longer as the definition becomes higher, so that the line resistance becomes higher and, on the other hand, the time allowed for driving one line becomes shorter. The desired voltage cannot be applied to the liquid crystal cell.

That is, as shown in FIG. 8A, the drive voltage is applied from the data line 13-i and the gate line 12-j, but the voltage actually applied to the liquid crystal cell 72 is the capacitance of the circuit. The voltage waveform changes transiently due to the capacitance of the cell capacitance and the wiring resistance. Further, as the driving circuit speeds up, as shown in FIG. 2B, the time constant becomes large and the driving time width becomes narrow, so that a desired voltage cannot be applied to the liquid crystal cell.

[0007]

Therefore, when a large-screen liquid crystal display panel is driven, desired luminance cannot be obtained, and display unevenness occurs, which causes a problem of deterioration of display quality.

An object of the present invention is to provide a drive control circuit of a liquid crystal display device capable of driving a liquid crystal display panel having a large screen by applying a voltage required for a liquid crystal cell within a predetermined drive time width. To do.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. In order to solve the above problems, a drive control circuit of a liquid crystal display device according to a first aspect of the present invention comprises an active matrix liquid crystal display panel 1 and gates for driving gate lines 12-1 to 12-M of the liquid crystal display panel 1. Drive unit 2,
Data lines 13-1 to 13- of the liquid crystal display panel 1
A drive control circuit for a liquid crystal display device, comprising: a data driver 3 for driving N, wherein the gate driver 2 is an arbitrary gate line 1 in the gate lines 12-1 to 12-M.
The drive voltage controller 5 is configured to set the drive voltage (absolute value) of the data lines 13-1 to 13-N to a higher voltage for a certain period of the period of driving 2-j.

The drive control circuit of the liquid crystal display device of the second invention is an active matrix type liquid crystal display panel 1.
And the gate lines 12-1 to 12-1 of the liquid crystal display panel 1.
A drive control circuit for a liquid crystal display device, comprising: a gate drive unit 2 for driving 2-M and a data drive unit 3 for driving the data lines 13-1 to 13-N of the liquid crystal display panel 1. The gate driving unit 2 has the gate line 12-1.
.. 12-M, a switching signal generator 4 for generating a switching signal 11 that divides a period for driving an arbitrary gate line 12-j into two periods, and data lines 13-1 to 13-1 by controlling the switching signal 11. 13-N, the drive voltage control unit 5 that sets the drive voltage (absolute value) in the first period to a higher voltage is configured.

[0011]

In the drive control circuit of the liquid crystal display device of the first and second inventions, as shown in FIG. 1, the period in which the gate drive section 2 drives the gate lines 12-1 to 12-M is divided into two periods. The switching signal generator 4 generates the switching signal 11 to be divided, and the driving voltage controller 5 controls the absolute value of the driving voltage in the first period of the data lines 13-1 to 13-N by controlling the switching signal 11. It outputs as a large voltage.

Therefore, the voltage waveform actually applied to the liquid crystal cell 72 reaches a predetermined drive voltage within a predetermined drive time width as shown in FIG. 8C, and a desired brightness can be obtained, and as a result, It can be driven without deteriorating the display quality.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a drive control circuit of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 shows a time chart of signals at respective parts. In FIG. 1, the same parts as those in FIG. 6 (conventional example) are designated by the same reference numerals.

In FIG. 1, the drive control circuit of the liquid crystal display device of the present embodiment has a liquid crystal display panel 1 formed as an active matrix type having the structure shown in FIG. 7, and a gate line 12-1 of the liquid crystal display panel 1. .About.12-M, the gate driver 2 for controlling ON / OFF of the active elements on the upper surface and the data lines 13-1 to 13-13 of the liquid crystal display panel 1.
-N, that is, the data driver 3 for applying a predetermined voltage to the liquid crystal cell 72 on the gate line selected by the gate driver 2 through the active element, and the gate line 12-j having the gate driver 2 Drive period is 2 of Ta and Tb
A switching signal generator 4 that generates a switching signal 11 that is divided into two periods, and a data line 13 that is controlled by the switching signal 11.
The voltage of -1 to 13-N is set to a voltage (absolute value) larger than the output voltage of the data driving unit 3 in the first period Ta, and the output voltage of the data driving unit 3 is kept unchanged in the period Tb to correct the data line. The drive voltage controller 5 outputs 14-1 to 14-N.

Next, the detailed circuit configuration and operation of each component will be described with reference to FIG. In the timing chart of FIG. 2, as an example, the output of the gate drive unit 2 is 4
The case of books (12-1 to 12-4) is described.

In this embodiment, the polarity of the voltage applied to the liquid crystal cell 72 is inverted every screen (one frame) by the alternating signal ACM so that the DC voltage is not continuously applied to the liquid crystal cell 72.

When the synchronization signal FRAME for each screen and the synchronization signal LOAD for each line are input at the same time, the gate driver 2 starts selecting the first line 12-1 of the liquid crystal display panel 1 and the next synchronization. It lasts until the pulse of signal LOAD. Hereinafter, every time the pulse of the synchronization signal LOAD comes, the second
The gate electrode is selected in the order of the line 12-2, the third line 12-3, .... Also, data for one line (N)
Is input to and latched by the data driver 3 at the timing of the clock CLK via the data signal line DATA, and the data lines 13-1 to 13-N are synchronized with the synchronization signal LOAD.
Is output to.

On the other hand, the switching signal generator 4 is composed of a one-shot multivibrator 6 as shown in FIG. 3 (a), and is connected to the resistor R1 in synchronization with the 1-line synchronizing signal LOAD.
And a pulse signal having a width (corresponding to the period Ta) according to the time constant C1 · R1 determined by the product of the capacitor C1, that is, the switching signal 11 for dividing the selection period of each gate line into two periods Ta and Tb. To do.

The drive voltage controller 5 has the circuit configuration shown in FIG. 3 (b). That is, the switching signal 11 and the alternating signal ACM are input, and the HI signal is input in a period other than the period Ta.
GH level control signal 5A, control signal 5B having positive polarity of AC signal ACM being HIGH level during period Ta, and control signal 5C having negative polarity of AC signal ACM being HIGH level during period Ta Generate and NOT
Gates NOT1 and NOT2, and AND gate AN
A combinational logic composed of D1 and AND2, a variable resistor VR1 that sets the voltage + Vm output in the period Ta with a positive polarity, and a voltage − output in the period Ta with a negative polarity.
A variable resistor VR2 that sets Vm, an analog switch SW1-i that outputs the output signal 13-i of the data driving unit 3 as an output signal 14-i in a period other than the period Ta under the control of the control signal 5A, and a control signal. An analog switch SW2-i that outputs a voltage + Vm as an output signal 14-i in the period Ta with a positive polarity based on the control of 5B, and a control signal 5.
An analog switch SW3 that outputs a voltage -Vm as an output signal 14-i in a period Ta with a negative polarity under the control of C
-I and the configuration.

The analog switches SW1-i to SW3
One set of -i is required for each gate line (N lines), but the other components may be at least one in the entire device.

With such a configuration, the drive voltage controller 5
The waveforms of the control signals 5A, 5B, and 5C generated by the combinational logic of are as shown in FIGS.
Assuming that the voltage waveform of the data line 13-i output from the data driver 3 is the waveform shown in FIG. 1L, the voltage waveform of the data line 14-i corrected by the drive voltage controller 5 is As shown in (n) of FIG.
Voltage + Vm, and during the period Ta of negative polarity, voltage -Vm,
In the other periods, the voltage waveform of the data line 13-i is obtained.

Therefore, according to this embodiment, the voltage waveform of the data line 14-i is as shown in FIG. 8C, and the voltage waveform actually applied to the liquid crystal cell 72 is within a predetermined driving time width within a predetermined driving time width. The drive voltage is reached, the desired brightness can be obtained, and as a result, driving can be performed without degrading display quality.

Second Embodiment FIG. 4 shows a circuit configuration diagram of a drive voltage control section of a drive control circuit of a liquid crystal display device according to a second embodiment of the present invention. The outline of the configuration of the drive control circuit of this embodiment is the same as that of FIG. 1 (first embodiment), and the components other than the drive voltage controller 5 have the same configuration as that of the first embodiment.

The drive voltage controller 5 of this embodiment uses the operational amplifier 21-i to generate the voltage output during the period Ta by multiplying the voltage output during the period Tb by C (>1; a constant). The configuration is such that an operational amplifier 21-i that outputs the voltage of the data line 13-i by C times (ratio of resistors R2-i and R3-i) and outputs the switching signal 11 is NOT gate NO.
Based on the control of the signal inverted at T3, the output signal 13-i of the data driver 3 is output during the period other than the period Ta.
Based on the control of the analog switch SW4-i for outputting as i and the switching signal 11, the operational amplifier 21-i is operated during the period Ta.
Of the analog switch SW5-i for outputting the output voltage of the output signal 14-i as the output signal 14-i.

The analog switches SW4-i and SW
One set of 5-i, resistors R2-i and R3-i, and operational amplifier 21-i is required for each gate line (N lines). In addition, as a modification of the first and second embodiments,
By adding a gate capable of performing tristate control based on the control of the inverted signal of the switching signal 11 to each of the outputs 13-1 to 13-N of the data driver 3, the analog switch SW1-i of the first embodiment, Also, the analog switch SW4-i of the second embodiment can be eliminated.

Third Embodiment FIG. 5 shows a circuit configuration diagram of a drive voltage control section of a drive control circuit of a liquid crystal display device according to a third embodiment of the present invention. The outline of the configuration of the drive control circuit of this embodiment is the same as that of FIG. 1 (first embodiment), and the components other than the drive voltage controller 5 have the same configuration as that of the first embodiment.

The drive voltage control section 5 of the present embodiment uses the operational amplifier 31-i as in the second embodiment to change the voltage output during the period Ta to C (>1; of the voltage output during the period Tb).
It is generated by multiplying by a (constant), but its configuration is the analog switch SW6 which is turned on / off under the control of the switching signal 11 level-shifted by the level shift circuit 32.
-I and the period Ta, the voltage of the data line 13-i which is the output of the data driver 3 is multiplied by C (resistors R4-i and R5.
In the period Tb, the operational amplifier 31-i outputs the data line 13-i as it is.

The analog switch SW6-i and the resistor R
4-i and R5-i, and one operational amplifier 31-i are required for each gate line (N lines). Further, although the analog switch is used in the first, second and third embodiments, any other switch can be used as long as the voltage can be switched.

[0029]

As described above, according to the present invention,
By applying the required voltage to the liquid crystal cell within the predetermined drive time width, the desired brightness of the liquid crystal panel can be obtained, and as a result, the liquid crystal panel with a large screen configuration can be driven without degrading the display quality. A drive control circuit for a liquid crystal display device can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention or a configuration diagram of a drive control circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a time chart of signals of respective parts of the drive control circuit of the present invention.

FIG. 3A is a circuit configuration diagram of a switching signal generation unit of the drive control circuit of the present invention, and FIG. 3B is a circuit configuration diagram of a drive voltage control unit.

FIG. 4 is a circuit configuration diagram of a drive voltage control unit of a drive control circuit of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a drive voltage control unit of a drive control circuit of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a drive circuit of a conventional liquid crystal display device.

FIG. 7 is a configuration diagram of a liquid crystal display panel.

FIG. 8 is a diagram illustrating a charging voltage waveform of a liquid crystal cell,
FIG. 8A shows the case of the conventional low-speed drive circuit, and FIG.
Shows a case of a conventional high-speed drive circuit, and FIG. 8C shows a case of a high-speed drive control circuit of the present invention.

[Explanation of symbols]

1 ... Liquid crystal display panel 2 ... Gate driver 3 ... Data driver 4 ... Switching signal generator 5 ... Drive voltage control unit CLK ... Clock signal DATA ... Data signal line ACM ... AC signal LOAD ... Synchronous signal for each line FRAME ... Sync signal for each screen 11 ... Switching signal 12-1 to 12-M ... Gate line 13-1 to 13-N ... Data line 14-1 to 14-N ... Data line 6 ... One-shot multi-vibrator R1, R2-i, R3-i, R4-i, R5-i ... Resistance C1 ... Capacitor VR1, VR2 ... Variable resistance NOT1, NOT2, NOT3 ... NOT gate AND1, AND2 ... AND gate SW1-i to SW6-i ... Analog switch 5A, 5B, 5C ... Control signal 21-i, 31-i ... Operational amplifier 32 ... Level shift circuit 72 ... Liquid crystal cell

Claims (2)

[Claims] 1. An active matrix type liquid crystal display panel (1) and a gate drive section (2) for driving gate lines (12-1 to 12-M) of the liquid crystal display panel (1).
And the data line (13- of the liquid crystal display panel (1)
1 to 13-N) and a data driver (3) for driving the liquid crystal display device, wherein the gate driver (2) is the gate line (12-1).
12-M), the data line (13-1) is driven for a certain period of time for driving an arbitrary gate line (12-j).
A drive control circuit for a liquid crystal display device, comprising: a drive voltage control section (5) for setting a drive voltage (absolute value) of (~ 13-N) to a higher voltage. 2. An active matrix type liquid crystal display panel (1) and a gate drive section (2) for driving gate lines (12-1 to 12-M) of the liquid crystal display panel (1).
And the data line (13- of the liquid crystal display panel (1)
1 to 13-N) and a data driver (3) for driving the liquid crystal display device, wherein the gate driver (2) is the gate line (12-1).
A switching signal generation unit (4) for generating a switching signal (11) for dividing a period for driving an arbitrary gate line (12-j) in (12-M) into two periods, and the switching signal (11). Control the data line (13
-1 to 13-N), a drive voltage control unit (5) having a larger drive voltage (absolute value) in the first period, a drive control circuit for a liquid crystal display device.