JP2003195819A - Image display device, display signal supply device, and write potential supply method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a deficiency in writing to a pixel as to an active matrix type display device which supplies a potential to two or more pixels from one display signal line on a time-division basis. <P>SOLUTION: The write times of the potential to pixel electrodes A1 and B1 connected to a common display signal line Dm are so set that the time of writing to the pixel electrode A1 is made longer than that to the pixel electrode B1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly to a technique that contributes to high definition of a liquid crystal display device.

[0002]

2. Description of the Related Art As a liquid crystal display device, an active matrix type liquid crystal display device using a TFT (Thin Film Transistor) as a switching element is known. In this active matrix type liquid crystal display device, scanning signal lines and display signal lines are arranged in a matrix, and a TFT array substrate in which thin film transistors are arranged at intersections thereof and a predetermined gap from the substrate. A liquid crystal material is enclosed between the color filter substrate and the color filter substrate, and the voltage applied to the liquid crystal material is controlled by a thin film transistor to enable display by utilizing the electro-optical effect of the liquid crystal.

The following problems have been raised with the increase in the number of pixels accompanying the higher definition of the active matrix type liquid crystal display device. That is, as the number of pixels increases, the number of display signal lines and scanning signal lines becomes very large, the number of drive ICs also becomes huge, and the cost is increased. Further, the electrode pitch for connection between the drive IC and the TFT array substrate becomes narrow, which makes connection difficult and reduces the yield of connection work. In order to solve this problem at the same time, the potential of one display signal line is applied to two or more pixels adjacent to each other in the column direction in a time-division manner to reduce the number of required driving ICs and reduce the pitch of the connection terminals. Many proposals to increase the size have been made so far. For example, JP-A-6-138851, JP-A-6-148680, JP-A-11-2837, and JP-A-5-265.
045, JP-A-5-188395, and JP-A-5-303114.

[0004]

As described above, various circuit structures have been proposed to cope with higher definition of the active matrix type liquid crystal display device. An object of the present invention is to provide a writing potential supply method suitable for an image display device having such a circuit structure. Also,
An object of the present invention is to provide a display signal supply device and an image display device for executing the method of supplying the write potential.

[0005]

In an image display device, a potential is applied in time division from one display signal line to two or more pixels adjacent to each other in the column direction (hereinafter, such a structure is referred to as a multi-pixel structure). , The following problems are assumed. That is, in the case of the multiple pixel structure, the time during which the potential is written in one pixel becomes short. For example, when a potential is applied to two pixels from one display signal line, if one predetermined horizontal scanning period is divided into ½, the writing time will be insufficient due to the difference in writing logic and characteristics. To
It is assumed that the write potential for one pixel does not reach the target write potential. Therefore, in the present invention,
Instead of equalizing the writing time for a plurality of pixel electrodes, a length and a short length are provided for each pixel.

The image display device of the present invention has a plurality of display signal lines for transmitting display signals, a first pixel electrode and a second pixel electrode to which display signals are written from the common display signal line, and a first pixel electrode. A scan signal line for transmitting a scan signal to the pixel electrode and the second pixel electrode;
The first display signal and the second display signal are generated based on the first signal corresponding to the first pixel electrode and the second signal corresponding to the second pixel electrode, and the predetermined 1
Signal processing means for supplying the first display signal and the second display signal in a time division manner within the horizontal scanning period HT. In this image display device, the signal processing means is characterized in that the time TA for writing the first display signal and the time TB for writing the second display signal are set to TA> TB.

In the image display device of the present invention, since TA> TB can be set, it is possible to solve the shortage of the writing time for the first pixel electrode. As will be apparent from the embodiments described later, in the image display device having the multiple pixel structure, the second pixel electrode is also supplied with the first display signal during the time TA during which the first display signal is written to the first pixel electrode. The display signal of 1 is written. First to this second pixel electrode
Writing of the display signal of means that preliminary potential writing (pre-charge) is performed on the second pixel electrode. Therefore, even if the writing time TB of the second display signal to the second pixel electrode is short, insufficient writing is unlikely to occur.

By the way, recent image display apparatuses are required to support a plurality of display modes for the purpose of power saving and the like. That is, power consumption is reduced by lowering the drive frequency. This power saving mode involves changing the horizontal scanning period. In order to maintain the normal driving of the liquid crystal display device, the writing time to each pixel electrode should be changed according to the change of the horizontal scanning period. Therefore, in the image display device of the present invention, the signal processing means is
When one horizontal scanning period fluctuates, it is desirable to reset TA and / or TB on the assumption that TA> TB. Since it is TA and / or TB, it is not limited to the case where both TA and TB are changed, and only TA may be changed or only TB may be changed. In the image display device of the present invention, TA and TB are set within one horizontal scanning period HT, but one horizontal scanning period may or may not be spent. That is, the signal processing means of the present invention can set the HT, the TA, and the TB so that HT = TA + TB or HT> TA + TB. In the image display device of the present invention, the predetermined horizontal scanning period HT is HT =
HD + HB (however, HD is a period in which the first signal or the second signal is input, and HB is a period in which the first signal and the second signal are not input). In this case, the signal processing means
It is desirable to set it to HD / 2 or less. Or T
It is desirable to set A-TB to HB or less.

As is well known, in the liquid crystal display device, the inversion driving method is adopted to prevent deterioration of the liquid crystal material. When the image display device of the present invention is applied to a liquid crystal display device, an inversion driving method is adopted. However,
In the case of the multiple pixel structure, it is assumed that the pixel electrodes connected to the common display signal line are usually driven with the same polarity within one horizontal scanning period. Therefore, the first pixel electrode and the second pixel electrode in the present invention are 1
During the horizontal scanning period, they are driven with the same polarity.

As an image display device of the present invention, a first switching element provided between a common display signal line and a first pixel electrode and having a gate electrode for controlling writing of a display signal, A second switching element arranged between the gate electrode of the first switching element and the predetermined scanning signal line; and a second switching element connected to the predetermined scanning signal line and
It is desirable to have a structure including a third switching element that controls the supply of the display signal to the pixel electrode.

In the multiple pixel structure, two pixel electrodes are connected to a common display signal line, and the other pixel electrode is connected within a period in which a potential is written in one of the two pixel electrodes. It is stated that the potential is also written. That is, in the multiple pixel structure, the pixel electrode to which the corresponding potential is written first is not pre-charged. On the other hand, the pixel electrode to which the corresponding potential is later written may be precharged. That is, it is understood that the time for writing the potential to the pixel electrode to which the potential is written first is longer than the time to write the potential on the pixel electrode to which the potential is written later. Therefore, the present invention provides an image display element in which a plurality of pixel electrodes are arranged in a matrix and a display signal line for transmitting a potential and a scanning signal line for transmitting a scanning signal are provided to each pixel electrode; And a signal processing means for generating and supplying the signal to the display signal line,
The image display device is connected to a display signal line having a common n (where n is an integer of 2 or more) pixel electrodes existing in the same row, and the signal processing means sets a maximum during a predetermined horizontal scanning period. Provided is an image display device, wherein a potential writing time for a predetermined pixel electrode to which a potential is first written is set longer than a writing time to another pixel electrode to which a potential is written thereafter.

In the image display device of the present invention, however,
It is important that the potential writing time for the predetermined pixel electrode to which the potential is written first and the writing time for the other pixel electrodes after which the potential is written are set so as to reach the reaching potential for each pixel electrode. Needless to say.

In the image display device of the present invention, in the image display element, two pixel electrodes are connected to a common display signal line, and a potential is written in one of the two pixel electrodes. It is possible to adopt a multiple pixel structure in which the potential is written in the other pixel electrode within a certain period. In this case, it is desirable that the signal processing unit sets the potential writing time for one pixel electrode longer than the potential writing time for the other pixel electrode. This is because the other pixel electrode is pre-charged and therefore the potential writing time may be shortened.

In the image display device of the present invention, in the image display element, three pixel electrodes are connected to a common display signal line, and a potential is written in a predetermined pixel electrode among the three pixel electrodes. It is also possible to adopt a multiple pixel structure in which the potential is written in other pixel electrodes within the period in which the pixel is charged. And similarly, the signal processing means
The potential writing time for a predetermined pixel electrode can be set longer than the potential writing time for another pixel electrode.

The image display element in the image display device of the present invention includes an n-th (n is a positive integer) scanning signal line and an n-th scanning signal line.
A first pixel electrode and a second pixel electrode which are arranged between the + 1st scanning signal line and are supplied with a display signal from a predetermined signal line, and an (n + 1) th scanning signal line and n +
When the mth (m is an integer excluding 0 and 1) scanning signal lines are both selected, a first switching mechanism that allows passage of a scanning signal and an n + 1th scanning signal line are selected It is preferable that the second pixel electrode further includes a second switching mechanism that allows passage of a scanning signal.

As described above, in the present invention, it is necessary to change the writing time when the display mode is changed. Then, the change of the writing time due to the change of the display mode is independently established as the display signal supply device. This display signal supply device is
A display signal supply device for supplying a writing potential to a matrix-type image display element, the signal supplying means supplying time-divisionally the writing potential for a plurality of pixels within one horizontal scanning period with respect to a predetermined display signal line And a writing time changing means for changing the supply time of the writing potential to at least one of the plurality of pixels.

The writing time changing means changes the supply time of the writing potential based on the change of one horizontal scanning period. Further, the change of the supply time of the write potential can be made on the assumption that the supply time of the write potential for a predetermined pixel of the plurality of pixels is set longer than the supply time of the write potential for the other pixels. Needless to say. Further, at this time, the signal supply unit supplies the write potential to the predetermined pixel,
It is prioritized over the supply of the write potential to other pixels.

The present invention also provides the following writing potential supply method which can be applied to the above image display device and display signal supply device. That is, the write potential supply method of the present invention is a write potential supply method for supplying a write potential to an active matrix type image display element, and a plurality of write potential supply methods within one horizontal scanning period based on video data supplied from the outside. Is generated, and the supply time of the write potential to a predetermined pixel of the plurality of pixels is set longer than the supply time of the write potential to the other pixels. In addition,
The write potential is supplied to a plurality of pixels from a common display signal line in a time division manner.

Also, the write potential supply method of the present invention receives video data for a plurality of pixels from the outside, generates write potentials for a plurality of pixels based on the video data, and time-divisionally within one horizontal scanning period. A method of supplying a write potential to an active matrix type image display element, which supplies a write potential to a plurality of pixels, wherein a write potential supply time for each of a plurality of pixels is dynamically set based on one horizontal scanning period. It is characterized by setting. As a more specific mode, it is possible to change the supply time of the write potential for each of a plurality of pixels along with the change of one horizontal scanning period.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) An image display device of the present invention will be described below based on an embodiment relating to a liquid crystal display device. FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device 1 according to the present embodiment, and FIG. 2 is a block diagram showing a configuration of an X driver 3. The liquid crystal display device 1 according to the present embodiment is characterized in that two adjacent pixels with one common display signal line in between share the same display signal line, thereby reducing the number of display signal lines by half. Have Further, the liquid crystal display device 1 according to the present embodiment
Is also characterized in that it is possible to make the supply (write) time of the display signal to the two pixels sharing one display signal line unequal. Of course, the liquid crystal display device 1 needs to include elements such as a TFT array substrate that constitutes the display element 2, a color filter substrate facing the TFT array substrate, and a backlight unit, but this is not a characteristic part of the present invention. Therefore, the description is omitted.

As shown in FIG. 1, the liquid crystal display device 1 is a drive circuit for supplying a display signal to the pixel electrode arranged in the display element 2 via the display signal line 30, that is, a driving circuit for writing a potential X. T via the driver 3 and the scanning signal line 40
A Y driver 4 which is a drive circuit for supplying a scanning signal for controlling ON / OFF of an FT (thin film transistor) is provided. In the display element 2, pixels are arranged in a matrix in the number of M × N (M and N are arbitrary positive integers).

The X driver 3 and the Y driver 4 are connected to the timing controller 5. The timing controller 5 receives digital video data (hereinafter referred to as video data), which are display signals, a synchronization signal (Sync), and a clock signal (CLK) from the system 6 side such as a personal computer. , X driver 3 and Y driver 4 are controlled. X driver 3, Y driver 4 and timing
Each of the controllers 5 or a combination thereof constitutes the signal processing means of the present invention. The timing controller 5 includes a parameter register 51 and a timing generator 52. Parameter register 51
Stores parameters for determining the strobe (STB) point. The strobe point means the time at which the write data read by the X driver 3 is converted into an analog voltage and output to the display signal line 30 is started. The timing generator 52 generates a signal necessary for driving the X driver 3 and the Y driver 4 based on the parameter stored in the parameter register 51, and outputs it to the X driver 3 and the Y driver 4. . The generated and output signals are STB
Besides, there are DIO which is a shift start signal for the X driver 3 and OE for the Y driver 4. The details of the timing controller 5 will be described later. The timing controller 5 may also include a block that handles video data transferred from the system 6 or a block that generates another control signal, but the description thereof is omitted here.

FIG. 2 is a block diagram showing the configuration of the driver element 31 constituting the X driver 3. It should be noted that, as is well known, the X driver 3 includes a plurality of driver elements 31.
Can be configured by. The driver element 31 is
As shown in FIG. 2, it includes a shift register 311, a data register 312, a latch 313, a level shifter 314, a DA converter 315, and an amplifier 316. However, it is not limited to this form. The shift register 311 produces a control pulse for sequentially packing the video data in the data register 312 into the data register 312. This control pulse is based on the shift start pulse DIO and CLK. The video data transferred from the timing controller 5 is temporarily stored in the data register 312. The video data stored in the data register 312 is transferred to the latch 313 according to the STB signal sent from the timing controller 5. The video data transferred to the latch 313 is supplied to the DA converter 315 after the voltage of the video data is converted into the DA converter input voltage by the level shifter 314. The video data converted from the digital signal to the analog signal by the DA converter 315 is amplified to a predetermined value by the amplifier 316 and then output to the display signal line 30 as a display signal.

Next, the circuit structure of the display element 2 will be described with reference to FIG. Note that FIG. 3 shows only a part of the display element 2, and the actual display element 2 is not shown in FIG.
A circuit having the structure shown in is formed continuously. In FIG. 3, for the pixel electrodes A1 and B1 that are adjacent to each other with the display signal line Dm interposed therebetween, the first TFT M1 and the second TFT M1
The M2 and the third TFT M3 and the three TFTs are arranged as follows. First, the first TFT M1 is
The source electrode is connected to the display signal line Dm, and the drain electrode is connected to the pixel electrode A1. Also, the first TF
The gate electrode of T M1 is connected to the source electrode of the second TFT M2. Here, the TFT is a switching element having three terminals, and in the liquid crystal display device 1, the display signal line 3
There is an example in which the side connected to 0 is called the source electrode, and the side connected to the pixel electrode is called the drain electrode, but there is also the opposite example. That is, which of the two electrodes other than the gate electrode is called the source electrode and the drain electrode is not uniquely determined. Therefore, hereinafter, the two electrodes except the gate electrode will be referred to as source / drain electrodes.

Next, in the second TFT M2, its source / drain electrode is the gate electrode of the first TFT M1,
The source / drain electrodes are connected to the scanning signal line Gn + 2. Therefore, the gate electrode of the first TFT M1 is connected to the scanning signal line Gn via the second TFT M2.
It will be connected to +2. In addition, the second TFT M
The second gate electrode is connected to the scanning signal line Gn + 1. Therefore, two adjacent scanning signal lines Gn + 1 and Gn +
The first TFT M1 is turned on and the potential of the display signal line Dm is supplied to the pixel electrode A1 only while 2 is simultaneously at the selection potential (hereinafter, simply referred to as selection). This means that the second TFT M2 turns on when the first TFT M1 turns on.
It suggests controlling OFF. Third TFT
The source / drain electrodes of M3 are the display signal lines Dm.
And its source / drain electrodes are connected to the pixel electrode B1. The gate electrode of the third TFT M3 is connected to the scanning signal line Gn + 1. Therefore,
When the scanning signal line Gn + 1 is selected, the third TFT M3 is turned on and the potential of the display signal line Dm is supplied to the pixel electrode B1.

Next, the pixel electrode C1 located below the pixel electrode A1 has the same structure as the pixel electrode A1.
Further, the pixel electrode D1 located below the pixel electrode B1 is
It has the same configuration as the pixel electrode B1.

In the above, the first TFT M1 to the third TF
The circuit configuration in the display element 2 viewed from T M3 has been described, but the circuit configuration in the display element 2 viewed from the pixel electrode A1 and the pixel electrode B1 will be described. A display signal is supplied to the pixel electrode A1 and the pixel electrode B1 from a common single display signal line Dm. That is, the display signal line Dm is connected to the pixel electrode A.
It can be said that the display signal line Dm is common to 1 and the pixel electrode B1. Therefore, while the pixels are arranged in an M × N matrix, the display signal line Dm
Is M / 2. The pixel electrode A1 has a first TFT M
1 and the second TFT M2 are connected, the first TFT M1 is connected to the display signal line Dm, and
It is connected to the second TFT M2. The gate electrode of the second TFT M2 is the scanning signal line Gn + 1 in the subsequent stage of the pixel electrode A1.
And the drain electrode of the second TFT M2 is connected to the scanning signal line Gn + 2 in the subsequent stage of the scanning signal line Gn + 1. Here, in order to supply the potential of the display signal line Dm to the pixel electrode A1, the first TFT M1 needs to be turned on. The gate electrode of the first TFT M1 is connected to the source / drain electrode of the second TFT M2, the gate electrode of the second TFT M2 is connected to its own scanning signal line Gn + 1, and the source / drain electrode of the latter stage is connected. Since it is connected to the scanning signal line Gn + 2, the first T
In order to turn on FT M1, the second TFT M2 is turned off.
N needs to be done. In order for the second TFT M2 to be turned on, the scanning signal line Gn + 1 needs to be selected, and when the scanning signal line Gn + 2 is selected during that time, the first TFT M1 is also turned on. Therefore, the first T
The FT M1 and the second TFT M2 are connected to the scanning signal line Gn.
A switching mechanism that allows passage of a scanning signal when both +1 and the scanning signal line Gn + 2 are selected is configured. Thus, the pixel electrode A1 has the scanning signal line Gn + 1.
Driven based on the scanning signal from the display signal line and the scanning signal from the scanning signal line Gn + 2, and receives the potential from the display signal line Dm.

A third TFT M3 is connected to the pixel electrode B1, and its gate electrode is connected to the scanning signal line Gn + 1. Therefore, the pixel electrode B1 is supplied with a potential from the display signal line Dm when its own scanning signal line Gn + 1 is selected. Although the pixel electrode A1 and the pixel electrode B1 have been described above, the pixel electrode A2 and the pixel electrode B2, the pixel electrode C1 and the pixel electrode D1, and the pixel electrode C2.
The pixel electrode D2 and other pixels have the same configuration.

Next, the flow of video data and control signals from the system 6 to the display element 2 will be described with reference to FIG. FIG. 4 is a diagram showing the flow of video data and control signals from the system 6 to the display element 2 in comparison. FIG. 4A shows data and control signals between the system 6 and the timing controller 5 of the liquid crystal display device 1. Further, FIG. 4B shows data and control signals between the timing controller 5 and the X driver 3. Further, FIG. 4C shows a signal output from the X driver 3.

In FIG. 4A, one horizontal scanning period (H Total in the drawing) is video data (1 horizontal display data) to be displayed in one horizontal scanning period (Dat in the drawing).
Time during which a) is being transferred from the system 6 to the timing controller 5 (H Display in the figure)
And one horizontal display data is not transferred (in the figure, H B
rank) and. In other words, H Displ
Video data is transferred from the system 6 to the timing controller 5 during ay. Further, a horizontal synchronizing signal (HSync in the figure) is transferred from the system 6 to the timing controller 5.

In FIG. 4B, the shift register 3
When DIO is input to 11, the video data is transferred from the timing controller 5 to the data register 312. The video data transfer is synchronized with the clock signal input to the shift register 311. Figure 4
The column "Driver Data" in (b) shows how the video data 1A is stored in the data register 312 by the first DIO. Further, it is shown that the video data 1B is stored in the data register 312 by the next DIO. The video data 1A includes pixel electrodes A1 and A2.
Video data to be written to ...
Data 1B represents video data to be written in the pixel electrodes B1, B2 ... Similarly, video
The data 1C indicates video data to be written in the pixel electrodes C1, C2 ... And the video data 1D indicates video data to be written in the pixel electrodes D1, D2. By supplying STB to the latch 313, the video data 1A stored in the data register 312 is supplied to the DA converter 315 via the level shifter 314. “Latched D” in FIG.
The column "ata for D / A" shows this state.
Video data 1A is transferred to the next S by the first STB.
Video data 1B is DA converter 31 by TB
It is output to 5.

FIG. 4C shows a signal (voltage waveform) supplied from the X driver 3 to the display signal line 30. FIG. 4C shows two display signal lines 30 (in FIG. 3,
Only signals for Dm, Dm + 1) are shown. Figure 4
In (c), the dotted line shows the voltage waveform based on the video data 1A, and the solid line shows the voltage waveform based on the video data 1B.

Next, referring to the circuit diagrams of FIGS.
The operation of the pixel electrodes A1 to D1 by selecting and deselecting the scanning signal lines Gn + 1 to Gn + 3 will be described. As shown in FIG. 5, the scanning signal line Gn + 1 and the scanning signal line Gn +
The first TFT M1 to the third TFT M3 are turned on during the period from when both of the two are selected until the scanning signal line Gn + 2 becomes the non-selection potential (hereinafter, simply referred to as non-selection). As shown in FIG. 5, the potential Va1 to be applied to the pixel electrode A1 from the display signal line Dm is written in the pixel electrode A1, the pixel electrode B1, and the pixel electrode D1. Here, the potential Va1 of the pixel electrode A1 is determined. Note that, in FIG. 5, the thick line indicates that the scanning signal line Gn + 1 and the scanning signal line Gn + 2 are selected. Further, the pixel electrodes to which the potential is written are hatched.

After the scanning signal line Gn + 2 is deselected, the potential supplied from the display signal line Dm is the pixel electrode B1.
It changes to the potential Vb1 to be applied to. Scan signal line Gn + 2
The scanning signal line Gn + continues for a period after being deselected.
By keeping 1 selected, the potential of the pixel electrode B1 at which the potential Vb1 is written to the pixel electrode B1 is determined as shown in FIG. Thus, the potential of the display signal line Dm is supplied to the pixel electrode A1 and the pixel electrode B1 in a time division manner. After the scanning signal line Gn + 1 is deselected, the display signal line D
The potential of m changes to the potential Vc1 to be given to the pixel electrode C1.

If the scanning signal line Gn + 2 is selected again and the scanning signal line Gn + 3 is selected during the period after the scanning signal line Gn + 1 is deselected, as shown in FIG. Electrode D1 and pixel electrode B2
The electric potential Vc1 is written in. Here, the potential Vc1 of the pixel electrode C1 is determined. After the scanning signal line Gn + 3 is deselected, the potential supplied from the display signal line Dm changes to the potential Vd1 to be given to the pixel electrode D1. Scan signal line Gn
The scanning signal line G continues to be used even after +3 is deselected.
By selecting n + 2 in advance, the potential Vd1 is written in the pixel electrode D1 as shown in FIG. 8, and the potential of the pixel electrode D1 is determined.

By the way, a potential is written in a time division manner from the common display signal line Dm to the two pixel electrodes A1 and B1 within one horizontal scanning period. Therefore, the time for writing the potentials in the two pixel electrodes A1 and B1 is shorter than that in the conventional liquid crystal display device in which one pixel electrode is connected to one display signal line Dm. Therefore, the writing of the potential to the pixel electrode A1 is insufficient, in other words,
The potential actually written may be lower than the potential to be originally written (reached potential). FIG. 9 is a diagram for explaining this. FIG. 9 is premised on writing the same potential (Va1 = Vb1) to the pixel electrodes A1 and B1. For example, when it is desired to display black. Figure 9
In, the upper graph shows the relationship between the writing potential for the pixel electrodes A1 and B1 and time. "Charge A", "Charge B" under this graph
Indicates the time during which the potential writing to the pixel electrode A1 and the potential writing to the pixel electrode B1 are performed, respectively. Further, “Gate n + 1” and “Gate n + 2” therebelow indicate selection and non-selection of the scanning signal lines Gn + 1 and Gn + 2. Further, the STB below it shows a strobe signal.

In FIG. 9, it is assumed that the potential writing time TA for the pixel electrode A1 and the potential writing time TB for the pixel electrode B1 are equal (TA = TB). This writing time is determined by STB. When the scanning signal lines Gn + 1 and Gn + 2 are selected, the potential is written not only to the pixel electrode A1 but also to the pixel electrode B1 as described above. Next, the scanning signal line Gn +
When 2 is not selected, the potential (Va1) to the pixel electrode A1
Is canceled, but the potential (V
Writing of b1) is continued. At this time, the pixel electrode B
Since the potential of No. 1 is written during the writing time to the pixel electrode A1, the writing potential can easily reach the reaching potential Vb1. But,
Since the writing time for the pixel electrode A1 is insufficient,
The writing potential of the pixel electrode A1 may not reach the reaching potential.

Therefore, in the present embodiment, the pixel electrode A1
Prolongs the writing time of the potential to. This state is shown in FIG. That is, in this embodiment, as shown in FIG.
As shown in, the potential writing time TA for the pixel electrode A1 is set longer than the potential writing time TB for the pixel electrode B1 (TA> TB). This TA is the pixel electrode A1
Is set so that there is no write shortage. On the other hand,
Although TB becomes shorter, the pixel electrode A1 is
Since the electric potential is written during the electric potential writing time TA, the insufficient writing of the electric potential in the pixel electrode B1 does not occur.

Potential writing time TA for the pixel electrode A1, potential writing time TB for the pixel electrode B1
Is determined by STB. Then, the parameter regarding the start of the STB is set in the parameter register 51 of the timing controller 5. FIG. 11 shows a specific example thereof. In FIG. 11, XSTB1stS
start and XSTB2ndStart determine the start time of the STB. The writing time TA of the potential with respect to the pixel electrode A1 is XSTB2ndStart-X.
It becomes STB1stStart. Further, the writing time of the potential to the pixel electrode B1 is H Total-TA. In the present embodiment, these STB-related parameters are set so that TA> TB.

In setting the parameters, the pixel electrode A
It should be taken into consideration that the writing of the electric potentials to the 1 and the pixel electrodes B1 are respectively sufficiently saturated. When the liquid crystal display device 1 adopts the normally white mode, the pixel electrode A1 has the longest potential writing time when displaying black. Therefore, the potential writing time TA for the pixel electrode A1 should be determined in consideration of this condition. The pixel electrode B1 is the pixel electrode A1.
When white is displayed, the potential writing time becomes the longest when black is displayed. Therefore, the pixel electrode B1
The potential writing time TB with respect to should be determined in consideration of this condition.

By the way, the pixel electrode A1 and the pixel electrode B
The writing of the potential with respect to 1 takes 1 horizontal scanning time (H T
It is performed in the total). H Total is the above H
It is the total time of Display and H Blank. Within this H Total, TA> TB will be satisfied. At this time, the pixel electrode A1 and the pixel electrode B
H Blank can also be spent writing the potential for 1. In addition, as shown in FIG. 12, the pixel electrode A1
And all H Total can be spent for writing the potential to the pixel electrode B1 (TA + TB = H
Total). However, the present invention is not limited to this, and when writing the potential to the pixel electrode A1 and the pixel electrode B1,
It is possible to stay within the predetermined time of tal (TA + T
B <H Total). Here, TB is H Displa
y 1/2 or less, or TA-TB to H Blank
The following is desirable.

As described above, in the liquid crystal display device 1 according to the first embodiment, the potential writing time TA for the pixel electrode A1 is set longer than the potential writing time TB for the pixel electrode B1. It is possible to solve the shortage of writing to. The liquid crystal display device 1 according to the first embodiment adopts a configuration in which a drive potential is written from one display signal line, for example, the display signal line Dm to two pixel electrodes A1 and B1 which are adjacent to each other with the display signal line Dm interposed therebetween. ing. Therefore, it is possible to reduce the number of display signal lines, that is, the number of data drivers, by half as compared with the conventional liquid crystal display device in which the pixels and the display signal lines correspond one to one. Moreover, the liquid crystal display device 1 according to the first embodiment
The first TFT M1 connected to the pixel electrode A1 and the second TFT M2 connected to the pixel electrode B1 are directly connected to the common display signal line Dm. Therefore, unlike the case where two TFTs are connected in series between the display signal line and the pixel electrode, it is not necessary to design the TFT to be large in order to secure a desired current. That is, according to the first embodiment, the first T
The FT M1 and the second TFT M2 can be downsized.

Liquid crystal display device 1 according to the first embodiment
Has a storage capacitor Cs installed between it and the scanning signal line in the preceding stage. That is, as shown in FIG. 4, the pixel electrodes A1 and B are
The storage capacitors Cs of 1, A2 and B2 are provided between them and the scanning signal line Gn, and the storage capacitors Cs of the pixel electrodes C1, D1, C2 and D2 are provided between them and the scanning signal line Gn + 1. The scanning signal line Gn is connected to the pixel electrodes A1, B1, A2.
And B2 are not involved, and the scanning signal line Gn + 1
Does not participate in driving the pixel electrodes C1, D1, C2 and D2. Here, during and immediately after the period in which the potentials are written to the pixel electrodes A1, B1, A2 and B2 from the display signal lines Dm and Dm + 1, the scanning signal line Gn
Does not change. Therefore, the pixel electrodes A1 and B
Since the fluctuation of the pixel potential at 1, A2 and B2 can be avoided, the pixel potential can be controlled with high accuracy. This is a great advantage in terms of image quality and can provide high quality images.

(Second Embodiment) The second embodiment according to the present invention will be described below. The first embodiment has been described on the assumption that the image display mode is one type (fixed). However, recently, a liquid crystal display device capable of supporting a plurality of display modes has been desired mainly for the purpose of power saving. The second embodiment is an example in which the present invention is applied to a liquid crystal display device having a plurality of display modes.
Since the basic configuration of the liquid crystal display device according to the second embodiment is the same as that of the liquid crystal cover device 1 according to the first embodiment, only the differences will be described below. FIG.
Shows examples of two display modes adopted in a liquid crystal display device of XGA resolution. Mode 1 (M
1) is the normal display mode, and mode 2 (M2) is
The display mode for power saving is shown. M2 is H Total P by cutting H Blank against M1.
Pixe by reducing the number of clocks (horizontal direction clock)
ls Clock Rate is lowered.

Problems in the case where the display mode is changed as described above will be described with reference to FIG. In FIG. 14, it is assumed that the liquid crystal display device 1 is initially driven by M1 (before changing the mode). At this time, the number of clocks in the horizontal direction is 1343. It is assumed that STB is set to be generated at the 500th clock and the 1343th clock, and the potential is written to the pixel electrode A1 during this period (TA). Here, it is assumed that the display mode is changed to M2. This is the position horizontal scanning period (H Total
l) has been changed. If the STB setting is left unchanged, as shown in mode change (a) of FIG.
The second STB cannot be output. Therefore, the liquid crystal display device 1 cannot be normally driven. Therefore,
In the second embodiment, the display mode, that is, H
When the Total is changed, the timing of STB generation is set again. This is shown in the mode change (b) of FIG. In this example, the STB is generated at the 400th clock and the 1151st clock in accordance with the change of the display mode to M2.

In order to change the timing of STB generation as described above, H Total is monitored. In order to realize this, in the second embodiment, as shown in FIG.
And a translator 54. The timing controller 5 shown in FIG. 15 measures H Total based on the input horizontal synchronization signal (H Sync),
Optimal parameters are determined by the translator 54. The setting of the parameter register 51 is changed according to the determined parameter. Timing generator 52
STB, DIO, OE based on its parameters
Generate signals such as. The signal is supplied to the X driver 3 and the Y driver 4.

Here, ST in the translator 54
Various forms are conceivable for determining the generation timing of B. For example, when H Total is greater than or equal to a predetermined value,
Driven by X Data Strobe Point A, and when less than a predetermined value, X Data Strobe Point A
It can be driven at t B. Also, the threshold value is increased to n, and n + 1 X Data Strobe Poi
It is also possible to prepare a set of nt and parameters. Also, instead of having all the parameters
It can also be calculated based on the measured H Total. For example, when HTotal exceeds a certain value, Ba
It is driven by sic X Data Strobe Point + α, and when it is less than a certain value, Basic X Data
It is conceivable to drive by Strobe Point + β. Alternatively, it can be calculated from the variation value (δ) of H Total. For example, δ from the reference H Total
Basic X Data Strob as a function f of
Driving at e Point + f (δ) is considered.

The parameters transferred from the translator 54 to the parameter register 51 are, as shown in FIG. 11, X STB 1st Start and X STB 1s.
t End, X STB 2nd Start and X S
TB 2nd End must be considered. Then, as described above, XSTB 1st Start and X STB 2nd Start determine the start timing of STB. The writing time TA of the potential with respect to the pixel electrode A1 is X STB 2nd Start−.
X STB 1st Start. Also, the pixel electrode B
The writing time of the potential with respect to 1 is H Total-TA
Becomes Although not shown in FIG. 11, X STB 1st
Start, X STB 1st End, X STB 2
Along with the change of the nd Start and the X STB 2nd End, other parameters, for example, the parameters regarding the Y driver 4 are also changed appropriately. However, since it does not affect the present invention, description thereof is omitted here.

As described above, according to the second embodiment, even if the display mode is changed, it is possible to write an appropriate potential to the pixel electrodes A1 and B1.

(Third Embodiment) The third embodiment of the present invention will be described below. In the first embodiment, an example in which two pixel electrodes are connected to a common display signal line has been shown, but the present invention is a case where three or more pixel electrodes are connected to a common display signal line. It is also effective.
Hereinafter, a liquid crystal display device in which three pixels are connected to one common display signal line will be described. The basic configuration is the same as that of the liquid crystal display device 1 according to the first embodiment except that the three pixels are connected to one common display signal line. Therefore, only the differences will be described below. .

FIG. 16 shows the circuit configuration of the display element 2 of the liquid crystal display device 1 according to the third embodiment. That is, as shown in FIG. 16, in the display element 2 of the liquid crystal display device 1 of the third embodiment, the display signal line Dm is connected to the pixel electrode A21 (pixel electrode D21, ...), the pixel electrode B21.
The three pixels of (pixel electrode E21, ...) And pixel electrode C21 (pixel electrode F21, ...) Are shared. And
The data potential of the display signal line Dm is written in the pixel electrode A21 when both the scanning signal line Gn + 1 and the scanning signal line Gn + 3 are selected. In addition, the pixel electrode B2
1 includes a scanning signal line Gn + 1 and a scanning signal line Gn + 2.
When is selected, the data potential of the display signal line Dm is written. The pixel electrode C21 is connected to the scanning signal line G.
When n + 1 is selected, the data potential of the display signal line Dm is written.

In order to perform the above operation, in the third embodiment, the first TFT as a switching element is used.
The arrangement of the M21 to fifth TFTs M25 is set as described below. That is, as shown in FIG.
One source / drain electrode of the first TFT M21 is connected to the pixel electrode A21, and the other source / drain electrode thereof is connected to the display signal line Dm. Also, the first TFT
The gate electrode of M21 is the source of the second TFT M22 /
It is connected to the drain electrode. Second TFT M22
Has one of the source / drain electrodes connected to the scanning signal line Gn.
+3, and the other source / drain electrode is connected to the gate electrode of the first TFT M21. Therefore, the gate electrode of the first TFT M21 is
It is connected to the scanning signal line Gn + 3 via T M22. The gate electrode of the second TFT M22 is connected to the scanning signal line Gn + 1. Therefore, the first TFT M21 is turned on and the potential of the display signal line Dm is written to the pixel electrode A21 only while the two scanning signal lines Gn + 1 and Gn + 3 are simultaneously selected. This means that the second TFT M22 is
It is a switching element that controls ON / OFF of the. The third TFT M23 has one source / drain electrode connected to the display signal line Dm and the other source / drain electrode connected to the pixel electrode C21. The gate electrode of the third TFT M23 is the scanning signal line G
It is connected to n + 1. The fourth TFT M24 has one source / drain electrode connected to the display signal line Dm and the other source / drain electrode connected to the pixel electrode B21. In addition, the gate electrode of the fourth TFT M24 is the fifth
Connected to the source / drain electrodes of the TFT M25. The fifth TFT M25 has one source / drain electrode connected to the scanning signal line Gn + 2 and the other source / drain electrode connected to the gate electrode of the fourth TFT M24. Therefore, the fourth TFT M2
The gate electrode of No. 4 is connected to the scanning signal line Gn + 2 via the fifth TFT M25. Also, the fifth T
The gate electrode of the FT M25 is connected to the scanning signal line Gn + 1. Therefore, the two scanning signal lines Gn + 1 and Gn
Only during the period when +2 are simultaneously selected, the fourth TF
TM24 is turned on and the potential of the display signal line Dm is supplied to the pixel electrode B21. This means that the fifth TFT M
It is shown that 25 is a switching element which controls ON / OFF of the fourth TFT M24.

The circuit configuration of the array substrate viewed from the first TFT M21 to the fifth TFT M25 has been described above, but the circuit configuration of the display element 2 viewed from the pixel electrodes A21 to C21 will be described. Display signals are written to the pixel electrodes A21 to C21 from a single display signal line Dm. That is, the display signal line Dm is connected to the pixel electrodes A21 to A21.
The display signal line Dm is common to the pixel electrode C21. A first TFT M21 and a second TFT M22 are connected to the pixel electrode A21, and the first TFT M21 and the second TFT M22 are connected to each other.
M21 is connected to the display signal line Dm and also to the second TFT M22. The gate electrode of the second TFT M22 is connected to its own scanning signal line Gn + 1, and the source / drain electrode of the second TFT M22 is connected to the scanning signal line Gn + 3 of the subsequent stage. Here, in order to write the potential of the display signal line Dm to the pixel electrode A21, the first TFT M21 needs to be turned on. The gate electrode of the first TFT M21 is the second TF.
The scanning signal line Gn connected to the source / drain electrode of the TFT M22 and the gate electrode of the second TFT M22 is located at a stage subsequent to the pixel electrode A21 and the pixel electrode B21.
+1 and the source / drain electrodes are scanning signal lines Gn +
Since it is connected to the scanning signal line Gn + 3 in a stage subsequent to 1, the second TFT M22 needs to be turned on in order to turn on the first TFT M21. Second TFT
In order for M22 to be turned on, the scanning signal line Gn + 1 and the scanning signal line Gn + 3 at the subsequent stage need to be selected.
In this way, the pixel electrode A21 is driven based on the scanning signal from the scanning signal line Gn + 1 and the scanning signal from the scanning signal line Gn + 3, and receives the potential from the display signal line Dm.

The pixel electrode B21 has a fourth TFT M24.
And the fifth TFT M25 are connected, and the fourth TFT M24 is connected to the display signal line Dm and the fifth TFT M25. 5th TFT
The gate electrode of M25 is connected to the scanning signal line Gn + 1, and the source / drain electrode of the fifth TFT M25 is connected to the scanning signal line Gn + 2. Here, in order to write the potential of the display signal line Dm to the pixel electrode B21, the fourth TFT M24 needs to be turned on. The gate electrode of the fourth TFT M24 is the fifth TF.
The gate electrode of the fifth TFT M25 connected to the source / drain electrode of T M25 is the scanning signal line Gn + 1.
Since the source / drain electrodes are connected to the scanning signal line Gn + 2, the fifth TFT M25 needs to be turned on in order to turn on the fourth TFT M24. In order to turn on the fifth TFT M25, the scanning signal line Gn + 1 and the scanning signal line Gn + 2 need to be selected. Thus, the potential from the display signal line Dm is supplied to the pixel electrode B21 only when the scanning signal line Gn + 1 located at the subsequent stage and the scanning signal line Gn + 2 at the subsequent stage are selected. In addition, the pixel electrode C21
Is connected to the third TFT M23, and its gate electrode is connected to the scanning signal line Gn + 1. Therefore, when the scanning signal line Gn + 1 is selected, the pixel electrode C21 is supplied with the potential from the display signal line Dm. Although the pixel electrodes A21 to C21 have been described above, the same configuration is adopted for the pixel electrodes D21 to F21 and the pixels below it.

In the display element 2 shown in FIG. 16, the scanning signal line Gn + is supplied within one horizontal scanning period (H Total).
It is assumed that 1, Gn + 2 and Gn + 3 are selected by the following procedure. First, Gn + 1, Gn + 2 and Gn + 3 are all selected. Then Gn + 1 and G
Select n + 2 and deselect Gn + 3. Then G
Select n + 1 and deselect Gn + 2 and Gn + 3. The operation of the display element 2 when the above selection procedure is executed will be described with reference to FIGS. In addition,
17 to 19 show only the operation of the pixel electrodes A21 to C21.

As shown in FIG. 17, the scanning signal lines Gn + 1,
In the period from the selection of all Gn + 2 and Gn + 3 to the non-selection of the scanning signal line Gn + 3, the first TF
TM21 to fifth TFT M25 are turned on. FIG. 17
As shown in, the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21 are connected to the pixel electrode A21 from the display signal line Dm.
The potential Va1 to be applied to is written. Here, the potential Va1 of the pixel electrode A21 is determined.

After the scanning signal line Gn + 3 is deselected, the potential supplied from the display signal line Dm is the pixel electrode B2.
It changes to the potential Vb1 to be given to 1. Scan signal line Gn +
The scanning signal line Gn continues in the period after 3 is not selected.
By selecting +1 and Gn + 2, the potential Vb1 is supplied to the pixel electrode B21 and the pixel electrode C21 as shown in FIG. Then, when the scanning signal line Gn + 2 as well as the scanning signal line Gn + 3 is deselected, the potential Vb1 of the pixel electrode B21 is determined.

In addition to the scanning signal line Gn + 3, the scanning signal line G
After n + 2 is also deselected, the potential supplied from the display signal line Dm changes to the potential Vc1 to be given to the pixel electrode C21, and the potential V2 is applied to the pixel electrode C21 as shown in FIG.
c1 is written.

As described above, in the third embodiment, the potentials are applied to the three pixel electrodes A21 to C21 in a time division manner within one horizontal scanning period (H Total).
Therefore, as described in the first embodiment, insufficient writing of the potential may occur. FIG. 20 is a diagram for explaining this, which is shown in FIG. 9 of the first embodiment.
It corresponds to. In FIG. 20, the pixel electrode A2
The potential writing time TA for 1 is equal to the potential writing time TB for the pixel electrode B21 and the potential writing time TC for the pixel electrode C21 (TA = TB =
TC). This writing time is determined by STB. Then, the time for writing the potential to the pixel electrode A21 may be insufficient. On the other hand, the potential (Va1) is written in the pixel electrode B21 even during the writing time of the potential in the pixel electrode A21. Further, the potential (Va1, Vb1) is written to the pixel electrode C21 also during the writing time of the potential to the pixel electrode A21 and the writing time of the potential to the pixel electrode B21.
Therefore, the writing potential of the pixel electrodes B21 and C21 can easily reach the reaching potential. The reaching potentials of the pixel electrodes A21 to C21 are equal (Va1 = Vb1 = Vc1).

Therefore, in the third embodiment, as shown in FIG. 21, the potential writing time TA for the pixel electrode A21 is set longer than the potential writing time for the pixel electrodes B21 and C21 (TA> TB, TC). This TA
Is set so that insufficient writing does not occur in the pixel electrode A21. On the other hand, although TB and TC become shorter,
Since the potential is written in advance on the pixel electrodes B21 and C21, insufficient writing of the potential on the pixel electrodes B1 and C21 does not occur. Note that the adjustment of the write time is executed by appropriately setting the parameters regarding the STB set in the parameter register 51, as in the first embodiment. In addition, as described in the first embodiment, it is necessary to take into consideration that the writing of the potential to the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21 is sufficiently saturated in the parameter setting.

In the above, the mode in which both of the pixel electrodes B21 and C21 are previously written with the potential (pre-charge) has been described. However, the third shown in FIG.
In the display element 2 of the embodiment, the scanning signal lines Gn,
Depending on the procedure of selecting Gn + 1 and Gn + 2, there is a case where the pixel electrode B21 is not precharged. Hereinafter, this example will be described.

In the display element 2 having the structure shown in FIG.
It is assumed that the scanning signal lines Gn + 1, Gn + 2 and Gn + 3 are selected by the following procedure. First, Gn +
1 and Gn + 3 are selected, but Gn + 2 is unselected. Then select Gn + 1 and Gn + 2 and
+3 is not selected. Then select Gn + 1 and Gn
+2 and Gn + 3 are unselected. 22 to 2 show the operation of the display element 2 when the above selection procedure is executed.
4 will be described.

As shown in FIG. 22, the scanning signal lines Gn + 1 and Gn + 3 are selected, but when Gn + 2 is not selected, the first TFT M21 to the third TFT M23 are O.
N is done. Therefore, as shown in FIG. 22, the pixel electrode A
The potential Va1 to be applied to the pixel electrode A21 from the display signal line Dm is written in the pixel electrode 21 and the pixel electrode C21. The potential Va1 of the pixel electrode A21 is determined when the scanning signal lines Gn + 1 and Gn + 2 are selected and Gn + 3 is deselected.

After selecting the scanning signal lines Gn + 1 and Gn + 2 and deselecting Gn + 3, the potential supplied from the display signal line Dm is the potential V to be applied to the pixel electrode B21.
Change to b1. After selecting the scanning signal lines Gn + 1 and Gn + 2 and deselecting Gn + 3, the potential Vb is applied to the pixel electrodes B21 and C21 as shown in FIG.
1 is supplied. Then, when the scanning signal line Gn + 1 is selected and Gn + 2 and Gn + 3 are not selected, the potential Vb1 of the pixel electrode B21 is determined.

Scan signal line Gn + 1 is selected and Gn + 2
And after deselecting Gn + 3, the display signal line Dm
The electric potential supplied from is changed to the electric potential Vc1 to be given to the pixel electrode C21, and the electric potential Vc1 is supplied to the pixel electrode C21 as shown in FIG.

When the potentials are written to the pixel electrodes A21 to C21 within one horizontal scanning period (H Total) in the time division as described above, the potentials of not only the pixel electrode A21 but also the pixel electrode B21 are changed. There is a risk of insufficient writing. The situation is shown in FIG. Note that FIG.
Indicates that the potential writing times TA, TB and TC for the pixel electrodes A21 to C21 are equal (TA = TB = TC).
I am supposed to. In FIG. 25, the pixel electrode C21 is
Since the potentials are written even during the potential writing time (TA and TB) to the pixel electrode A21 and the pixel electrode B21, the writing potential can easily reach the reaching potential. However, since the writing time for the pixel electrode A21 is insufficient, the writing potential of the pixel electrode A21 may not reach the reaching potential. Similarly, for the pixel electrode B21, the writing potential of the pixel electrode A21 may not reach the reaching potential because the writing time is insufficient.

Therefore, as shown in FIG. 26, the pixel electrode A
21 for writing potential TA to the pixel 21 and the pixel electrode B
21 for writing the potential TB to the pixel electrode C21
Longer than the writing time TC of the potential to (T
A, TB> TC). By doing so, the pixel electrode A2
It is possible to solve the shortage of writing in 1 and the pixel electrode B21. On the other hand, although the time TC for writing the potential to the pixel electrode C21 becomes short, the pixel electrode C21
Is pre-charged, there is no shortage of writes.

As described above, the three pixel electrodes A2
Also in the image display device 1 in which 1 to C21 are connected to one display signal line Dm, three pixel electrodes A21 to C2 are also provided.
By adjusting the time for writing the potential to 1 the insufficient writing of the potential to each of the pixel electrodes A21 to C21 can be eliminated.

(Fourth Embodiment) In the second embodiment described above, the liquid crystal display device 1 has its own STB.
I was changing the parameters for. However, this parameter change can also be performed from the system 6 to which the liquid crystal display device 1 is connected. This method has the advantage that the system 6 knows the display mode in the first place and can therefore provide the optimum drive parameters. Therefore, unlike the second embodiment, it is not necessary to measure H Total on the liquid crystal display device 1 side. for that reason,
The H counter 53 and the translator 54 shown in the second embodiment are not required. However, system 6
Needs to acquire information about the liquid crystal display device 1 in order to set and change the parameters.

FIG. 27 is a block diagram showing a configuration for changing the parameters relating to the STB by the system 6 from outside the liquid crystal display device 1. 27, the same components as those in FIG. 1 are designated by the same reference numerals. The liquid crystal display device 1 has a ROM 7 that stores information regarding the liquid crystal display device 1. Information (module information) about the liquid crystal display device 1 stored in the ROM 7, for example, information necessary for setting parameters such as parts and numbers is the communication interface (I / I).
F) 8 is transferred to the system 6.

The system 6 transfers the transferred module information to the communication interface (I / F) 9
It is received by the controller 10 via. The controller 10 provides a video mode to the video timing generator 11. Video mode is H Total
Contains information about. The controller 10 is H
ST based on the received module information and Total
Set parameters for B. The set parameters relating to the STB are output from the controller 10 to the liquid crystal display device 1 via the communication interface (I / F) 9. The controller 10 is H T
Whenever the total is changed, the parameter regarding the STB is reset each time. Video timing generator 11
Outputs the video data to the liquid crystal display device 1 based on the received video mode.

In the liquid crystal display device 1, the timing controller 5 receives the digital video data output from the system 6. Further, in the liquid crystal display device 1, the timing controller 5 receives the parameter regarding the STB output from the system 6 via the communication interface (I / F) 8. timing·
The controller 5 stores the received parameter regarding the STB in the parameter register 51. The timing generator 52 controls the driving of the X driver 3 and the Y driver 4 based on the parameters stored in the parameter register 51 and the received digital video data. As the contents of this control, the contents described in the first to third embodiments may be adopted.

[0073]

As described above, according to the present invention,
It is possible to provide a method of supplying a write potential suitable for an active matrix type display device in which a potential is time-divided from one display signal line to two or more adjacent pixels. More specifically, it is possible to eliminate the insufficient writing to the two or more pixels.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of an X driver according to the first embodiment.

FIG. 3 is a diagram showing a circuit configuration of a display element according to the first embodiment.

FIG. 4 is a diagram showing a flow of video data and a control signal from the system to the display element in the first embodiment.

FIG. 5 is a diagram showing a circuit configuration of a display element according to the first embodiment.

FIG. 6 is a diagram for explaining the operation of the display element according to the first embodiment.

FIG. 7 is a diagram for explaining the operation of the display element according to the first embodiment and is a diagram showing a state next to FIG. 6;

FIG. 8 is a diagram for explaining the operation of the display element according to the first embodiment, and a diagram showing the next state of FIG. 7.

FIG. 9 is a diagram showing a relationship between a potential writing time and a writing potential with respect to a pixel electrode A1 and a pixel electrode B1, showing a writing time with respect to the pixel electrode A1 and a pixel electrode B1.
It is a figure which shows the case where the write time with respect to is equal.

FIG. 10 is a diagram showing the relationship between the potential writing time and the writing potential for the pixel electrode A1 and the pixel electrode B1, showing the writing time for the pixel electrode A1.
FIG. 3 is a diagram showing a case where it is longer than the writing time for 1;

FIG. 11 is a diagram showing parameters set in a parameter register according to the first embodiment.

FIG. 12 is a diagram showing a distribution mode of writing times of the pixel electrode A1 and the pixel electrode B1 with respect to H Total.

FIG. 13 is a diagram showing setting of a display mode according to the second embodiment.

FIG. 14 is a diagram illustrating a problem when the display mode is changed and a method for solving the problem.

FIG. 15 is a block diagram showing a timing controller according to a second embodiment.

FIG. 16 is a diagram showing a circuit configuration of a display element according to a third embodiment.

FIG. 17 is a diagram for explaining the operation of the display element according to the third embodiment.

FIG. 18 is a diagram for explaining the operation of the display element according to the third embodiment and is a diagram showing a state next to that in FIG. 17;

FIG. 19 is a diagram for explaining the operation of the display element according to the third embodiment and is a diagram showing a state next to FIG. 18.

FIG. 20 is a diagram showing the relationship between the potential writing time and the writing potential with respect to the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21, which shows the writing time with respect to the pixel electrode A21, the writing time with respect to the pixel electrode B21, and the pixel electrode C21. It is a figure which shows the case where writing time is equal.

FIG. 21 is a diagram showing a relationship between a potential writing time and a writing potential with respect to the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21, in which the writing time with respect to the pixel electrode A21 is with respect to the writing time with respect to the pixel electrode B21 and the pixel electrode C21. It is a figure which shows the case where it is longer than a writing time.

FIG. 22 is a diagram for explaining another operation example of the display element according to the third embodiment.

FIG. 23 is a diagram for explaining another operation example of the display element in the third embodiment, and a diagram showing the next state of FIG. 22;

FIG. 24 is a diagram for explaining another operation example of the display element in the third embodiment, and a diagram showing a state next to FIG. 23.

FIG. 25 is a diagram showing a relationship between a potential writing time and a writing potential with respect to the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21. FIG. 25 shows a writing time with respect to the pixel electrode A21, a writing time with respect to the pixel electrode B21, and a pixel electrode C21. It is a figure which shows the case where writing time is equal.

FIG. 26 is a diagram showing the relationship between the potential writing time and the writing potential with respect to the pixel electrode A21, the pixel electrode B21, and the pixel electrode C21. The writing time with respect to the pixel electrode A21 and the writing time with respect to the pixel electrode B21 with respect to the pixel electrode C21. It is a figure which shows the case where it is longer than a writing time.

FIG. 27 is a block diagram showing configurations of a system and a liquid crystal display device according to a fourth embodiment.

[Explanation of symbols]

1 ... Liquid crystal display device, 2 ... Display element, 3 ... X driver, 4
... Y driver, 5 ... Timing controller, 6 ... System, 7 ... ROM, 8, 9 ... Communication interface (I / F), 10 ... Controller, 11
… Video timing generator, 31… Driver element, 3
11 ... shift register, 312 ... data register,
313 ... Latch, 314 ... Level shifter, 315 ... D
A converter, 316 ... Amplifier, 51 ... Parameter register, 52 ... Timing generator, 53 ... H counter, 54 ... Translator, A11, B11, C11,
D11 ... Pixel electrode, M1, M21, M2, M22, M
3, M23 ... TFT

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642C (72) Inventor Eisuke Kanzaki 1623 Shimotsuruma, Yamato-shi, Kanagawa Japan AIBM Co., Ltd., Yamato Works (72) Inventor, Manabu Koritsu 1623 Shimotsuruma, Yamato City, Kanagawa Prefecture 14 Japan BM Co., Ltd., Yamato Works (72) Inventor, Kazuhiro Abe Yamato, Kanagawa Prefecture 1623 Shita-Tsuruma, Ichi, Japan F-Term in Yamato Plant, Japan AIBM Co., Ltd. (reference) 2H092 GA24 GA28 GA32 JA24 JB22 JB31 JB41 JB62 JB68 NA25 PA06 2H093 NA16 NA23 NA44 NA47 NB23 NC16 NC22 NC23 NC34 NC35 NC36 ND17 ND20 ND43 ND49 ND52 ND53 ND54 NE01 NE03 NE07 NH14 NH18 5C006 AC22 AF42 BB16 BC03 BC06 EB05 FA26 GA02 5C080 AA10 BB05 DD09 DD30 FF11 JJ02 JJ 04 JJ05

Claims (18)

[Claims] 1. A plurality of display signal lines for transmitting a display signal, a first pixel electrode and a second pixel electrode to which a display signal is written from a common display signal line, the first pixel electrode and the first pixel electrode. A scanning signal line for transmitting a scanning signal to two pixel electrodes, and a first signal corresponding to the first pixel electrode and a second signal corresponding to the second pixel electrode, which are input from the outside. Generate a first display signal and a second display signal based on the above, and supply the first display signal and the second display signal to the display signal line within a predetermined one horizontal scanning period HT in a time division manner. And a signal processing unit for setting the time TA for writing the first display signal and the time TB for writing the second display signal such that TA> TB. Image display device. 2. The second pixel electrode is written with the first display signal during a period of time TA during which the first display signal is written in the first pixel electrode. The image display device according to claim 1. 3. The signal processing means resets the TA and / or the TB on the assumption that TA> TB when the one horizontal scanning period changes. Image display device. 4. The image display device according to claim 1, wherein the signal processing means sets the HT, the TA and the TB so that HT = TA + TB or HT> TA + TB. 5. The image display device according to claim 1, wherein the first pixel electrode and the second pixel electrode are driven with the same polarity within the one horizontal scanning period. 6. The predetermined horizontal scanning period HT is HT =
HD + HB (however, HD is a period in which the first signal or the second signal is input, HB is a period in which the first signal and the second signal are not input), and the signal processing The image display device according to claim 1, wherein the means sets TB to HD / 2 or less. 7. An image display element having a plurality of pixel electrodes arranged in a matrix and provided with a display signal line for transmitting a potential and a scanning signal line for transmitting a scanning signal to each pixel electrode, and the potential. And a signal processing means for generating and supplying the signal to the display signal line, wherein the image display elements are n in the same row (where n is 2 or more). (Integer) pixel electrodes are connected to a common display signal line, and the signal processing unit sets a potential writing time to a predetermined pixel electrode in which a potential is written first in a predetermined horizontal scanning period, and a potential after that. An image display device, which is set to be longer than a writing time for another pixel electrode to be written. 8. The image display device according to claim 1, wherein two pixel electrodes are connected to the common display signal line, and the other pixel electrodes are connected to the other pixel electrode within a period in which a potential is written in one pixel electrode. An electric potential is written, and the signal processing unit is longer than an electric potential writing time for the other pixel electrode.
The image display device according to claim 7, wherein a potential writing time for the one pixel electrode is set to be long. 9. The image display element is configured such that three pixel electrodes are connected to the common display signal line and a potential is written in a predetermined pixel electrode among the three pixel electrodes. The potential is also written to another pixel electrode, and the signal processing unit sets the potential writing time to the predetermined pixel electrode longer than the potential writing time to the other pixel electrode. Item 7. The image display device according to item 7. 10. A potential writing time for a predetermined pixel electrode to which a potential is written first and a writing time to another pixel electrode after which a potential is written are
The image display device according to claim 7, wherein the image display device is set so as to reach a reaching potential with respect to each pixel electrode. 11. A display signal supply device for supplying a write potential to an active matrix type image display element, wherein a write potential for a plurality of pixels is supplied to a predetermined display signal line within one horizontal scanning period. A display signal supply device comprising: a signal supply unit that supplies in a divided manner; and a write time change unit that changes a supply time of the write potential to at least one pixel of the plurality of pixels. 12. The display signal supply device according to claim 11, wherein the write time changing unit changes the supply time of the write potential based on a change of the one horizontal scanning period. 13. The signal supply means sets a supply time of a write potential for a predetermined pixel of the plurality of pixels to be longer than a supply time of a write potential for another pixel. 1
1. The display signal supply device according to 1. 14. The display signal supply according to claim 13, wherein the signal supply unit prioritizes the supply of the write potential to the predetermined pixel over the supply of the write potential to the other pixel. apparatus. 15. A writing potential supply method for supplying a writing potential to an active matrix type image display element, wherein the writing potentials for a plurality of pixels within one horizontal scanning period are based on video data supplied from the outside. And supplying the write potential to a predetermined pixel of the plurality of pixels for longer than the supply time of the write potential to another pixel. 16. The write potential supply method according to claim 15, wherein the write potential is supplied to the plurality of pixels from a common display signal line in a time division manner. 17. Video data for a plurality of pixels is externally received, write potentials for the plurality of pixels are generated based on the video data, and the write is performed for the plurality of pixels in a time division manner within one horizontal scanning period. A method for supplying a write potential to an active matrix type image display device, which supplies a potential, wherein the write potential supply time for each of the plurality of pixels is 1
A writing potential supply method, which is dynamically set based on a horizontal scanning period. 18. The write potential supply method according to claim 17, wherein the write potential supply time for each of the plurality of pixels is changed in accordance with the change of the one horizontal scanning period.