JPH09139819A - Image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly conduct signal processing in a sample-and-hold section and an A/D converter section with respect to an output signal outputted from an image sensor even when the image sensor is driven at a high speed. SOLUTION: The device uses a detection section 17 to detect a timing of an output signal of an image sensor 9 to generate a signal processing clock signal such as a proper sample-and-hold clock signal and a sampling clock signal for A/D conversion synchronously with an output signal of the image sensor 9 and even when the image sensor 9 is driven at a high speed, the signal processing in the sample-and-hold section 15 and the A/D converter section 16 with respect to the output signal outputted from the image sensor 9 is conducted properly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading device for optically reading image information by an image sensor and extracting it as an electric signal in a device such as a scanner, a digital copying machine and a digital facsimile.

[0002]

2. Description of the Related Art FIG. 7 shows a general structure of an image reading apparatus mounted on, for example, a digital copying machine. A light source 2 and a first mirror 3 are mounted below a contact glass 1 on which a document (not shown) is set, and a first traveling body 4 which scans and moves the lower surface of the contact glass 1 in the sub-scanning direction.
Further, a second traveling body 7 which mounts the second and third mirrors 5 and 6 and reciprocates at a speed of 1/2 in the same direction as the first traveling body 4 is provided. An image sensor, for example, a linear CCD (charge coupled device) 9 is provided on the optical path of the third mirror 6 via an imaging lens 8. With such a configuration, the reflected light from the original is received by the CCD 9, converted into an analog electric signal, and output.

Here, the signal processing system after the CCD 9 generally includes a sample and hold unit 10, as shown in FIG.
The zero clamp section 11 and the A / D conversion section 12 are connected in this order. Each part 9, 10, 11, 12
The operation timing of is controlled by a clock or the like generated by the timing generator unit 13. First, CCD
Reference numeral 9 outputs an analog electric signal that is faithful to the reflected light (optical information) from the document in accordance with the transfer clock, shift pulse, and reset pulse generated by the timing generator unit 13 (see the waveform shown in FIG. 9A). ). The output signal from the CCD 9 is sent to the sample & hold unit 10
Is converted into a low frequency signal as shown in FIG.
Here, the operation of the sample & hold unit 10 is controlled by the sample & hold clock generated and output by the timing generator unit 13 as shown in FIG. 9B. That is, sampling is performed while the sample & hold clock is at the L level, and held while the sample & hold clock is at the H level. The output signal from the sample & hold unit 10 is adjusted in the level of the DC component by the zero clamp unit 11, and then the timing generator unit 1
It is converted into a digital signal by the A / D converter 12 in accordance with the sampling clock generated in 3.

[0004]

However, recently,
A CCD driven at a high speed has been developed. However, when the CCD is driven at a high speed, the output period of the output signal from the CCD is shortened, and each is generated by passing through some gates in the timing generator unit 13. Due to the factors such as the variation of the delay time of the clock occupying a large weight within the output period of the output signal of the CCD, the variation per cycle becomes large. As a result,
It is difficult to generate the sample-and-hold clock and the A / D conversion sampling clock, and it may not be possible to accurately sample the output signal from the CCD.

Therefore, the present invention provides an image reading apparatus capable of accurately performing signal processing in a sample & hold section and an A / D conversion section with respect to an output signal output from the image sensor even when the image sensor is driven at high speed. The purpose is to do.

[0006]

According to a first aspect of the invention, an image sensor for receiving reflected light from a document and converting it into an electric signal, and a sample & sample for sampling and holding an output signal from the image sensor. A hold unit and an A / A that converts the output signal sampled and held by the sample and hold unit into a digital signal
An image reading apparatus including a D conversion unit includes a detection unit that detects the timing of the output signal of the image sensor.

Therefore, since the timing of the output signal of the image sensor is detected by the detection unit, a signal processing clock such as an appropriate sample & hold clock synchronized with the output signal of the image sensor or a sampling clock for A / D conversion. Therefore, even if the image sensor is driven at high speed, the signal processing of the output signal output from the image sensor in the sample & hold unit and the A / D conversion unit can be accurately performed.

According to a second aspect of the present invention, in addition to the image reading apparatus according to the first aspect of the present invention, a signal processing clock detected by the detection section and synchronized with the timing of the output signal of the image sensor is generated and sampled. & Hold part and A
A clock generation unit for outputting to the / D conversion unit is provided.

Therefore, even if the image sensor is driven at a high speed, a clock for signal processing such as an appropriate sample & hold clock synchronized with an output signal output from the image sensor and a sampling clock for A / D conversion is provided in the clock generation unit. Is given to the sample & hold section and the A / D conversion section, so that the signal processing can be accurately performed.

According to a third aspect of the present invention, in addition to the image reading apparatus according to the first aspect of the present invention, for signal processing which is a sample and hold clock detected by a detection section and synchronized with the timing of the output signal of the image sensor. It has a clock generation unit that generates a clock and outputs it to the sample & hold unit.

Therefore, even if the image sensor is driven at high speed, a signal processing clock which is an appropriate sample and hold clock synchronized with the output signal output from the image sensor is supplied from the clock generation unit to the sample and hold unit. While the sample & hold processing can be performed accurately, the signal processing in the A / D conversion unit by the A / D conversion clock can be synchronized with the entire system such as the image processing system in the subsequent stage.

According to the invention of claim 4, claim 2 or 3
In the image reading apparatus described above, the clock generator is a PLL.
It is configured to include a circuit. Therefore, the PLL circuit can accurately synchronize the output signal from the image sensor with the signal processing clock such as the sample and hold clock.

[0013]

FIG. 1 shows a first embodiment of the present invention.
A description will be given with reference to FIG. The image reading apparatus of the present invention is applied to an image reading apparatus of a digital copying machine as shown in FIG. 7 as one embodiment thereof, and the configuration of FIG. 7 is used as it is.

First, a line-shaped CCD 9, which is a typical example of an image sensor (solid-state image pickup device), is connected with a timing generator section 14 for giving a transfer clock, a shift pulse and a reset pulse. On the other hand, on the output side of the CCD 9, a sample & hold unit 15 and an A
The / D converter 16 is sequentially connected. Further, a detection unit 17 is connected to the output side of the CCD 9 so as to be branched from the sample & hold unit 15 side. A clock generator 18 is connected to the detector 17. The output side of the clock generation unit 18 is connected to the sample & hold unit 15 and the A / D conversion unit 16.

Here, the detection section 17 has a function of detecting the timing of the output signal from the CCD 9. Specifically, the output signal from the CCD 9 has a waveform having an output signal value (electrical signal) and reset noise with the offset voltage as a reference, as shown in FIG. The detector 19 is configured by the comparator 19 in which the value E ₁ between and is set to the reference value.

As a result, the output signal (synchronous clock) from the detection section 17 (comparator 19) is as shown in FIG. 4 (b) with respect to the output waveform of the CCD 9 as shown in FIG. 4 (a). The pulse waveform is synchronized with the output signal of the CCD 9.

The clock generator 18 has, for example, a delay line structure, and is synchronized with the synchronous clock from the detector 17 as shown in FIG. A sample and hold clock as shown in FIG.
A sampling clock for A / D conversion that is synchronized with the synchronous clock from the detection unit 17 by being delayed by one synchronization clock is generated to generate the A / D conversion unit 1.
6 is output.

Therefore, according to the present embodiment, the sample & hold section 15 and the A / D conversion section 16 perform signal processing in synchronization with the timing of the output signal from the CCD 9, and the signal processing shown in FIGS. ) Produces an output such as here,
The output signal of the CCD 9 is applied to the detection unit 17 by a method with less variation in delay, and an appropriate sample & hold clock is generated only by delaying this with a clock generation unit 18 having a delay line configuration to generate a sample & hold unit. Since it can be assigned to 15, the output signal value portion in the output signal of the CCD 9 can be sampled accurately.
Further, since the A / D conversion unit 16 is sampled using the synchronous clock detected by the detection unit 17, the low frequency output sampled and held by the sample & hold unit 15 can be properly digitized.

Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof will be omitted (the same applies to the following embodiments). In the present embodiment, the clock generation unit 18 is connected only to the sample & hold unit 15, and the sampling clock for the A / D conversion unit 16 is generated by the timing generator unit 14. That is, in the present embodiment, the clock generation unit 18 is configured to generate only the sample & hold clock for the sample & hold unit 15 as the signal processing clock.

Therefore, according to the present embodiment, the output signal of the CCD 9 can be sampled and held at an optimum timing, as in the case of the above-described embodiments. On the other hand, if the sampling clock of the A / D conversion unit 16 depends on the timing of the output signal from the CCD 9, there is a possibility that the timing may differ from the timing of the image processing system in the subsequent stage. Since the sampling clock for D conversion is generated in the timing generator unit 14, the sampling timing of A / D conversion can be synchronized with the entire system.

A third embodiment of the present invention will be described with reference to FIG. In the present embodiment, the phase comparator (PD) 20 and the low-pass filter (LPF) are provided on the output side of the detection unit 17.
21 and a voltage controlled oscillator (VCO) 22
An L circuit 23 is provided, and the PLL circuit 23 constitutes a clock generation unit. Here, the phase comparator 20 compares the output of the detection unit 17 (clock synchronized with the output signal of the CCD 9) with the output signal of the voltage controlled oscillation circuit 22, and determines the difference signal voltage corresponding to the phase difference between the two signals. Output. The low pass filter 21 smoothes the difference signal voltage from the phase comparator 20. The smoothed difference signal voltage is input to the voltage controlled oscillator circuit 22 to generate a signal processing clock having a target phase and frequency.

By using the PLL circuit 23 for synchronization with the output signal of the CCD 9 as in the present embodiment, the synchronization can be accurately achieved and at the timing when the reset noise in the output signal falls. Alternatively, the phase comparator 20 may be configured to compare at the falling edge, and the sample time for sample & hold may be lengthened.

[0023]

According to the first aspect of the invention, since the timing of the output signal of the image sensor is detected by the detection section, an appropriate sample and hold clock synchronized with the output signal of the image sensor or A It becomes possible to generate a signal processing clock such as a sampling clock for A / D conversion. Therefore, even if the image sensor is driven at high speed, a sample & hold unit and an A / D conversion unit for the output signal output from the image sensor. It can be configured to accurately perform signal processing in.

According to the second aspect of the invention, in addition to the image reading apparatus of the first aspect of the invention, a signal processing clock that is detected by the detection section and is synchronized with the timing of the output signal of the image sensor is generated. Since a clock generation unit for outputting to the sample & hold unit and the A / D conversion unit is provided, an appropriate sample & hold clock synchronized with the output signal output from the image sensor even when the image sensor is driven at high speed. A signal processing clock such as a sampling clock for A / D conversion can be given from the clock generation unit to the sample & hold unit and the A / D conversion unit, and thus signal processing can be accurately performed.

According to the third aspect of the invention, in addition to the image reading apparatus of the first aspect of the invention, a signal which is a sample & hold clock detected by the detection section and synchronized with the timing of the output signal of the image sensor. Since it has a clock generation unit that generates a processing clock and outputs it to the sample and hold unit, even if the image sensor is driven at high speed, an appropriate sample and hold clock synchronized with the output signal output from the image sensor. The signal processing clock can be given from the clock generation unit to the sample & hold unit, so that the sample & hold process can be accurately performed, and further, the A / D conversion unit using the A / D conversion clock The signal processing can be synchronized with the entire system such as an image processing system in the subsequent stage.

According to a fourth aspect of the present invention, in the image reading apparatus according to the second or third aspect, the clock generator is P
Since the configuration includes the LL circuit, the PLL circuit can accurately synchronize the output signal from the image sensor with the signal processing clock such as the sample & hold clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an input signal to a detection unit.

FIG. 3 is a block diagram showing a configuration example of a detection unit.

FIG. 4 is a time chart showing operation waveforms of respective parts.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a schematic front view showing the configuration of a general image reading apparatus.

FIG. 8 is a block diagram showing a conventional example.

FIG. 9 is a block diagram showing some operation waveforms.

[Explanation of symbols]

 9 image sensor 15 sample & hold unit 16 A / D conversion unit 17 detection unit 18 clock generation unit 23 PLL circuit

Claims (4)

[Claims] 1. An image sensor for receiving reflected light from an original and converting it into an electric signal, a sample & hold unit for sampling and holding an output signal from the image sensor, and a sample & hold unit for sampling the output signal. An image reading apparatus including an A / D conversion unit that converts the held output signal into a digital signal, the image reading apparatus including a detection unit that detects the timing of the output signal of the image sensor. 2. A clock generation unit for generating a signal processing clock that is detected by the detection unit and synchronized with the timing of the output signal of the image sensor, and outputs the signal processing clock to the sample & hold unit and the A / D conversion unit. The image reading apparatus according to claim 1, wherein the image reading apparatus is an image reading apparatus. 3. A clock generation unit for generating a signal processing clock, which is detected by the detection unit and synchronized with the timing of the output signal of the image sensor, which is a sample & hold clock, and outputs the generated signal to the sample & hold unit. The image reading apparatus according to claim 1, wherein the image reading apparatus is an image reading apparatus. 4. The image reading device according to claim 2, wherein the clock generation unit includes a PLL circuit.