JPH09247394A - Digital reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it easy to design a timing signal for a pixel clock even if the pixel clock is fast. SOLUTION: This device is equipped with a CCD 101 which photoelectrically converts light information corresponding to the light and shade of a document image and outputs an analog electric signal and an A/D converter 103 which converts the analog electric signal outputted from the CCD 101 into a digital electric signal. In this case, the device is equipped with a phase detecting circuit 104 which detects a phase signal from a delay detection signal that is nearly equal to or nearly synchronized with the delay quantity of the output signal of the CCD 101 and a timing generating circuit 105 which generates driving pulses of the A/D converter 103 according to the phase signal detected by the phase detecting circuit 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital reader such as a digital copying machine or an image scanner, and more specifically, it detects a phase signal from analog image data output from a CCD (solid-state image sensor), The present invention relates to a digital reader that controls the timing of signal processing using a phase signal.

[0002]

2. Description of the Related Art A conventional digital reading apparatus using a solid-state image pickup device such as a CCD is shown in FIG. In the figure, 101 is a CCD (solid-state image sensor) that photoelectrically converts the reflected light of the original incident from a reading optical system (not shown) and outputs an image signal, and 102 is a sample hold (S / H)
A circuit, 103 is an A / D converter for converting an analog signal into a digital signal, 104 is a phase detection circuit as a phase signal detection means to be described later, 701 is a sample and hold circuit 102, and timing for giving a timing signal to the A / D converter 103. It is a generation circuit.

Reference numeral 106 denotes the output V _OUT of the CCD 101.
The analog amplifiers (A1) and 107 for amplifying the signal are provided on the signal processing boat side, and the analog amplifiers (A2) and 108 for amplifying the output value of the analog amplifier (A1) 106 temporarily hold the output of the timing generation circuit 105. In order to do so, a buffer provided on the signal processing board side and 109 are buffers provided on the CCD board side for temporarily holding the output of the buffer 108.

In this timing generation circuit 701, CC
Driving frequency of D (solid-state image sensor) 101 (reading frequency)
When the speed becomes faster, it is very difficult to design the timing, and for the timing adjustment, elements such as the delay line 901 are used for adjustment as shown in FIG. In addition, other means such as adjusting the pulse interval by using the high-frequency original oscillation were used.

Further, the above timing adjustment must satisfy the condition as shown in FIG. Here, the most important factor is whether or not the output Vout ′ from the CCD 101 can be sampled and held at the correct timing under any variation conditions, that is, component variations, voltage conditions, temperature and humidity, and the like.

In order to make the sample / hold timing exist, it is necessary to secure the effective width of the image data even when all the conditions are the worst. That is, as shown in FIG. 8, T _f − (TD1 _max + TR _max + TD3 _max −TD2 _min ) = T
It is necessary to satisfy the condition of _SH > 0.

[0007]

However, in the conventional digital reading device as described above, when the pixel clock becomes faster and T _f becomes shorter, the parentheses in the conditional expression above are changed. Since the calculated value has a limit value depending on the element, there is a problem that the above conditional expression is not satisfied and accurate timing cannot be designed.

The present invention has been made in view of the above, and an object thereof is to facilitate the design of the timing signal even when the pixel clock is high speed.

[0009]

In order to achieve the above object, in a digital reading apparatus according to a first aspect of the present invention, optical information is photoelectrically converted according to the density of a document image and an analog electric signal is output. In a digital reading device including a solid-state image sensor and a signal processing means for converting an analog electric signal output from the solid-state image sensor into a digital electric signal, a delay amount of an output signal of the solid-state image sensor is Phase signal detecting means for detecting a phase signal from delay detection signals that are equal or substantially synchronized, and drive pulse generating means for generating a drive pulse for the signal processing means based on the phase signal detected by the phase signal detecting means. It is equipped with and.

That is, since the drive pulse generating means generates the drive pulse of the signal processing means using the signal detected by the phase signal detecting means, it has been difficult or impossible in the conventional absolute timing design. It is possible to generate a timing signal that matches.

Further, in the digital reading apparatus according to the second aspect, the phase signal detecting means uses an analog electric signal output from the solid-state image pickup device as the delay detection signal.

That is, by using the analog image data output from the solid-state image pickup device as the delay detection signal, a signal with the smallest error amount can be obtained and accurate signal processing can be realized.

Further, in the digital reading apparatus according to the third aspect, the drive pulse generation means drives the drive signal of the solid-state image pickup device and the signal processing means based on the phase signal of the phase detection means. The pulse is relatively controlled.

That is, by relatively moving the phase relationship between the drive signal of the solid-state image sensor and the drive signal of the signal processing means, complicated processing of regenerating all the timings with the detected phase is omitted. Therefore, when the image data input to the signal processing means and the timing signal for driving the signal processing means need to satisfy a certain fixed condition, one of the reference clocks is changed to satisfy the above condition. And accurate image processing is realized.

Further, in the digital reading apparatus according to the fourth aspect, the phase signal detecting means detects the phase signal by using the output signal of the non-image effective portion among the output signals of the solid-state image pickup device. It is a thing.

That is, when the phase is detected using the analog image data, stable phase detection can be performed by using the analog image data of the non-image effective portion where the output waveform of the solid-state image sensor is stable. .

Further, in the digital reading apparatus according to the fifth aspect, the drive pulse generating means includes a ring oscillator which generates a plurality of signals having different phases, and the signal generated by the ring oscillator is used to generate the signal. A drive pulse for the processing means is generated.

That is, since ring oscillators are used to generate clocks with different phases required for timing generation, it is economical and many phases are different without using expensive elements such as delay lines. The signal is obtained.

Further, in the digital reading apparatus according to the sixth aspect, the drive pulse generating means latches a plurality of signals having different phases output from the ring oscillator by the phase signal detected by the phase detecting means. Then, the drive pulse of the signal processing means is generated based on the latched signal.

That is, it is possible to statically detect the amount of phase shift by latching a plurality of signals having a phase shift with the phase signal.

Further, in the digital reading apparatus according to the seventh aspect, when the drive pulse generating means uses the latched signal, the drive pulse generating means selects a part of the plurality of signals having different phases and outputs the signal. A drive pulse for the processing means is generated.

That is, when an optimum signal is obtained based on the statically detected phase shift amount information,
By selecting a plurality of signals whose phases are deviated, an economically advantageous circuit configuration can be realized without using an expensive element such as a delay line.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

[Embodiment] (Configuration of Embodiment) FIG. 1 is a block diagram showing a configuration of a timing generation circuit of a digital reading device according to an embodiment. In the figure, 101 is a CCD (solid-state image sensor) that photoelectrically converts the reflected light of the original incident from a reading optical system (not shown) and outputs an image signal, and 102 is the CCD 1
A sample and hold (S / H) circuit for sampling and holding the output of 01, 103 is an A / D converter as a signal processing means for converting an analog signal into a digital signal,
Reference numeral 104 is a phase detection circuit as a phase signal detection means described later, and 105 is a timing generation circuit as a drive pulse generation means described later.

Further, 106 is the output V _OUT of the CCD 101.
The analog amplifiers (A1) and 107 for amplifying the signal are provided on the signal processing boat side, and the analog amplifiers (A2) and 108 for amplifying the output value of the analog amplifier (A1) 106 temporarily hold the output of the timing generation circuit 105. In order to do so, a buffer provided on the signal processing board side and 109 are buffers provided on the CCD board side for temporarily holding the output of the buffer 108.

FIG. 2 is a block diagram showing the internal structure of the timing generation circuit in FIG. In the figure, 20
Reference numeral 1 is a ring oscillator that generates and outputs a plurality of waveforms having different phases required for timing generation, 202 is a latch that latches the output of the ring oscillator 201, and 203 is a drive clock for the sample and hold circuit 102 and the A / D converter 103. A signal processing timing generating unit for generating and outputting, 204 is a selector provided in the signal processing timing generating unit 203, and 205 is a CCD timing generating unit for generating a drive timing signal for the CCD 101.

FIG. 3 shows the phase detection circuit 104 in FIG.
3 is a circuit diagram showing an internal configuration of a gate signal PHSGT
It is configured by a differentiating circuit that is turned on / off by.

(Operation of Embodiment) Next, the timing conditions obtained in the above configuration will be described with reference to the timing charts shown in FIGS. In this embodiment, the sample and hold can be performed at the target position of the image data Vout ′ without being influenced by the delay amounts TD1 and TD2 of the analog image data from the driving clocks φL and φR of the CCD 101. There is.

Further, the image data is sampled and held by the sample and hold circuit 102 and then converted into a digital signal by the A / D converter 103. However, A / DCLK for direct A / D conversion is used. Can also generate a clock at the target position.

In order to realize such timing,
The phase detection circuit 104 detects the phase from the analog image data and corrects each timing based on the phase data. The details will be described below.

The phase detection circuit 104 receives the gate signal PHSGT for detecting the phase and differentiates it (see FIG. 3).
The output of the reference) is turned on, and the signal XSCK in which the edge portion of the image data is detected is created. In the present embodiment,
Although the rising portion of the reset noise (see FIG. 4) is detected, it goes without saying that the falling portion of the reset noise or the falling portion of the image data may be detected.

Next, the tap output of the ring oscillator 201 is latched at the timing of the falling edge of the signal XSCK. In this embodiment, as shown in FIG. 5, a 5-tap type is shown.

Subsequently, the output of the phase detection circuit 104 is latched by the latch 202, and the latched output is fed to the selector 20.
Enter in 4. Further, an optimum signal is selected and output from the output of the ring oscillator 201 and its inverted output based on the data. Here, since OS [4: 0] is latched by the signal processing timing generation unit 203, OS_SEL [4: 0] = 0BH is determined as the selector signal.

Then, by the above OS_SEL [4: 0], the image data Vou shown in the timing chart of FIG. 4 is obtained.
A signal satisfying the timing condition between t'and S / HCLK, A / DCLK, CLK is selected.

As a result, the buffers 108 and 109 and the analog amplifiers 106 and 10 from the driving clock of the CCD 101 to the sampling and holding of the image data.
It is possible to perform timing design ignoring the influence of the delay amounts TD1 and TD2 due to 7. Moreover, in this case, it can be realized without using an expensive element such as a delay line.

Further, in the present embodiment, since the phase is detected by the analog image data, it is advantageous that the shape (waveform) of the analog image data is stable. That is, when the waveform of Vout changes like the signal when reading the document, the phase may not be accurately detected. Therefore, as shown in FIG.
It is more effective to use the analog image data of the non-image effective portion where the waveform of Vout is stable.

By the way, although the timing for signal processing is adjusted in accordance with the image data in the above-mentioned FIG. 2, the same structure can be obtained by changing the driving timing for the CCD 101 as shown in FIG. The effect is obtained.

Although the above embodiments have been described by taking a digital reader such as an image scanner as an example,
The present invention is not limited to this and can be applied to other devices. For example, in a data transmission / reception device, a delay time until a control signal is processed by a device in which a master side device sends a control signal to a slave side device and the master side receives a result processed by the control signal. It can also be applied to a device with unevenness.

(Effects of the Embodiment) Next, the effects of the embodiment described above will be listed.

First, the timing generation circuit generates a drive pulse for the A / D converter 103 by using the signal detected by the phase detection circuit 104, which is difficult or impossible in absolute timing design. It is possible to generate a timing signal that matches.

Second, since the analog image data output from the CCD 101 is used as the delay detection signal to minimize the error amount, accurate signal processing can be performed.

Thirdly, in order to accurately perform image processing on the image data, the image data input to the A / D converter 103 and the timing signal for driving the A / D converter 103 satisfy certain conditions. There is a need. Therefore, the drive signal of the CCD 101 and the A / D converter 103
By relatively moving the phase relationship with the drive signal of, the complicated processing of regenerating all the timings with the detected phase is omitted. Therefore, by changing either one of the reference clocks, the above condition is satisfied. Can be satisfied.

Fourth, when the phase is detected using the analog image data, it is advantageous that the shape (waveform) of the analog image data is stable. That is, when the waveform of Vout changes like the signal when the document is being read, it may not be possible to accurately detect the phase. Therefore, stable phase detection can be performed by using the analog image data of the non-image effective portion in which the waveform of Vout is stable.

Fifth, in the case of generating clocks having different phases required for timing generation, the ring oscillator 2 can be used without using an expensive element such as the delay line 901.
Since 01 is used, a lot of signals with different phases can be obtained economically.

Sixth, by latching a plurality of phase-shifted signals with a phase signal, the phase shift amount can be statically detected. As another method of detecting the phase difference, a method of using a signal that is sufficiently faster than the detected phase and counting the phase shift in time is conceivable. However, in this method, a phase difference of several to several tens ns is detected. It is very difficult to detect accurately.

Seventh, when an optimum signal is obtained based on the statically detected phase shift amount information as described above, by selecting a plurality of phase shift signals, the delay line It is realized with an economically advantageous circuit configuration without using such an expensive element.

[0047]

As described above, according to the digital reading apparatus (Claim 1) of the present invention, the drive pulse generating means uses the signal detected by the phase signal detecting means to generate the drive pulse of the signal processing means. By generating it, it becomes possible to generate a timing signal that was difficult or impossible in the conventional absolute timing design. Therefore, even if the pixel clock is high speed, it is easy to design the timing signal. Can be done.

Further, according to the digital reader (Claim 2) of the present invention, since the analog image data output from the solid-state image sensor is used as the delay detection signal, the signal with the smallest error amount can be obtained. Accurate signal processing is realized.

Further, according to the digital reading apparatus (Claim 3) of the present invention, the phase detected between the drive signal of the solid-state image pickup device and the drive signal of the signal processing means is relatively moved. Since the complicated process of regenerating all the timings is omitted by the above, when it is necessary to satisfy a certain condition of the image data input to the signal processing means and the timing signal for driving the signal processing means, The above conditions can be satisfied by changing either one of the reference clocks, and accurate image processing is realized.

According to the digital reading apparatus of the present invention (Claim 4), when the phase is detected by using the analog image data, the analog of the non-image effective portion in which the output waveform of the solid-state image sensor is stable. Since image data is used, stable phase detection can be performed.

Further, according to the digital reading apparatus (Claim 5) of the present invention, since the ring oscillator is used when clocks having different phases necessary for timing generation are generated, an expensive element such as a delay line is used. Even without using it, it is possible to obtain a large number of signals with different phases, which are economical.

Further, according to the digital reader of the present invention (claim 6), since a plurality of signals having a phase shift are latched by the phase signal, the phase shift amount can be statically detected.

Further, according to the digital reader (Claim 7) of the present invention, when an optimum signal is obtained based on the statically detected phase shift amount information, a plurality of the phase shifts are performed. Since the signal is selected, it is possible to realize an economically advantageous circuit configuration without using an expensive element such as a delay line.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a timing generation circuit of a digital reading device according to an embodiment.

FIG. 2 is a block diagram showing an internal configuration of a timing generation circuit in FIG.

3 is a circuit diagram showing an internal configuration of a phase detection circuit in FIG.

FIG. 4 is a timing chart showing each signal operation of the digital reading device according to the embodiment.

FIG. 5 is a timing chart showing generation and detection signals according to the embodiment.

FIG. 6 is a block diagram showing an internal configuration of another timing generation circuit different from that of FIG.

FIG. 7 is a block diagram showing a configuration of a timing generation circuit of a conventional digital reading device.

FIG. 8 is a timing chart for explaining timing conditions during sample and hold.

FIG. 9 is a block diagram showing a configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

 101 CCD (Solid-State Image Sensor) 103 A / D Converter 104 Phase Detection Circuit 105 Timing Generation Circuit 201 Ring Oscillator 202 Latch 203 Signal Processing Timing Generation Unit 204 Selector 205 CCD Timing Generation Unit

Claims (7)

[Claims] 1. A solid-state image sensor for photoelectrically converting light information according to the light and shade of a document image and outputting an analog electric signal, and a signal for converting an analog electric signal output from the solid-state image sensor into a digital electric signal. In a digital reader equipped with a processing means, a phase signal detecting means for detecting a phase signal from a delay detection signal that is equal or substantially synchronized with the delay amount of the output signal of the solid-state image sensor, and the phase signal detecting means. A drive pulse generating means for generating a drive pulse for the signal processing means based on the phase signal detected by the means. 2. The digital reading apparatus according to claim 1, wherein the phase signal detecting means uses an analog electric signal output from the solid-state image pickup device as the delay detection signal. 3. The drive pulse generation means relatively controls the drive signal of the solid-state image sensor and the drive pulse of the signal processing means based on the phase signal of the phase detection means. The digital reader according to claim 1, wherein 4. The digital reader according to claim 1, wherein the phase signal detecting means detects the phase signal by using the output signal of the non-image effective portion among the output signals of the solid-state imaging device. . 5. The drive pulse generating means includes a ring oscillator for generating a plurality of signals having different phases, and generates a drive pulse for the signal processing means by using a signal generated by the ring oscillator. The digital reading device according to claim 1. 6. The drive pulse generating means latches a plurality of signals having different phases output from the ring oscillator by a phase signal detected by the phase detecting means, and the signal processing means based on the latched signals. 6. The digital reading device according to claim 5, wherein the driving pulse is generated. 7. The drive pulse generating means, when using the latched signal, selects a part of the plurality of signals having different phases and generates a drive pulse of the signal processing means. The digital reader according to claim 6.