JP2012195873A - Signal processing circuit, image reading device, and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a true output signal to be obtained even when performing high-speed drive.SOLUTION: When a differential amplifier circuit 9 obtains a difference between a signal component detected by a sample hold circuit 5 and a reference component detected by a sample hold circuit 7 and outputs it to a subsequent stage as a truly effective signal, a filter circuit 10 makes a signal detection speed in the sample hold circuit 7 lower than a signal detection speed in the sample hold circuit 5, and thereby dispersion of a pixel level due to speed-up is removed by filtering from an output signal itself on which composite noise with plural noise factors combined therein is superimposed, so that only noise with a relatively slow period which causes stripe-like noise appearing in an image is detected.

Description

  The present invention relates to a signal processing circuit, an image reading device such as a scanner equipped with the signal processing device (an image reading unit or a single image reading device mounted in an image forming apparatus such as a digital copying machine, a digital multifunction peripheral, or a facsimile machine), and The present invention relates to an image forming apparatus equipped with the image reading apparatus.

For example, a scanner acquires reflected light from an image surface of a document (hereinafter also simply referred to as “document”), and uses the reflected light to place a CCD (Charge Coupled Device) image sensor (hereinafter simply referred to as “CCD”) on a sensor control board. The image of the original is read by photoelectrically converting it into an electrical signal (image signal).
In such a scanner, a circuit for correcting noise superimposed on an image signal has been actively proposed in recent years, and a typical example is an SSCG (spread spectrum clock generator) correction circuit.

The problem with the noise caused by SSCG is that the offset level, which is the reference level of the output signal, fluctuates by spreading the drive clock and appears as a streak in the image.
As a proposed countermeasure circuit (correction circuit), an output signal is obtained by taking out a signal subjected to SSCG modulation, amplifying the fluctuation of the signal, and taking a difference from the superimposed output signal of the signal. It is already known to correct noise caused by SSCG superimposed on.

  In addition, for noise detection, a CDS (correlated double sampling) circuit is provided, and fluctuation noise is detected by sampling a signal in a non-signal region that does not react to light, and a difference between the detected noise and a signal output is calculated. A proposal to obtain a signal output (image signal) with reduced noise by taking the noise is already known. For example, Patent Document 1 has a problem that offset fluctuation occurs due to the influence of SSCG fluctuation, and in order to solve the problem, each signal in the signal area and the non-signal area is sampled and held by using a CDS circuit. (Also referred to as “S / H”), and a proposal for reducing offset fluctuation by a differential amplifier for obtaining a difference between the signals is disclosed.

  Here, the signal in the non-signal region that does not react to light is a signal within a period (non-signal region) that does not react to light incidence among the output signals for each pixel from the CCD. The signal in the signal region that reacts to light is a signal within a period (signal region) that reacts to light incidence among the output signals for each pixel from the CCD.

However, the conventional correction circuit as described above is only a countermeasure against one noise factor.
That is, when noise countermeasures using a plurality of signals that cause noise are implemented, it is necessary to configure a plurality of countermeasure circuits, which causes a problem that the circuit scale becomes enormous.
In addition, using a CDS circuit and simply detecting each signal in the signal region that reacts to the sensor output light and the non-signal region that does not react to light to detect noise that causes offset fluctuation, high-speed driving is performed. If this is done, the pixel level rampage is significant, so the non-signal area does not have any stable area, and it is not known whether the level obtained by S / H is the noise to be detected or the rampage for each pixel. In addition, when the signal is used for correction, there is a problem of an adverse effect that noise is increased.

  The present invention has been made in view of the above points, and detects noise superimposed on an output signal stably even when high-speed driving is performed, and corrects the detected noise for true output. It is an object to provide a high-quality image by obtaining a signal.

In order to achieve the above object, the present invention provides a signal processing circuit, an image reading apparatus, and an image forming apparatus shown in the following (1) to (10).
(1) Signal detection means for detecting a signal component with respect to an output signal from the signal output means, reference detection means for detecting a reference component serving as a reference for the signal component, and a signal component detected by the signal detection means And a difference output means for taking out the difference between the reference component detected by the reference detection means and outputting it to the subsequent stage as a truly effective signal, the signal detection speed at the reference detection means being A speed delay means for providing a signal slower than the signal detection speed of the signal detection means is provided.

(2) In the signal processing circuit of (1), the signal output means is an image sensor that performs photoelectric conversion, the signal component is a signal component that reacts to light in the output signal from the image sensor, and The reference component is a signal component that does not react to light in the output signal from the image sensor, the signal detection means and the reference detection means are both sample-hold circuits, and the differential output means is a differential amplifier circuit. The speed delay means is a filter.

(3) In the signal processing circuit of (1), the reference detecting means includes the speed delay means.
(4) In the signal processing circuit of (3), the signal output means is an image sensor that performs photoelectric conversion, the signal component is a signal component that reacts to light in the output signal from the image sensor, and The reference component is a signal component that does not react to light in the output signal from the image sensor, the signal detection means is a sample hold circuit, the speed delay means is a filter, and the reference detection means is a sample hold circuit. And the filter, and the differential output means is a differential amplifier circuit.

(5) In the signal processing circuit according to any one of (1) to (4), the reference detection unit includes the reference component from a signal portion that does not react to light including reset noise in the output signal from the signal output unit. Is detected.
(6) In the signal processing circuit according to any one of (1) to (5), a signal buffer means for receiving an output signal from the signal output means (image sensor) is provided after the signal output means. .
(7) In the signal processing circuit according to any one of (1) to (5), the signal detection means and the reference signal detection means are formed on the same semiconductor chip.
(8) In the signal processing circuit of (6), the signal detection means, the reference detection means, and the signal buffer means are formed on the same semiconductor chip.
(9) An image reading apparatus including the signal processing circuit according to any one of (1) to (8).
(10) An image forming apparatus including the image reading apparatus according to (9) and performing an image forming process based on image data read by the image reading apparatus.

  According to the signal processing circuit of the present invention, the difference output means takes the difference between the signal component detected by the signal detection means and the reference component detected by the reference detection means, and outputs it as a truly effective signal to the subsequent stage. In this case, by making the signal detection speed of the reference detection means slower than the signal detection speed of the signal detection means, a true effective signal component can be obtained even when driving at high speed (high speed operation).

It is a block diagram which shows the example of a basic composition of the signal processing circuit by this invention. It is a circuit diagram which shows the specific structural example of the signal processing circuit by this invention. FIG. 3 is a waveform diagram showing an example of an output signal in a dark state when the signal processing circuit shown in FIG. 2 is driven at high speed. FIG. 3 is a waveform diagram showing an example of an output signal when the signal processing circuit shown in FIG. 2 is driven at high speed and light is incident on the CCD 1.

It is a circuit diagram which shows the other specific structural example of the signal processing circuit by this invention. FIG. 3 is a circuit diagram showing an example in which a part of the signal processing circuit shown in FIG. 2 is formed on the same semiconductor chip and integrated. It is the schematic which shows the hardware structural example of the scanner which mounts the control board containing the signal processing circuit shown in FIG. It is the schematic which shows the structural example of the image forming apparatus provided with the scanner carrying the control board containing the signal processing circuit shown in FIG.

It is a circuit diagram which shows the structural example of the noise correction imaging device which uses the conventional CDS circuit. FIG. 10 is a waveform diagram illustrating an example of an output signal during normal operation of the noise correction imaging apparatus illustrated in FIG. 9. FIG. 10 is a waveform diagram illustrating an example of an output signal when the noise correction imaging apparatus illustrated in FIG. 9 is driven at high speed.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
In the following embodiments, noise that detects only the fluctuation noise that has a relatively slow period and affects the image as a streak out of the output signal from the image signal such as a CCD is detected from the output signal itself. A detection unit is provided.

That is, a noise detection unit that detects combined noise after a plurality of noise factors superimposed on an output signal have been combined, instead of performing noise detection from each signal that becomes a noise source.
The noise detection unit can detect only noise having a relatively slow cycle by filtering out the high-frequency noise superimposed on the signal obtained after sampling the non-image area after taking out the output signal on which the synthesized noise is superimposed. It has become a feature.

Therefore, its features will be described in detail. Before entering the description, for convenience of understanding, a noise correction imaging apparatus using a CDS circuit mounted on a conventional scanner and its problems will be described with reference to FIG. Description will be made with reference to FIG.
FIG. 9 is a circuit diagram showing a configuration example of a noise correction imaging apparatus using a conventional CDS circuit.

The scanner equipped with the noise correction imaging device shown in FIG. 9 acquires reflected light from a document, and photoelectrically converts it into an electrical signal (analog image signal) by the CCD 1 arranged in the noise correction imaging device. The original image is read.
The noise correction imaging apparatus constitutes a noise correction circuit that performs noise correction of an output signal using a CDS circuit, and includes a CCD 1, a timing generator (hereinafter abbreviated as “TG”) 2, and an analog delay 3 ( DL1), analog delay device 4 (DL2), sample hold circuit 5 (S / H_sig1), sample hold circuit 6 (S / H_sig2), noise extraction unit 8 having sample hold circuit 7 (S / H_no), A differential amplifier circuit (differential output circuit) 9 is provided.

The CCD 1 is driven in accordance with a drive signal (drive clock) from the TG 2, and photoelectrically converts reflected light from the document and outputs an analog image signal (Vsig).
The TG 2 generates a drive signal and timing signal (trigger signal) necessary for driving the CCD 1 and supplies them to the CCD 1 and the analog delay units 3 and 4.
The analog delay device 3 delays the timing signal from the TG 2 and outputs it as a sample hold signal SH1.
The analog delay device 4 delays the timing signal from TG2 and outputs it as a sample hold signal SH2. Note that the delay times of the timing signals by the analog delay units 3 and 4 are different.

The sample hold circuit 5 receives an analog image signal (hereinafter also simply referred to as “image signal” or “output signal”) Vsig from the CCD 1 so as to obtain a signal component that reacts to light, that is, a signal in the signal region. S / H (sample hold) at the rise timing of the sample hold signal SH1 from 3 and output as a signal V_s / h_sig1 in the signal region.
The sample-and-hold circuit 6 converts the output signal V_s / h_sig1 from the sample-and-hold circuit 5 into a signal component that does not react to light including reset noise, that is, a signal in a non-signal region (feedthrough level in the prior art) of a reference level (reference level). S / H is performed at the rising timing of the sample hold signal SH2 from the analog delay device 4 so that it can be acquired as a component), and is output as a reference level (non-signal region) signal V_s / h_sig2.

The noise extraction unit 8 performs noise extraction using the sample hold circuit 7. The sample and hold circuit 7 rises the sample and hold signal SH2 from the analog delay device 4 at the same timing as the sample and hold circuit 6 so that the output signal Vsig from the CCD 1 can acquire a signal in a non-signal region that does not react to light. S / H is performed at the timing, and is output as a signal V_s / h_no in the non-signal region.
The output signal V_s / h_sig2 from the sample hold circuit 6 and the output signal V_s / h_no from the sample hold circuit 7 are input to the differential amplifier circuit 9 at the subsequent stage.
The differential amplifier circuit 9 outputs the difference between the output signal V_s / h_sig2 from the sample hold circuit 6 and the output signal V_s / h_no from the sample hold circuit 7, thereby removing the noise superimposed on the output signal Vsig. A signal (Vsig_out) is obtained.

Note that an SSCG (Spread Spectrum Clock Generator) is connected to TG2, and a crystal oscillator (not shown) is further connected via the SSCG.
The output signal of the crystal oscillator is a reference clock signal with a fixed frequency and a fixed period, and the clock signal output via the SSCG is a modulated clock signal obtained by shifting the frequency of the reference clock signal with a predetermined period. This modulated clock signal is used as a clock signal for TG2.
The TG 2 is configured by a synchronization circuit, and generates a trigger signal that is a source of various drive signals and sample hold signals of the CCD 1 while synchronizing with a signal obtained by dividing (or multiplying) the modulation clock signal. Output.

FIG. 10 is a waveform diagram showing an example of an output signal during normal operation of the noise-correcting imaging apparatus shown in FIG.
The signal waveform shown in FIG. 10 shows a state in which S / H is performed by the sample hold circuits 5, 6 and 7 on the output signal Vsig in pixel units.
Here, the offset level changes due to the influence of the SSCG (not shown) and the switching frequency of the power source.

When viewed in a long range of one line cycle, the fluctuation fluctuates in synchronization with the above cycle.
An output signal (signal area signal) V_s / h_sig1 obtained by S / H of the output signal Vsig from the CCD 1 at the signal area signal acquisition timing, and its output signal V_s / h_sig1 as a non-signal area signal The output signal (non-signal region signal) V_s / h_sig2 S / H S / H obtained at the acquisition timing causes offset fluctuation, and similarly, the output signal Vsig serving as the reference signal is converted to the non-signal region signal. Since the output signal V_s / h_no from the sample-and-hold circuit 7 that has been S / H at the acquisition timing also fluctuates, the offset fluctuation is caused by taking the difference between the output signal V_s / h_sig2 and the output signal V_s / h_no. The removed true output signal Vsig_out can be obtained .
Therefore, in the signal processing circuit shown in FIG. 9, if the output signal Vsig is an ideal waveform, the signal component (signal in the signal region that reacts to light) and the reference signal component (non-signal region that does not react to light) are simply used. The noise is corrected by taking the difference from the signal ()), and a true output signal such as Vsig_out is obtained.

The noise correction operation according to the prior art has been described with reference to FIGS. 9 and 10. Next, problems with the prior art will be described in detail with reference to FIG.
Certainly, if the waveform of the output signal Vsig is an ideal shape as shown in FIG. 10, it is possible to correct noise and obtain a true output signal even in the prior art.
However, in recent years, as the speed of devices increases, the drive frequency becomes higher and the timing constraints between various drive clocks that must be ensured during one pixel period becomes shorter, and the delay time of the device is fixed. In order to achieve high speed, it becomes difficult to satisfy various timing specifications. Along with this, when driven at a fast frequency, the output signal becomes a signal in which the rampage, overshoot (OS), undershoot (US), and undulation are superimposed for each pixel.

FIG. 11 is a waveform diagram illustrating an example of an output signal when the noise correction imaging apparatus illustrated in FIG. 9 is driven at high speed.
FIG. 11 shows an ideal waveform (illustrated by a broken line) of the output signal Vsig superimposed with an actual image waveform (illustrated by a thick solid line).
High frequency noise is superimposed on the output signal Vsig, and the offset level fluctuates, and the waveform shape is actually collapsed more than shown.

For this reason, if the signal in the non-signal region that does not react to light is simply S / H according to the rise timing of the sample hold signal SH2, S / H is performed including rampage / OS / US / swell for each pixel. It is difficult to accurately detect the reference level of the waveform.
Therefore, when a difference is taken between V_s / h_sig2 and V_s / h_no, pixel violence remains in Vsig_out, and a true output signal cannot be obtained.

In order to solve the above problems, embodiments of the present invention will be described below.
FIG. 1 is a block diagram showing a basic configuration example of a signal processing circuit according to the present invention.
As shown in FIG. 1, the signal processing circuit includes a signal output unit 21, a signal detection unit 22, a reference detection unit 23, and a difference output unit 24.
The signal output unit 21 is a signal output unit that generates and outputs various signals.
The signal detection unit 22 is a signal detection unit that detects a signal component of the output signal from the signal output unit 21.

The reference detection unit 23 is a reference detection unit that detects a reference component serving as a reference for the signal component.
The difference output unit 24 is a difference output unit that takes the difference between the signal component detected by the signal detection unit 22 and the reference component detected by the reference detection unit 23 and outputs the difference as a truly effective signal to the subsequent stage. The difference output unit 24 functions as a speed delay unit that makes the signal detection speed at the reference detection unit 23 slower than the signal detection speed at the signal detection unit 22. A circuit (speed delay circuit) that functions as a speed delay means may be provided alone.

FIG. 2 is a circuit diagram showing a specific configuration example of the signal processing circuit according to the present invention. Parts corresponding to those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.
This signal processing circuit is a noise correction circuit incorporating an actual circuit, and includes a CCD 1, a TG 2, a sample hold circuit 5 (S / H_sig), a sample hold circuit 7 (S / H_no), and a differential amplifier circuit. 9 and a filter circuit 10.

The CCD 1 corresponds to the signal output unit 21 in FIG. 1 and is driven according to the drive signal from the TG 2 to photoelectrically convert the reflected light from the document and output an analog image signal (Vsig).
The TG 2 supplies a drive signal necessary for driving the CCD 1 to the CCD 1 and the timing signal T_s / so that the sample hold circuit 5 can S / H a signal of an effective input signal portion (signal region) that reacts to light. A timing signal T_s / h_no is generated and supplied to the sample and hold circuit 7 so that h_sig is generated and supplied to the sample and hold circuit 5 or the signal in the non-signal region where the sample and hold circuit 7 does not react to light can be S / H. Supply.

The sample hold circuit 5 (S / H_sig) corresponds to the signal detection unit 22 of FIG. 1 so that an output signal (image signal) Vsig from the CCD 1 can acquire a signal in a signal region that reacts to light. Then, S / H is performed at the rising timing of the timing signal T_s / h_sig, and the signal is output as the signal V_s / h_sig in the signal region.
The sample hold circuit 7 (S / H_no), together with the filter circuit 10, functions as the reference detection unit 23 in FIG. 1, and outputs the output signal Vsig from the CCD 1 as a signal in a non-signal region that does not react to light. S / H is performed at the rising timing of the timing signal T_s / h_no so that it can be acquired as a reference level signal, and is output as a reference level (non-signal region) signal V_s / h_no.

The filter circuit 10 performs filtering on the reference level signal V_s / h_no from the sample hold circuit 7 to delay the response, and outputs it as V_s / h_fil.
The differential amplifier circuit 9 corresponds to the differential output unit 24 in FIG. 1 and outputs a difference between the output signal V_s / h_sig from the sample hold circuit 5 and the output signal V_s / h_fil from the filter circuit 10. Thus, the true output signal Vsig_out from which the non-signal component superimposed on the output signal Vsig is removed can be obtained.

  The reason why the filter circuit 10 is provided in the subsequent stage of the sample hold circuit 7 and the response is delayed by using the filter circuit 10 for the output signal V_s / h_sig is that the high frequency noise of the pixel order that increases when the high speed driving is performed. This is to remove a component and take out a slow signal with a relatively slow cycle that causes offset fluctuation.

  In addition, as means for realizing the same effect by means other than the addition of the filter circuit 10, the basic configuration of the sample hold circuit 7 is a switch that is turned on (ON) at the timing of performing S / H, If the capacitor is configured to store charges in order to hold a reference level signal, the switch ON resistance is increased or the capacitance of the capacitor is increased so that the S / H response time for the input signal is increased. There is also a method (noise removal) for avoiding the influence of fluctuations due to the slow, that is, high-frequency noise.

If the purpose is simply to remove high-frequency noise by the filter circuit 10, the filter circuit may be set before or after the sample hold circuit 7.
However, the feature of this embodiment is that only noise that causes offset fluctuation superimposed on the signal itself is detected, and the signal level to be detected must be a reference level.
If the filter circuit 10 is configured in the order of the sample hold circuit 7, the output signal Vsig filters the output signal including the reset noise and the output level of the signal, so that the output signal is smoothed.

Since the shape of the waveform to be S / H is changed in the subsequent stage and a level different from the level that is originally desired to be detected is detected, if differential output is performed by the differential amplifier circuit 9, the noise is reversed. It will be superposed.
Therefore, the order of the sample hold circuit 7 and the filter circuit 10 for detecting noise is important.

FIG. 3 is a waveform diagram showing an example of an output signal in the dark state (state where no light is incident on the CCD 1) when the signal processing circuit (noise correction circuit) shown in FIG. 2 is driven at high speed.
By high-speed driving, the pedestal part of the non-signal region where the S / H is performed for the detection of the reference level in the prior art has no flat part, and the reference level cannot be obtained even if the S / H is simply performed.
In this embodiment, the output signal (Vsig) from the CCD 1 is S / H at a timing at which a signal in the signal region (signal level) that reacts to light can be acquired, and is output as a signal V_s / h_sig in the signal region.

Further, the output signal (Vsig) from the CCD 1 is S / H at a timing at which a signal in a non-signal region that does not react to light can be acquired as a signal of a reference level (a fluctuation level including pixel level fluctuation). Although it is output as the signal V_s / h_no, since the high-frequency component (high-frequency noise) is removed by the subsequent filter circuit 10, it is possible to detect only a slow frequency fluctuation (noise with a slow period) and output it as V_s / h_fil. Note that the high frequency component corresponds to, for example, a thing of MHz order or more. Further, the slow fluctuation of the frequency corresponds to a KHz order, for example.
Therefore, by taking the difference between V_s / h_sig and V_s / h_fil, it is possible to obtain a signal (Vsig_out) having a signal level that reacts to true light from which high-frequency components including pixel fluctuations have been removed (noise corrected).

FIG. 4 is a waveform diagram showing an example of an output signal when the signal processing circuit shown in FIG. 2 is driven at a high speed and light is incident on the CCD 1.
Even when light is incident on the CCD 1, the same offset fluctuation as the offset fluctuation of the output signal Vsig is detected as a reference level, and after detecting the reference level, noise is removed by filtering to detect pixel fluctuations, so that V_s / h_sig and V_s / A true signal output can be obtained by taking a difference from h_fil. Therefore, only the incident light can be obtained as a true signal output.

  Since it is only necessary to detect the offset fluctuation, the timing for S / H of the signal in the non-signal region is not used for noise detection by using the pedestal period of the prior art as the non-signal region (high speed). Therefore, it is more effective to perform noise detection using the entire non-signal period including reset noise having a long period because the period is very short and the waveform fluctuation and undulation are severe.

  In this way, the differential amplifier circuit 9 (difference output unit 24) detects the signal component detected by the sample hold circuit 5 (signal detection unit 22) and the reference component detected by the sample hold circuit 7 (reference detection unit 23). When the signal detection speed in the sample and hold circuit 7 is made slower than the signal detection speed in the sample and hold circuit 5, Even when the processing circuit is driven at high speed, a true effective signal component can be obtained.

  That is, even when high-speed driving is performed, from the output signal itself on which the synthesized noise in which a plurality of noise factors are synthesized by the sample-and-hold circuit 7 and the filter circuit 10 serving as a noise detection unit is superimposed, the speed increases. The pixel level fluctuation is removed by filtering, and only the relatively slow noise that causes streak noise appearing in the image is detected, and the difference between the detected noise and the output signal on which the original synthesized noise is superimposed By taking this, a noise-corrected output signal can be obtained. Therefore, it is possible to provide a high-quality image.

  Further, the sample and hold circuit 7 detects the reference component from the signal portion that does not react to the light including reset noise in the output signal from the CCD 1 (signal output unit 21), so that the reference component corresponding to the reset noise is included. Since the detection period can be widened, signal detection can be performed with high accuracy.

FIG. 5 is a circuit diagram showing another specific configuration example of the signal processing circuit according to the present invention. Parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.
In this signal processing circuit, the buffer 11 which is a signal buffer means is provided in the subsequent stage of the CCD 1, so that it is possible to avoid as much as possible that external noise is superimposed during signal propagation from the CCD 1 to the sample hold circuits 5 and 7.

When a circuit is actually configured on a substrate, there are restrictions on the substrate size and device terminal arrangement, and it is difficult to wire all signals at equal distances between signal output and signal input. As a result, there will be a long signal turn. Since the possibility of receiving external noise increases as the propagation distance increases, providing the buffer 11 can lower the impedance and enhance noise resistance.
The buffer 11 may be arranged before the differential amplifier circuit 9 (difference output unit 24 in FIG. 1).

FIG. 6 is a circuit diagram showing an example in which a part of the signal processing circuit (noise correction circuit) shown in FIG. 2 is formed and integrated on the same semiconductor chip.
The sample hold circuit 5 (S / H_sig), sample hold circuit 7 (S / H_no), differential amplifier circuit 9, and filter circuit 10 of the signal processing circuit (noise correction circuit) shown in FIG. Thus, by forming and integrating on the same semiconductor chip 50, space saving and low cost can be realized.
Note that the buffer 11 of FIG. 5 may be included in the semiconductor chip 50 and formed.

  As described above, the embodiment in which the present invention is applied to a signal processing circuit that can be mounted on a scanner that reads an image of an original with a CCD has been described. However, the present invention is not limited to this, and the present invention can be applied to a scanner that reads an image of an original with another image sensor. In addition to the signal processing circuits that can be mounted, of course, a signal processing circuit that can be mounted on another image reading device that reads an image of an original by those image sensors, an image reading device that includes the signal processing circuit, and the image reading device are mounted. The present invention can also be applied to various image forming apparatuses such as digital copying machines, facsimile machines, and printers. The image forming apparatus main body can print the image data from the image reading apparatus on a print medium as a visible image.

FIG. 7 is a schematic diagram showing a hardware configuration example of a scanner on which the control board including the signal processing circuit shown in FIG. 2 is mounted. The same parts (CCD 1) as those in FIGS. Yes.
This scanner 100 is of a flat bed type, and a contact glass 101 which is a document glass on which a document is placed is installed on the upper surface of the main body.
Below the contact glass 101, the first carriage 106 and the second carriage 107 are arranged to move in the direction of arrow A (sub-scanning direction) at a speed of 2 to 1.

A halogen lamp 102 and a first mirror 103 as a light source are mounted on the first carriage 106, and a second mirror 104 and a third mirror 105 are mounted on the second carriage 107.
The reflected light from the original irradiated by the halogen lamp 102 is reflected by the first mirror 103, the second mirror 104, and the third mirror 105, enters the imaging lens 108, and is collected by the imaging lens 108. The analog electrical signal imaged on the imaging surface of the CCD (linear image sensor) 1 and photoelectrically converted by the CCD 1 includes the signal processing circuit shown in FIG. 2 (or the signal processing circuit shown in FIG. 5). It is converted to digital image data (original image data) by the substrate 109 and sent to the subsequent stage.

On the other hand, in order to make the distribution of the image data of the document in the main scanning direction (direction orthogonal to the sub-scanning direction) uniform, shading correction is performed, but it is necessary to acquire read data of the reference white plate 111 for that purpose.
In order to perform shading correction, the surface of the reference white plate 111 is read by illumination by the halogen lamp 102 before reading the image of the document, and shading correction at the time of reading the image of the document is performed based on the reading result (read data). Done.

Here, the reason why the first and second carriages 106 and 107 move in the sub-scanning direction at a speed of 2 to 1 is to keep the optical path length from the original surface to the imaging surface of the CCD 1 constant. Is mounted on the control board 109.
Further, a pressure plate 110 is provided so as to be openable and closable so as to cover the upper surface of the contact glass 101, so that external light does not enter the CCD 1 when a document is placed on the contact glass 101. Instead of the pressure plate 110, an ADF (automatic document feeder) or ARDF may be provided so that the document can be automatically fed.

FIG. 8 is a schematic diagram showing a configuration example of an image forming apparatus including a scanner on which a control board including the signal processing circuit shown in FIG. 2 is mounted. The same parts as those in FIGS. It is attached.
The image forming apparatus 200 includes a scanner 100 and a printer 120.
The scanner 100 includes a control board including a CCD 1 and a TG 2, sample hold circuits 5 and 7, a differential amplifier circuit 9, a filter circuit 10, an A / D converter 112, and an LVDS (Low Voltage Differential Signaling) 113. The output signal from the amplifier circuit 9 is converted into digital image data by the A / D converter 112 and sent to the LVDS 113.

On the other hand, the printer 120 includes a printer engine 121 and a control unit 122 that controls the printer engine 121, and both are communicably connected via an I / F 123.
The control unit 122 includes a CPU 124, an image processing circuit 125, and an LVDS 126.
The CPU 124 is communicably connected to the TG 2 and controls the printer engine 121 based on digital image data input via the LVDS 126 to form an image on a medium such as recording paper. Since there are various image forming processes of the printer engine 121 and any type of printer engine can be used, description of the printer engine is omitted.

Of course, the signal processing circuit in the control board mounted on the scanner shown in FIG. 7 or the image forming apparatus shown in FIG. 8 may be the one shown in FIG.
In the present invention, a true effective signal component can be obtained from the signal processing circuit even when driven at high speed. Therefore, by applying the present invention to an image forming apparatus such as a scanner or a copying machine, stable operation and high performance can be achieved. A reliable system can be realized and high-quality images can be obtained.
In addition, this invention is not limited to embodiment mentioned above, It cannot be overemphasized that all the technical matters contained in the technical idea described in the claim are object.

  As is apparent from the above description, according to the present invention, a true effective signal component can be obtained even when driven at high speed. Accordingly, it is possible to provide a signal processing circuit, an image reading apparatus, and an image forming apparatus that can obtain a true effective signal component even when driven at high speed.

1: CCD 2: TG (timing generator)
5, 7: Sample hold circuit 9: Differential amplifier circuit 10: Filter circuit 11: Buffer 21: Signal output unit 22: Signal detection unit 23: Reference detection unit 24: Difference output unit 50: Semiconductor chip 100: Scanner 109: Control Substrate 200: Image forming apparatus

JP 2000-224392 A

Claims (10)

Signal detection means for detecting a signal component with respect to an output signal from the signal output means;
Reference detection means for detecting a reference component which is a reference of the signal component;
A signal processing circuit having difference output means for taking a difference between the signal component detected by the signal detection means and the reference component detected by the reference detection means and outputting the difference to a subsequent stage as a truly effective signal,
A signal processing circuit comprising speed delay means for making a signal detection speed of the reference detection means slower than a signal detection speed of the signal detection means. The signal output means is an image sensor that performs photoelectric conversion,
The signal component is a signal component that reacts to light in the output signal from the image sensor,
The reference component is a signal component that does not react to light in the output signal from the image sensor,
The signal detection means and the reference detection means are both sample hold circuits,
The differential output means is a differential amplifier circuit;
The signal processing circuit according to claim 1, wherein the speed delay unit is a filter.   The signal processing circuit according to claim 1, wherein the reference detection unit includes the speed delay unit. The signal output means is an image sensor that performs photoelectric conversion,
The signal component is a signal component that reacts to light in the output signal from the image sensor,
The reference component is a signal component that does not react to light in the output signal from the image sensor,
The signal detection means is a sample and hold circuit,
The speed delay means is a filter;
The reference detection means includes a sample hold circuit and the filter,
4. The signal processing circuit according to claim 3, wherein the differential output means is a differential amplifier circuit.   5. The reference detection unit according to claim 1, wherein the reference detection unit detects the reference component from a signal portion that does not react to light including reset noise in the output signal from the signal output unit. A signal processing circuit according to 1. In the signal processing circuit according to any one of claims 1 to 5,
A signal processing circuit characterized in that signal buffer means for receiving an output signal from the signal output means is provided at a subsequent stage of the signal output means.   6. The signal processing circuit according to claim 1, wherein the signal detection unit and the reference detection unit are formed on the same semiconductor chip.   7. The signal processing circuit according to claim 6, wherein the signal detection means, the reference detection means, and the signal buffer means are formed on the same semiconductor chip.   An image reading apparatus comprising the signal processing circuit according to claim 1.   An image forming apparatus comprising the image reading apparatus according to claim 9, wherein an image forming process is performed based on image data read by the image reading apparatus.

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