JPH09139555A - Ceramic substrate and its manufacture - Google Patents

Ceramic substrate and its manufacture

Info

Publication number
JPH09139555A
JPH09139555A JP7322294A JP32229495A JPH09139555A JP H09139555 A JPH09139555 A JP H09139555A JP 7322294 A JP7322294 A JP 7322294A JP 32229495 A JP32229495 A JP 32229495A JP H09139555 A JPH09139555 A JP H09139555A
Authority
JP
Japan
Prior art keywords
ceramic substrate
electrodes
electrode
dividing
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7322294A
Other languages
Japanese (ja)
Inventor
Shinichiro Tsuboi
新一郎 坪井
Nobuhiko Nakai
信彦 中井
Masazumi Miyama
正純 深山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hokuriku Electric Industry Co Ltd
Original Assignee
Hokuriku Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hokuriku Electric Industry Co Ltd filed Critical Hokuriku Electric Industry Co Ltd
Priority to JP7322294A priority Critical patent/JPH09139555A/en
Publication of JPH09139555A publication Critical patent/JPH09139555A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a substrate wherein conductive paste for forming electrodes does not ooze out into division trenches, and electrodes are not short-circuited, and a manufacturing equipment of the substrate. SOLUTION: In order to take out many substrates of chip electronic components like chip resistors, a plurality of division trenches 28a, 28b are formed in the length and breadth directions, in a ceramic substrate 32. A plurality of pairs of electrodes 6 are formed on the ceramic board 32. In the division trench 28a in the direction between each pair of electrodes, an intercepting part 30 wherein the division trench 28a is partly shallowed in the vicinity of the electrode 6 is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、いわゆるチップ
状の電子部品の絶縁基板を形成するセラミック基板とそ
の製造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate for forming an insulating substrate for a so-called chip-shaped electronic component and a manufacturing apparatus therefor.

【0002】[0002]

【従来の技術】先ず、絶縁基板2がセラミックで形成さ
れたチップ抵抗器1を、図6に示す。このチップ抵抗器
1の製造方法は、焼成前のセラミックのグリーンシート
に、直交する多数の刃が一定間隔で設けられている金型
を押し付けて、各々直交する分割溝12a、12bを形
成する。そして、このグリーンシートを焼成して、図5
に示す大型のセラミック基板14ができ上がる。次に、
分割溝12aをはさんで所定間隔で第一電極6を、メタ
ルグレーズペースト等で複数列印刷し、再び焼成し、同
様に第二電極7、抵抗体3、ガラスコート11を、順次
印刷と焼成を繰り返して形成する。この後、セラミック
基板14を、一方の分割溝12aで一列毎に分割し、そ
の分割端面を覆うように第三電極8を塗布し、焼成す
る。更に、Niメッキ9、ハンダメッキ10を順次この
電極表面に施し、そして抵抗体3の表面に保護コート1
2を施す。最後に、分割溝12bで個々に分割し、独立
したチップ抵抗器1を完成させる。
2. Description of the Related Art First, a chip resistor 1 whose insulating substrate 2 is made of ceramic is shown in FIG. In the method for manufacturing the chip resistor 1, a die having a large number of orthogonal blades at regular intervals is pressed against a green ceramic sheet before firing to form orthogonal division grooves 12a and 12b. Then, by firing this green sheet,
The large-sized ceramic substrate 14 shown in FIG. next,
A plurality of rows of the first electrodes 6 are printed with a metal glaze paste or the like at predetermined intervals across the dividing groove 12a and fired again. Similarly, the second electrode 7, the resistor 3 and the glass coat 11 are sequentially printed and fired. Are repeatedly formed. After that, the ceramic substrate 14 is divided into rows by one of the division grooves 12a, and the third electrode 8 is applied so as to cover the division end face and fired. Further, Ni plating 9 and solder plating 10 are sequentially applied to the surface of this electrode, and a protective coating 1 is applied to the surface of the resistor 3.
Apply 2. Finally, the chip grooves 1 are individually divided by the dividing grooves 12b to complete the independent chip resistor 1.

【0003】[0003]

【発明が解決しようとする課題】上記従来の技術の場
合、第一電極6や第三電極8を印刷する際に、分割溝1
2aと直交する分割溝12bに、導電性ペーストが毛細
管現象によりにじみ出して延出し、両端の第一電極6が
分割溝12b内で互いに接触して導通状態になってしま
うという不良が発生することがあった。これは、特にチ
ップの大きさが小さくなるほど現れやすい問題である。
In the case of the above-mentioned conventional technique, when the first electrode 6 and the third electrode 8 are printed, the dividing groove 1 is formed.
The conductive paste oozes out and extends into the dividing groove 12b orthogonal to 2a due to a capillary phenomenon, and the first electrodes 6 at both ends come into contact with each other in the dividing groove 12b to be in a conductive state. was there. This is a problem in which the smaller the chip size, the more likely it is to appear.

【0004】この発明は、上記従来の技術の問題点に鑑
みてなされたもので、電極を形成する導電性ペーストが
分割溝ににじみ出さず、電極がショートしてしまうこと
のないセラミック基板とその製造装置を提供することを
目的とする。
The present invention has been made in view of the above-mentioned problems of the prior art, and a ceramic substrate and a conductive substrate which form an electrode do not ooze out into the dividing groove and the electrode is not short-circuited. An object is to provide a manufacturing apparatus.

【0005】[0005]

【課題を解決するための手段】この発明は、チップ抵抗
器等のチップ電子部品の基板を多数個取りするために、
縦横にそれぞれ複数本の分割溝が形成されたセラミック
基板であって、このセラミック基板に設けられる複数対
の電極の各一対の電極間方向の分割溝内に、上記電極近
傍で上記分割溝を部分的に浅くしたり幅狭にしたりして
小さくした遮断部が設けられたセラミック基板である。
SUMMARY OF THE INVENTION In order to obtain a large number of substrates for chip electronic parts such as chip resistors,
A ceramic substrate in which a plurality of dividing grooves are formed in each of the vertical and horizontal directions, and the dividing grooves are formed in the vicinity of the electrodes in the dividing grooves in a pair of electrodes of a plurality of pairs of electrodes provided in the ceramic substrate. The ceramic substrate is provided with a cutoff portion that is made shallower or narrower.

【0006】またこの発明は、チップ電子部品の基板を
多数個取りするため、複数の分割溝を有したセラミック
基板を形成するセラミック基板の製造装置であって、平
板上に、上記セラミック基板の表面に分割溝を形成する
複数本の突条が縦横にそれぞれ設けられ、上記セラミッ
ク基板に設けられる複数対の電極の各一対の電極間方向
の分割溝を形成する上記突条の一部が、高さ方向または
幅方向に切り欠かれている金型を備えたセラミック基板
の製造装置である。
Further, the present invention is an apparatus for manufacturing a ceramic substrate for forming a ceramic substrate having a plurality of dividing grooves for picking up a large number of substrates for a chip electronic component, wherein the surface of the ceramic substrate is on a flat plate. A plurality of ridges for forming dividing grooves are provided vertically and horizontally, and a part of the ridges for forming dividing grooves in the direction between each pair of electrodes of the plurality of pairs of electrodes provided on the ceramic substrate is It is an apparatus for manufacturing a ceramic substrate provided with a die cut out in the depth direction or the width direction.

【0007】この発明のセラミック基板は、セラミック
基板に電極を導電性ペーストで印刷する際、電極近傍の
分割溝に導電性ペーストがしみ出した際にも、しみ出し
た導電性ペーストが分割溝内の遮断部で遮られ、ショー
トすることがない。
In the ceramic substrate of the present invention, when the electrodes are printed on the ceramic substrate with the conductive paste, even if the conductive paste oozes into the dividing grooves near the electrodes, the conductive paste exuded is kept in the dividing grooves. There is no short-circuit because it is blocked by the shut-off part of.

【0008】[0008]

【発明の実施の形態】以下、この発明の実施形態につい
て、図面に基づいて説明する。この実施形態のセラミッ
ク基板の製造装置は、図1に示す平板状の金型20を有
している。金型20は金属製で、平板22の片面に直交
する複数本の突条である刃24a、24bが設けられて
いる。そして、刃24a、24bの断面形状は、先端が
鋭角の三角形で、高さは0.25mm程度である。刃2
4aは、刃24bとの交点から交点までの間は、長辺が
約1mmで短辺が約0.5mmであり、この間に2カ所
切り欠き部26が設けられている。切り欠き部26は、
刃24a、24bの交点からそれぞれ0.2〜0.4m
mの位置で、電極形成部近傍に位置し、幅0.1mm程
度に設けられている。
Embodiments of the present invention will be described below with reference to the drawings. The ceramic substrate manufacturing apparatus of this embodiment has a flat plate-shaped mold 20 shown in FIG. The mold 20 is made of metal, and is provided with blades 24a and 24b, which are a plurality of ridges orthogonal to one surface of a flat plate 22. The cross-sectional shape of the blades 24a, 24b is a triangular shape with a sharp tip and a height of about 0.25 mm. Blade 2
4a has a long side of about 1 mm and a short side of about 0.5 mm from the point of intersection with the blade 24b to the point of intersection, and two notches 26 are provided therebetween. The cutout 26 is
0.2 to 0.4 m from the intersection of the blades 24a and 24b
It is located in the vicinity of the electrode formation portion at a position of m and is provided with a width of about 0.1 mm.

【0009】次に、金型20を使用したチップ抵抗器の
製造方法を図2、図3に基づいて説明する。まず、いわ
ゆるドクターブレード法により、焼成前のセラミックス
のグリーンシートを作る。このグリーンシートの製法は
公知のもので、原料の粉体と溶剤その他を混合し、バイ
ンダーを加えて更に混練し、所定のキャリアテープ上に
これを一定の厚さで塗り、乾燥させてグリーンシートを
作る。このグリーンシートを金型20によりプレスし
て、直交する分割溝28a、28bを形成する。分割溝
28aには、分割溝28bとの交点から交点までの間
に、分割溝28aが形成されていない2カ所の遮断部3
0が設けられている。遮断部30は、金型20の切り欠
き部26によるもので、分割溝28a、28bの交点か
らそれぞれ0.2〜0.4mmの位置に0.1mm幅で
分割溝28aを埋めたものである。そして、分割溝28
a、28bが形成されたグリーンシートは、所定の温度
で焼成され、セラミック基板32となる。
Next, a method of manufacturing a chip resistor using the mold 20 will be described with reference to FIGS. First, a so-called doctor blade method is used to prepare a ceramic green sheet before firing. This green sheet is produced by a known method. A powder of a raw material is mixed with a solvent and the like, a binder is added and further kneaded, and this is coated on a predetermined carrier tape with a constant thickness and dried to obtain a green sheet. make. This green sheet is pressed by the mold 20 to form the dividing grooves 28a and 28b which are orthogonal to each other. In the dividing groove 28a, between the intersecting points with the dividing groove 28b and between the intersecting points, there are two blocking portions 3 in which the dividing groove 28a is not formed.
0 is provided. The blocking portion 30 is formed by the cutout portion 26 of the mold 20, and is formed by filling the dividing groove 28a with a width of 0.1 mm at a position of 0.2 to 0.4 mm from the intersection of the dividing grooves 28a and 28b. . Then, the dividing groove 28
The green sheet on which a and 28b are formed is fired at a predetermined temperature to become the ceramic substrate 32.

【0010】そして、セラミック基板32に、分割溝2
8bをはさんで所定間隔で、第一電極6となるAg−P
t等のメタルグレーズペーストやAg−レジンペースト
等の導電性ペーストを複数列印刷する。このとき、導電
性ペーストが、第一電極6と直交する分割溝28aに毛
細管現象によりしみ出すが、その近傍にある遮断部30
で塞き止められる。その後、所定の温度で焼成し第一電
極6を形成する。さらに同様にして第二電極7を、セラ
ミック基板32の裏面に、第一電極6と対向する位置に
印刷し焼成する。さらに第一電極6の間のセラミック基
板36上にマトリクス状に多数の抵抗体3を形成し、焼
成する。この後、抵抗体3の表面にガラスや樹脂等の保
護コート11を施し平均680℃で焼成する。
The dividing groove 2 is formed on the ceramic substrate 32.
Ag-P which becomes the first electrode 6 at a predetermined interval with 8b in between.
A plurality of rows of conductive paste such as metal glaze paste such as t or Ag-resin paste is printed. At this time, the conductive paste exudes into the dividing groove 28a orthogonal to the first electrode 6 by the capillary phenomenon, but the blocking portion 30 in the vicinity thereof is present.
Can be blocked by. Then, it is baked at a predetermined temperature to form the first electrode 6. Similarly, the second electrode 7 is printed on the back surface of the ceramic substrate 32 at a position facing the first electrode 6 and fired. Further, a large number of resistors 3 are formed in a matrix on the ceramic substrate 36 between the first electrodes 6 and fired. After that, the surface of the resistor 3 is coated with a protective coat 11 such as glass or resin and baked at an average of 680 ° C.

【0011】この後、セラミック基板32を分割溝28
bに沿って一列毎に分割し、その分割面にAg−レジン
系等の導電性ペーストの第三電極8を、約20μの厚み
に塗布し、200℃程度の温度で硬化させる。そして、
Niメッキ、ハンダメッキを各々順次施す。最後にセラ
ミック基板32を分割溝28aに沿って個々に分割し、
独立したチップ抵抗器となる。
After that, the ceramic substrate 32 is divided into the dividing grooves 28.
It is divided into rows along b, and the third electrode 8 of a conductive paste of Ag-resin system or the like is applied to the divided surface to a thickness of about 20 μm and cured at a temperature of about 200 ° C. And
Ni plating and solder plating are sequentially applied. Finally, the ceramic substrate 32 is individually divided along the dividing grooves 28a,
It becomes an independent chip resistor.

【0012】この実施形態のセラミック基板32は、印
刷される電極の近傍に分割溝28aの遮断部30が設け
られており、第一電極6や第三電極8を印刷する導電性
ペーストが分割溝28aににじみ出しても、遮断部30
で塞き止められるため、両側の第一電極6がショートし
てしまう不良を防ぐことができる。また、遮断部30は
一部の狭い範囲で設けられており、遮断部30以外の部
分は十分な長さの分割溝28aが確保されているので容
易に分割することができる。さらに、金型20の刃24
aを一部切除するだけなので、簡単でコストもかからな
い。
In the ceramic substrate 32 of this embodiment, a blocking portion 30 for the dividing groove 28a is provided in the vicinity of an electrode to be printed, and a conductive paste for printing the first electrode 6 and the third electrode 8 is formed in the dividing groove. Even if it oozes out to 28a, the blocking portion 30
Since the first electrodes 6 on both sides are short-circuited by the above, it is possible to prevent a defect that the first electrodes 6 on both sides are short-circuited. In addition, since the blocking portion 30 is provided in a part of a narrow range, and the portion other than the blocking portion 30 is provided with the dividing groove 28a having a sufficient length, it can be easily divided. Furthermore, the blade 24 of the mold 20
It is easy and cost-free because only part of a is cut off.

【0013】次にこの発明の第二実施形態について図4
に基づいて説明する。ここで、上記実施形態と同様の部
材は、同一符号を付して説明を省略する。この実施形態
の金型32は、刃24aは、刃24bとの交点から交点
までの間に2カ所切り欠き部34が設けられている。切
り欠き部34は、刃24a、刃24bの交点からそれぞ
れ0.2〜0.4mmの位置に設けられ、刃24aを水
平に真横に見たとき逆三角形をしており、下方の一頂点
は平板表面に到達している。この実施形態の金型32に
よっても上記実施形態と同様の効果を得ることができ
る。
Next, a second embodiment of the present invention will be described with reference to FIG.
It will be described based on. Here, the same members as those in the above embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the mold 32 of this embodiment, the blade 24a is provided with two notches 34 between the points of intersection with the blade 24b. The notch 34 is provided at a position of 0.2 to 0.4 mm from the intersection of the blade 24a and the blade 24b, and has an inverted triangle when the blade 24a is viewed horizontally horizontally, and one lower vertex is It has reached the flat plate surface. With the mold 32 of this embodiment, the same effect as that of the above embodiment can be obtained.

【0014】この発明は、上記各実施形態に限定される
ものではなく、例えば金型20、32の切り欠き部2
6、34は平板22の表面に達しないくぼみ程度でも良
く、幅方向に切り欠いて、形成される分割溝の幅を狭く
するようにしたものでも良い。従って、遮断部34は、
メタルグレーズペースト等の導電性ペーストが確実に塞
き止められる形状の遮断部を、セラミック基板の分割溝
に形成可能なものであれば良い。
The present invention is not limited to the above-mentioned respective embodiments, and for example, the cutout portion 2 of the molds 20 and 32.
The recesses 6 and 34 may be recesses that do not reach the surface of the flat plate 22, or may be notched in the width direction so as to narrow the width of the dividing groove to be formed. Therefore, the blocking unit 34
It suffices as long as it is possible to form, in the dividing groove of the ceramic substrate, a blocking portion having a shape capable of reliably blocking the conductive paste such as the metal glaze paste.

【0015】[0015]

【発明の効果】この発明のセラミック基板とその製造装
置は、電極形成時に各電極が互いにショートする不良が
発生せず、且つ基板の分割も容易に行なうことができ
る。特に、小型のチップ電子部品で電極間距離が短い場
合も、電極間でショートすることはない。
The ceramic substrate and the manufacturing apparatus for the same according to the present invention do not cause a defect in which the electrodes are short-circuited with each other when the electrodes are formed, and the substrate can be easily divided. In particular, even in the case of a small chip electronic component having a short distance between electrodes, there is no short circuit between the electrodes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第一実施形態の金型を示す部分斜視
図である。
FIG. 1 is a partial perspective view showing a mold according to a first embodiment of the present invention.

【図2】この第一実施例のセラミック基板を示す部分斜
視図である。
FIG. 2 is a partial perspective view showing the ceramic substrate of the first embodiment.

【図3】この第一実施例のチップ抵抗器の一製造工程の
状態を示す斜視図である。
FIG. 3 is a perspective view showing a state of one manufacturing process of the chip resistor of the first embodiment.

【図4】この発明の第二実施例の金型を示す斜視図であ
る。
FIG. 4 is a perspective view showing a mold according to a second embodiment of the present invention.

【図5】従来の技術のセラミック基板を示す斜視図であ
る。
FIG. 5 is a perspective view showing a conventional ceramic substrate.

【図6】従来の技術のチップ抵抗器を示す断面図であ
る。
FIG. 6 is a cross-sectional view showing a prior art chip resistor.

【符号の説明】[Explanation of symbols]

20 金型 22 平板 24a,24b 刃 26 切り欠き部 32 セラミック基板 28a,28b 分割溝 30 遮断部 20 mold 22 flat plate 24a, 24b blade 26 notch 32 ceramic substrate 28a, 28b dividing groove 30 blocking part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 チップ電子部品の基板を多数個取りする
ために、縦横にそれぞれ複数本の分割溝が形成されたセ
ラミック基板において、このセラミック基板に設けられ
る複数対の電極の各一対の電極間方向の分割溝内に、上
記電極近傍で上記分割溝を部分的に小さくした遮断部が
設けられたことを特徴とするセラミック基板。
1. A ceramic substrate in which a plurality of dividing grooves are formed vertically and horizontally in order to obtain a large number of substrates for a chip electronic component, and between a pair of electrodes of a plurality of electrodes provided on the ceramic substrate. A ceramic substrate, characterized in that, in the dividing groove in the direction, a blocking portion is provided in the vicinity of the electrode in which the dividing groove is partially made small.
【請求項2】 チップ電子部品の基板を多数個取りする
ため、複数の分割溝を有したセラミック基板を形成する
セラミック基板の製造装置において、平板上に、上記セ
ラミック基板の表面に分割溝を形成する複数本の突条が
縦横にそれぞれ設けられ、そのセラミック基板に設けら
れる複数対の電極の各一対の電極間方向の分割溝を形成
する上記突条の一部が切り欠かれていることを特徴とす
るセラミック基板の製造装置。
2. A ceramic substrate manufacturing apparatus for forming a ceramic substrate having a plurality of dividing grooves for picking up a large number of substrates for a chip electronic component, wherein the dividing grooves are formed on the surface of the ceramic substrate on a flat plate. A plurality of ridges are provided vertically and horizontally, and a part of the ridges that form the dividing grooves in the direction between each pair of electrodes of the plurality of pairs of electrodes provided on the ceramic substrate is cut out. Characteristic ceramic substrate manufacturing equipment.
JP7322294A 1995-11-15 1995-11-15 Ceramic substrate and its manufacture Pending JPH09139555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7322294A JPH09139555A (en) 1995-11-15 1995-11-15 Ceramic substrate and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7322294A JPH09139555A (en) 1995-11-15 1995-11-15 Ceramic substrate and its manufacture

Publications (1)

Publication Number Publication Date
JPH09139555A true JPH09139555A (en) 1997-05-27

Family

ID=18142028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7322294A Pending JPH09139555A (en) 1995-11-15 1995-11-15 Ceramic substrate and its manufacture

Country Status (1)

Country Link
JP (1) JPH09139555A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165516A (en) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd Method of manufacturing chip type network electronic component
JP2007173867A (en) * 2007-03-20 2007-07-05 Koa Corp Substrate for electronic component, and method for manufacturing electronic component
JP2012227506A (en) * 2011-04-08 2012-11-15 Maruwa Co Ltd Ferrite composite sheet and method of manufacturing the same, and sintered ferrite small piece used for such ferrite composite sheet

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165516A (en) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd Method of manufacturing chip type network electronic component
JP2007173867A (en) * 2007-03-20 2007-07-05 Koa Corp Substrate for electronic component, and method for manufacturing electronic component
JP2012227506A (en) * 2011-04-08 2012-11-15 Maruwa Co Ltd Ferrite composite sheet and method of manufacturing the same, and sintered ferrite small piece used for such ferrite composite sheet
US8323776B2 (en) 2011-04-08 2012-12-04 Maruwa Co., Ltd. Composite ferrite sheet, method of fabricating the composite ferrite sheet, and array of sintered ferrite segments used to form the composite ferrite sheet

Similar Documents

Publication Publication Date Title
JPS6235693A (en) Circuit board
JPH09139555A (en) Ceramic substrate and its manufacture
US4757298A (en) Ceramic substrates for tip electronic parts
JP3167968B2 (en) Manufacturing method of chip resistor
JPH10189305A (en) Angular plate type chip resistor and its manufacture
JP3126131B2 (en) Square plate type chip resistor
JP2006024767A (en) Manufacturing method of chip resistor
JPH0541554Y2 (en)
JP2007220860A (en) Manufacturing method of chip-type electronic part
TWI817476B (en) Chip resistor and method of manufacturing chip resistor
JPH06238643A (en) Flat package and its manufacture
JP2000357604A (en) Aggregative substrate
JPH04213801A (en) Module resistor and manufacture thereof
JPH0528725Y2 (en)
JP2866808B2 (en) Manufacturing method of chip resistor
JPH11224809A (en) Manufacture of square plate type chip resistor
JPH03134974A (en) Manufacture of jumper chip component
JP2694843B2 (en) Method for manufacturing substrate piece in chip variable resistor
JPH043648B2 (en)
JPH0335506A (en) Manufacture of chip r network
JPH043647B2 (en)
JP2631898B2 (en) Manufacturing method of ceramic substrate for electronic components
KR20050011965A (en) Chip resister, method for manufacture thereof and method of manufacture of substrate for chip resister
JPH03242901A (en) Chip type resistor and manufacture thereof
JPH0766885B2 (en) Method for forming electrode coating on small electronic components

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080611

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 12

Free format text: PAYMENT UNTIL: 20110611

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 12

Free format text: PAYMENT UNTIL: 20110611

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120611

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120611

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120611

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 14

Free format text: PAYMENT UNTIL: 20130611

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130611

Year of fee payment: 14

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term