JPH09139176A - Manufacture of field emission type electron emission element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a yield by forming an emitter layer on a conductive substrate by using as a mask a metal thin plate in which an insulating layer and a self-sacrifice layer are formed and after that, eliminating the self-sacrifice layer to lower dimensional accuracy in working an electrode. SOLUTION: A metal thin plate is etched by photolithograpy and the hole 11 of a predetermined pattern is perforated to obtain a lead-out electrode. Next, an insulating layer 12 and a self-sacrifice layer 13 are formed by using as a pattern the hole 11 of the metal thin plate 10. The metal thin plate 10 and a conductive substrate 14 are faced against each other and an emitter layer 16 is deposited from the upper side of the metal thin plate 10 by a sputtering method and after that, the self-sacrifice layer 13 is removed by etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron emission device, and more particularly to a field emission type electron emission device in which an extraction electrode (gate electrode) is made of a thin metal plate and is used as a photomask. The present invention relates to a method of manufacturing an element.

[0002]

2. Description of the Related Art Conventionally, an FED (Field Emission Display) is known as a direct-viewing type self-luminous flat display. As shown in FIG. 1, this FED has a structure in which a cathode electrode 2, an emitter 3 having a sharp tip, and a gate electrode (lead-out electrode) 5 are formed around an emitter via an insulating layer 4 on a cathode substrate 1. And an anode part having a structure in which an anode electrode 7 made of ITO having an R, G, B phosphor layer 7 provided on the surface thereof is formed on the anode substrate 6.

Here, when a strong electric field is applied to the tip of the emitter by applying a grid voltage Vg (positive on the gate electrode side) to the cathode electrode 2 and the gate electrode 5, electrons are emitted from the emitter 3 into a vacuum and are emitted. The electrons are accelerated by the anode voltage Va applied between the cathode electrode 2 and the anode electrode 7 and irradiated on the phosphor layer, and as a result, the phosphor layer emits fluorescence. Note that R, G, and B in the drawing configure one pixel, and a two-dimensionally high-density mounting of this constitutes a flat display.

Next, the manufacturing process of the cathode portion of such an FED will be described with reference to FIG. Figure 2 is Spi
It is a figure which shows the manufacturing process of ndt type FEA (Field Emission Array). First, a Si oxide layer (S
An iO ₂ layer) and an Nb layer are formed (FIG. 2A). Next, after applying a photoresist, pattern exposure is performed, and the resist is developed and washed with water (FIG. 2 (b)).
The SiO ₂ layer is etched, and then the photoresist is removed (FIG. 2C). Then patterned N
A self-sacrificing layer (Al) is deposited on the b layer (see FIG. 2).
(D)). At this time, the self-sacrificing layer is formed in an overhang state so as to reduce the diameter of the patterned hole. Then, when an emitter layer (Mo) is deposited on the entire surface, the diameter of the hole formed by patterning becomes smaller as it is deposited, and finally the hole portion is completely covered, and by that time an emitter with a sharp tip grows. (Fig. 2
(E)). Finally, Al is etched and washed with water to remove the self-sacrificing layer and the Mo layer thereon.

[0005]

However, the conventional FEA manufacturing process described in FIG. 2 has complicated steps and requires high-precision fine processing. For this reason,
There was a problem that the yield was poor. The present invention is intended to solve the above-mentioned problems, and simplifies the steps of the FEA manufacturing process, improves the yield, and uses the extraction electrode itself as a mask to reduce the processing accuracy required during electrode processing. It is an object of the present invention to provide a method of manufacturing a field emission type electron-emitting device that can be manufactured.

[0006]

According to the present invention, a thin metal plate is patterned and punched, and an insulating layer and a self-sacrificing layer are formed using the punched thin metal pattern as a pattern. The thin metal plate on which the sacrificial layer is formed is used as a mask to form the emitter layer on the conductive substrate, and then the self-sacrificing layer is etched and removed. Therefore, the number of manufacturing steps is reduced, and since the extraction electrode is a mask, a mismatch between the extraction electrode and the emitter does not occur.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of the present invention will be described below. FIG. 3 is a diagram for explaining the FEA manufacturing process of the present invention. First, the Fe plate 10 is etched by photolithography to form holes 11 in a predetermined pattern (FIGS. 3A and 3B), which are used as extraction electrodes. Therefore, the processing on the extraction electrode side is completed by the above processing. It is possible to use a conventional manufacturing technique for a photomask, an aperture grill, or the like, to form a hole in the Fe plate in a predetermined pattern. next,
Insulating layer (SiO ₂ ) 12 with Fe plate 10 as a pattern
And a self-sacrificing layer 13 made of an Al layer is formed thereon (FIGS. 3C and 3D). Then, this Fe plate 1
0 and the Si substrate 14 are opposed to each other (FIG. 3 (e)), and a Mo layer is deposited from above the Fe plate 10 by using a sputtering method (FIG. 3 (f)). At this time, as the Mo layer 15 is deposited, the hole diameter of the Fe plate 10 is gradually reduced, and accordingly, the diameter of the Mo layer 16 deposited on Si through the hole is reduced, and finally the hole of the Fe plate 10 is closed. Therefore, the Mo layer 16 on Si has a sharp point. Such a phenomenon occurs when the Fe plate 10 has a small hole diameter. Then, the self-sacrificing layer 13 is etched to remove Mo.
This is completed by removing the layer 16 (FIG. 3 (g)).

Since the extraction electrode patterned in this way is used as a mask when the emitter is formed, it is possible to form the extraction electrode and the mask at the same time, and the number of steps is reduced. In addition, in the above steps, the insulator layer 12 (which functions as protection of Fe when etching the Al layer) existing on the Fe plate 10 is not always necessary. Further, the insulator layer on the Fe plate 10 may remain in the final form (FIG. 3 (g)), but it is not always necessary. Further, the substrate on the emitter side is not limited to the Si substrate and may be made of any material as long as it has electrical conductivity.

In this example, since there is no insulator layer for supporting the extraction electrode, a spacer is separately arranged or a structure for suspending the extraction electrode in the air is provided on the side wall for panelization when a spacer is formed. There is a need.

An insulator layer 17 may be provided between the emitter and the extraction electrode as shown in FIG. in this case,
Before integrating the emitter and extraction electrodes, the insulator layer
It may be formed on the side of the emitter substrate (Si substrate) 14 or on the side of the extraction electrode.

Further, as shown in FIG. 5, an insulator layer 20 may be formed on the side of the extraction electrode, and a converging electrode 21 for converging the electron beam so as not to impinge the electron beam on other pixels.
Also in this case, the insulator layer 17 between the emitter and the extraction electrode may or may not be present.

[0012]

Example 1 A resist agent (ORM85 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was spin-coated on a Fe plate having a film thickness of 100 μm by a spinner, and left in an oven at 80 ° C. for 30 minutes to be dried. After air cooling, a desired pattern is exposed, the resist is developed, washed with water, and left in an oven at 135 ° C. for 30 minutes. After air cooling, Fe is etched with a 3% FeCl ₂ aqueous solution and washed with water. Next, the substrate is left in a resist stripping solution (Clean Stop manufactured by Tokyo Ohka Kogyo Co., Ltd.) kept at 120 ° C. for 5 minutes, and then a strip rinse solution at room temperature
Then, the resist is stripped by immersing it in isopropyl alcohol at room temperature for 1 minute. This substrate is washed with water and then dried. This completes the patterning of Fe. On this substrate, a SiO ₂ layer and an Al layer are deposited with a film thickness of 200 μm and 150 μm, respectively, by a sputtering method. The lead electrode portion is formed as described above.

[0013]

EXAMPLE 2 introduces Si substrate in a chamber maintained at a vacuum, a Si0 ₂ by sputtering method on the surface 400
Deposit to a film thickness of μm. A resist agent (ORM85 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is spin-coated on it by a spinner,
Leave in the oven at 80 ° C. for 30 minutes to dry. After air cooling, a desired pattern is exposed, the resist is developed, washed with water, and left in an oven at 135 ° C. for 30 minutes. After air cooling, the SiO ₂ layer is patterned by reactive ion etching using CHF ₃ +0 ₂ as an etchant. Next, add 5 to the resist stripper (Tokyo Ohka Kogyo Clean Stop) that holds the substrate at 120 ° C.
The resist is peeled off by leaving it for 1 minute and then immersing it in a strip rinse solution at room temperature for 1 minute and then in isopropyl alcohol at room temperature for 1 minute. The spacer is formed as described above.

[0014]

Third Embodiment The extraction electrode portion patterned in the first embodiment is introduced into a vacuum chamber and placed on a heater heated to 350 ° C. The Si substrate prepared in Example 2 was placed on this, and the Si substrate side was used as a cathode to form a space between the Si substrate and the Fe plate.
By applying a voltage of V, electrostatic adhesion is performed and Fe
Was brought into close contact with the Si substrate. Next, sputter method
The o layer is deposited to form the Mo emitter layer. Next, 0.
Al is etched with a 5% caustic soda solution,
The self-sacrificing layer and the Mo layer on it are removed by washing with water. FEA was produced by the above method, and good electron emission characteristics were obtained.

In the case of the Spindt type, the hole diameter on the extraction electrode side is preferably smaller than the hole diameter on the cathode side. Such an example will be described below. First, the Al plate 50 is etched by photolithography to form holes 51 in a predetermined pattern (see FIG. 6A).
(B)), which is used as the extraction electrode. In addition, this hole 5
The diameter of 1 is smaller than the hole diameter on the cathode side. Next, A
An insulating layer (SiO ₂ ) 52 is formed using the l-plate 50 as a pattern, and a self-sacrificing layer 53 made of an Al layer is formed thereon (FIGS. 6C and 6D). Next, a Si substrate 54 is prepared, and an insulator layer (SiO ₂ and Al
A mixed layer of ₂ O ₃ ) 55 and a photoresist layer 56 are formed (FIGS. 6E and 6F), and then the photoresist layer is patterned and then the insulating layer is etched (FIG. 6).
(G), (h)). Then, after the extraction electrode and the emitter are integrated, a Mo layer 57 is deposited to form an emitter 58 (FIGS. 7 (i) and 7 (j)). As can be seen from FIG. 7 (i), the hole diameter of the Al plate 50 is smaller than the hole diameter on the Si substrate side. Then, the self-sacrificing layer 53 is etched to remove the Mo layer 57, and further the insulating layer 52 is removed to complete the process (FIGS. 7 (k) and (l)).

The extraction electrode and the emitter side may be integrated by any method such as an adhesive, electrostatic adhesion, or solid phase fusion, as long as it is a method of joining a metal and an insulator. For example, in FIG.
Shows an example of electrostatic adhesion between a glass substrate as an insulating layer and an Al plate, and such a method may be used. FIG.
In the vacuum chamber 40, the patterned Al plate 30 is placed on the heater 35 heated to 300 to 400 ° C., the glass substrate 33 whose surface has been cleaned is placed on the heater 35, and the glass substrate 33 is used as the cathode and the glass substrate 33. When a voltage of several hundreds of V is applied between the Al plate 30 and the Al plate 30, a chemical bond is generated on the surfaces of both and the two adhere to each other.

[0017]

Example 4 A resist agent (ORM85 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was spin-coated on an Al plate having a film thickness of 100 μm by a spinner, and left in an oven at 80 ° C. for 30 minutes to be dried. After air cooling, expose the desired pattern, develop the resist,
It is washed with water and left in an oven at 135 ° C. for 30 minutes. After air cooling, Al is etched with a 0.5% caustic soda aqueous solution and washed with water. Next, leave the substrate in a resist stripping solution (Clean Stop manufactured by Tokyo Ohka Kogyo Co., Ltd.) kept at 120 ° C. for 5 minutes, then soak it in a strip rinse solution at room temperature for 1 minute and in isopropyl alcohol at room temperature for 1 minute. Then, the resist is stripped. This substrate is washed with water and then dried. This completes the patterning of Fe.

On this substrate, Si0 was sputtered.
₂ and Al layers are deposited at film thicknesses of 200 μm and 150 μm, respectively.

The lead electrode portion is formed as described above.

[0020]

[Embodiment 5] A Si substrate is introduced into a chamber kept in vacuum, and the surface thereof is sputtered with SiO ₂ + Al ₂
O ₃ is deposited to a film thickness of 400 μm. A resist agent (ORM85 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is spin-coated on it with a spinner, left to stand in an oven at 80 ° C. for 30 minutes, and dried. After air cooling, a desired pattern is exposed, the resist is developed, washed with water, and left in an oven at 135 ° C. for 30 minutes. After air cooling, CHF ₃ + O ₂ is etched by hydrofluoric acid and patterned by reactive ion etching. Next, a resist stripping solution holding the substrate at 120 ° C. (Clean Stop manufactured by Tokyo Ohka Kogyo Co., Ltd.)
Then, the resist is stripped by immersing it in a strip rinse solution at room temperature for 1 minute and then in isopropyl alcohol at room temperature for 1 minute. The insulating layer is formed as described above.

[0021]

Sixth Embodiment The extraction electrode portion patterned in the fourth embodiment is introduced into a vacuum chamber and placed on a heater heated to 350 ° C. The Si substrate processed in Example 5 is placed on this, and the Si substrate is used as a cathode to form a cathode with an Fe plate of 400
By applying a voltage of V, electrostatic adhesion is performed and Al
Was brought into close contact with the Si substrate.

Next, a Mo layer is deposited by a sputtering method,
A Mo emitter layer is formed. Next, Al is etched with a 0.5% caustic soda aqueous solution and washed with water to remove the self-sacrifice layer and the Mo layer thereon. By this etching, the hole diameter of the Al plate and the hole diameter of the substrate-side insulating layer are made uniform.
Then, SiO ₂ is etched with hydrofluoric acid.

FEA was produced by the above method, and good electron emission characteristics were obtained.

[0024]

As described above, according to the present invention, the steps of the FEA manufacturing process are simplified, the yield is improved, and the extraction electrode itself is used as a mask, so that the processing precision required at the time of electrode processing is improved. Can be lowered.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an FED.

FIG. 2 is a diagram illustrating a conventional FEA manufacturing process.

FIG. 3 is a diagram illustrating an example of the FEA manufacturing process of the present invention.

FIG. 4 is a diagram in which a lead electrode and an emitter are integrated.

FIG. 5 is a diagram in which focusing electrodes are provided in FIG.

FIG. 6 is a diagram illustrating another example of the FEA manufacturing process of the present invention.

FIG. 7 is a diagram for explaining another example of the FEA manufacturing process of the present invention.

FIG. 8 is a diagram illustrating electrostatic adhesion.

[Explanation of symbols]

10 ... Fe plate, 11 ... Hole, 12 ... Si substrate, 13 ... Al
Layers, 14 ... Si substrate, 15 ... Mo layer, 15 ... Emitter layer, 17 ... Spacer, 20 ... Insulator layer, 21 ... Nb plate.

Claims (2)

[Claims] 1. An emitter and an extraction electrode, comprising: an emitter formed on a cathode electrode; an extraction electrode arranged in the vicinity of the emitter; and an anode electrode arranged to face the cathode electrode and provided with a phosphor on the surface. In the method of manufacturing a field emission electron-emitting device, in which a grid voltage for electron emission is applied between the cathode and the anode, and an anode voltage is applied between the cathode and the anode to cause the field emission of electrons from the emitter, a thin metal plate is patterned. Hole to create an extraction electrode, form an insulating layer and a self-sacrificing layer in the pattern of holes in a thin metal plate, and conduct electricity using the thin metal plate with the insulating layer and the self-sacrificing layer as a mask Emission type, characterized in that it comprises a step of forming an emitter layer on a flexible substrate and a step of etching and removing the self-sacrificial layer. Method of manufacturing electron-emitting device. 2. The method according to claim 1, wherein the hole diameter of the self-sacrificing layer is smaller than the hole diameter of the insulating layer.