JPH07320636A - Manufacture of electron emitting element - Google Patents

Abstract

PURPOSE:To form an insulating layer with high adhesion strength and free of pin holes between an emitter circuit layer and a gate electrode layer of an electric field emission-type electron emitting element. CONSTITUTION:A light transmissive emitter wiring layer 2 is formed on a light transmissive insulating substrate 1 and a light shielding layer 3, an emitter layer 4, and a resist layer 5 are successively formed on the resulting substrate and then patterning of the resist layer 5 is carried out. After the emitter layer 4 and the light shielding layer 3 are successively etched while the resulting resist layer 5 being used as a mask, the resist layer 5 is removed. A light transmissive insulating layer 6, a light transmissive gate electrode layer 7, and a negative-type photoresist layer 8 are successively formed on the surface of the insulating substrate 1 on the emitter layer 3 side. While using the light shielding layer 3 as a photo mask, the negative-type photoresist layer 8 is exposed from the back side of the insulating substrate 1 and after that, unexposed parts 8b are removed and while using the exposed part 8a of the negative-type photoresist layer as a mask, the gate electrode layer 7 and the insulating layer 6 are etched until the emitter layer 4 is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron-emitting device which emits electrons by a strong electric field and a method for manufacturing the same. More specifically, an array-shaped FEA (Field Emitter Arr) that constitutes a flat panel display.
and a method for manufacturing an electron-emitting device which is preferably applicable to ay).

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for a flat-panel display having a high-speed response and a high resolution. As a powerful display structure for that purpose, an array of minute electron-emitting devices in a high-vacuum flat plate cell is used. The ones that have been placed in are promising.

As such a minute electron-emitting device,
A field emission type electron-emitting device utilizing a so-called field emission phenomenon is known. That is, in the field emission type electron-emitting device, when the strength of the electric field applied to the substance is increased, the width of the energy barrier on the surface of the substance is gradually narrowed according to the strength,
When the electric field strength is a strong electric field of 10 ⁷ V / cm or more, the electrons in the substance can break through the energy barrier due to the tunnel effect, so that the phenomenon that electrons are emitted from the substance is used.

A typical electron-emitting device of such field emission type is a cone-type electron-emitting device having a pointed tip as shown in FIG.
1. An emitter wiring layer 32 for applying a voltage to an emitter 36 described later, an insulating layer 33, and a gate electrode layer 34 for concentrating a strong electric field on the emitter 36 are sequentially stacked.
The gate electrode layer 34 and the insulating layer 33 include the emitter wiring layer 3
2 has a structure in which an opening portion 35 reaching 2 is provided, and an emitter 36 is laminated on the emitter wiring layer 32 in the opening portion 35 so as not to contact the insulating layer 33 and the gate electrode layer 34. In this case, in order to concentrate a strong electric field on the tip of the emitter and make it easier to emit electrons from the tip of the emitter, the tip of the emitter is processed into a needle shape having a radius of curvature of several hundreds nm or less.

However, such a cone type electron-emitting device is used in a large area flat display for FEA.
However, there is a problem that it is very difficult to uniformly process the tip of the emitter on the FEA having a large area.

For this reason, as shown in FIG.
It has been proposed that 6 is not a cone type, but a disk type having good uniform workability. In this disc-type electron-emitting device, an electric field is concentrated on the edge portion of the disc-shaped emitter 36, and electrons are emitted from there. In this case, an emitter underlayer 37 is generally formed between the emitter 36 and the emitter wiring layer 32. And, such an emitter underlayer 37 is
It is said that the diameter is preferably smaller than the diameter of the emitter 36 so that the electric field is likely to be concentrated on the edge portion of the disk-shaped emitter 36.
7 is usually formed of a material that is more easily etched than the emitter 36.

By the way, the disk-type electron-emitting device is
Although it has better uniform workability in a wider area than the cone type, the concentration of the electric field is lower than that of the cone type electron-emitting device, so it is necessary to apply a higher voltage during electron emission. .

On the other hand, in order to provide a singular point on the upper surface of the disk-shaped emitter where the electric field is easily concentrated, as shown in the emitter plan views of FIGS. 5A to 5D, the disk-shaped emitter is shown. Is further processed to form a sharp edge. For example, an electron-emitting device having an emitter having the shape shown in FIG. 5A can be obtained by once manufacturing the electron-emitting device shown in FIG. 4 and then repeating the steps. The manufacturing process will be described with reference to FIG.

First, the insulating substrate 61 such as glass is coated with Cr.
A metal film such as is formed and patterned by photolithography or the like to form an emitter wiring layer 62 for applying a voltage to the emitter (FIG. 6A).

Next, the emitter underlayer 6 made of Al or the like is used.
3 is formed. The emitter underlayer 63 is not always necessary, but as described above, in order to concentrate an electric field on the emitter layer, it is preferable that the lower part of the emitter layer is side-etched. An emitter base layer 63 made of a material that is easily formed is formed below the emitter layer.

Further, the emitter layer 64 and the resist layer 6 made of Cr or the like are continuously formed on the emitter base layer 63.
5 are sequentially formed (FIG. 6B). Then, the resist layer 65 is patterned into a disk shape (FIG. 6).
(C)).

Next, the patterned resist layer 65.
With the mask as a mask, the emitter layer 64 and the emitter underlayer 63
And are patterned by etching until the emitter wiring layer 62 is exposed (FIG. 6D).

Next, from the vertical direction of the insulating substrate 61, an insulating layer 66 made of SiO ₂ or the like is formed on the insulating substrate 61 by using an anisotropic vapor deposition method such as a reactive electron beam (REB) vapor deposition method. The gate electrode layer 67 is formed on the entire surface and is continuously formed of Cr or the like (FIG. 6E). In this case, of the insulating layer 66 and the gate electrode layer 67, the portions 66a and 67a formed on the resist layer 65 and the portion laminated around the resist layer 65 are discontinuous. That is, so that there is a gap around the emitter layer 64,
The insulating layer 66 and the gate electrode 67 are formed in a self-aligned manner.

Next, a weak alkaline stripping solution (for example, Microposit 1112A, manufactured by Shipley Co.) is applied to the resist layer 65 to strip the resist layer 65 and the emitter layer 64 at the boundary between the resist layer 65 and the resist layer 65. The insulating layer 66a and the gate electrode layer 67a formed thereon are lifted off and removed, and the disk-shaped emitter layer 64 is formed.
Is exposed and a gate electrode pattern is formed (FIG. 6F). As a result, the electron-emitting device shown in FIG. 4 is obtained.

Next, the disk type emitter layer 64 is formed as shown in FIG.
The following steps are performed in order to process the shape shown in FIG.

First, a resist layer 68 made of a positive type resist or the like is formed on the emitter layer 64 (FIG. 6).
(G)). Then, the resist layer 68 is patterned into a cross shape by photolithography (FIG. 6).
(H)).

Next, the patterned resist layer 68.
With the mask as a mask, the emitter layer 64 and the emitter underlayer 63
And are patterned until they reach the emitter wiring layer 62 (FIG. 6I).

Finally, a weak alkaline stripping solution (for example, Microposit 1112A, manufactured by Shipley Co.) is applied to the resist layer 68 to remove the resist layer 68, so that the emitter having the shape shown in FIG. An electron-emitting device having the same can be obtained (FIG. 6 (j)).

[0019]

By the way, in the case of manufacturing an electron-emitting device as shown in FIG. 6, the method for laminating the insulating layer 66 and the gate electrode layer 67 is as follows.
In order to obtain a device structure in which 7 does not contact the emitter layer 64, an anisotropic film forming method in which the insulating layer 66 and the gate electrode 67 are formed in a self-aligned manner is used. Above all, the formation was limited to the anisotropic vapor deposition method.

However, the film formed by the anisotropic vapor deposition method generally has a problem that the adhesion is not sufficient and that a pinhole is easily generated in the film. Therefore, there is also a problem that a short circuit may occur between the emitter wiring layer and the gate electrode.

The present invention is intended to solve the above-mentioned problems of the prior art, and has high adhesion between the emitter wiring layer and the gate electrode layer of the field emission type electron-emitting device. At the same time, an object is to enable formation of a pinhole-free insulating layer without using an anisotropic vapor deposition method.

[0022]

The present inventor uses a light-transmissive insulating substrate, and provides a light-shielding layer between the emitter layer and the insulating substrate, and uses the light-shielding layer as a photomask. It is possible to pattern these by exposing the negative photoresist layer formed on the gate electrode layer from the back surface of the insulating substrate, patterning, and etching the gate electrode layer and the insulating layer using the pattern as a mask. In this case, it was found that the method for laminating the insulating layer and the gate electrode layer is not limited to the anisotropic vapor deposition method, and any means such as a sputtering method, a CVD method and a spin coating method can be used, and the present invention has been completed. It was

That is, according to the present invention, an insulating substrate, an emitter wiring layer, an insulating layer and a gate electrode layer are sequentially laminated, and an opening portion reaching the emitter wiring layer is provided in the gate electrode layer and the insulating layer. In a method of manufacturing a field emission type electron-emitting device in which a light-shielding layer and an emitter layer are sequentially laminated on an emitter wiring layer in the opening so as not to contact the insulating layer and the gate electrode layer, (a) light transmission A light-transmissive emitter wiring layer on a transparent insulating substrate; (b) sequentially laminating a light-shielding layer, an emitter layer, and a resist layer on the emitter wiring layer; (c) patterning the resist layer Step; (d) Step of sequentially etching the emitter layer and the light-shielding layer using the patterned resist layer as a mask; (e) Step of removing the patterned resist layer; (f) Insulating group A light-transmissive insulating layer, a light-transmissive gate electrode layer, and a negative photoresist layer are sequentially formed on the emitter-layer-side surface of the insulating substrate; The step of exposing the negative photoresist layer from (b) to (h) the step of removing the unexposed portion of the negative photoresist layer; (i) the insulation of the gate electrode layer from the negative photoresist layer of the remaining exposed portion as a mask And a step of: (j) removing the negative photoresist layer used as the mask, and a step of etching the layer until the emitter layer is exposed.

The manufacturing method of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a manufacturing process diagram (FIGS. 1A to 1J) of a preferred embodiment of the method for manufacturing an electron-emitting device of the present invention. The electron-emitting device obtained by this method is shown in FIG.
The structure shown in (j), that is, the insulating substrate 1, the emitter wiring layer 2, the insulating layer 6 and the gate electrode layer 7 are sequentially stacked, and the gate electrode layer 7 and the insulating layer 6 reach the emitter wiring layer 2. A hole A is provided, and the light shielding layer 3 and the emitter layer 4 are provided on the emitter wiring layer 2 in the opening A, and the gate electrode layer 7 is formed.
It has a laminated structure so that it does not come into contact with. The emitter underlayer is not provided in the structure of FIG. 1 (j).

Step (1a) First, a light-transmitting conductive film such as ITO (indium tin oxide) is formed on the insulating substrate 1 by a sputtering method or a vacuum deposition method, and this is formed by a photolithography method or a reactive method. The emitter wiring layer 2 is formed by patterning by an ion etching method (RIE method) or the like (FIG. 1A).

The insulating substrate 1 functions as a support for the electron-emitting device, but the negative photoresist layer 8 described later is used.
In order to be able to expose the substrate from the back surface of the insulating substrate 1, it needs to be light transmissive. As such an insulating substrate 1, a glass substrate having a thickness of about 1 to 5 mm can be preferably used.

The emitter wiring layer 2 is a wiring for applying a voltage to the emitter layer 4, and like the insulating substrate 1 described above, a negative photoresist layer 8 to be described later is provided from the back surface of the insulating substrate 1. It must be light transmissive in order to be exposed. Further, the material of the emitter wiring layer 2 is required to have good adhesion to the insulating substrate 1 and good conductivity. As such a material, I
TO can be preferably exemplified. In the case of ITO, its thickness is preferably about 0.1 to 0.2 μm. Further, as the material of the emitter wiring layer 2, 5
Metal thin film with a thickness of 0 nm or less, preferably Cr, W, Ta
Alternatively, a thin film of Nb can be used.

Step (1b) Next, the light shielding layer 3 and the emitter layer 4 are formed on the emitter wiring layer 2.
Then, the resist layer 5 is sequentially laminated (FIG. 1B).

The light-shielding layer 3 is for exposing a negative photoresist layer 8 to be described later from the back surface of the insulating substrate 1 so that patterning can be performed with high precision. As a material of such a light shielding layer 3, a metal having a high light shielding property can be used, and Cr or the like can be used. Moreover, the thickness can be appropriately determined as necessary.

The emitter layer 4 functions as a member that directly emits electrons from its surface. As a material of such an emitter layer 4, a material having a small work function, good electron emission characteristics, high voltage resistance, and a high melting point is used. Examples of such materials include Cr, W, Mo,
Ta and Nb can be preferably exemplified. The thickness can be appropriately determined as needed.

The resist layer 5 is a layer patterned on an etching mask used when the emitter layer 4 is disk-shaped or etched into a shape as shown in FIG. As such a resist layer 5, so-called positive type or negative type photoresist having high resolution can be used, and a thickness of about 0.3 to 0.8 μm is preferable.

Step (1c) Next, the resist layer 5 is patterned into an etching mask used when the emitter layer 4 is etched into a desired shape (FIG. 1C).

The patterning of the resist layer 5 can be performed by a usual photolithographic method.

Step (1d) Next, the emitter layer 4 and the light-shielding layer 3 are formed using the patterned resist layer 5 as a mask until the emitter wiring layer 2 is exposed (FIG. 1 (d)).

In this case, it is preferable that the cross-sectional shape of the emitter layer 4 in the film thickness direction is inversely tapered. With the inverse taper shape, the electric field strength can be increased at the surface edge of the emitter layer 4. As a method of forming the emitter layer 4 in an inversely tapered shape, it is preferable to use an etching method having a high degree of isotropicity. For example, when the emitter layer 4 is made of Cr, CHCl ₃
It is preferable to apply a reactive ion etching method using a Cl-based gas and oxygen gas. In this case, the Cl-based gas flow rate with respect to the total gas flow rate is 15 to 35 mol% and the gas pressure is 40 Pa to 100 Pa. Alternatively,
A wet etching method using a cerium ammonium nitrate-based etchant can also be applied.

Further, it is preferable not only to perform side etching in the reverse taper shape, but also to perform side etching so that the width x of the emitter layer 4 becomes smaller than the width y of the light shielding layer.
As a result, it is possible to reliably prevent a short circuit between the gate electrode layer 6 and the emitter layer 4, which will be described later.

Step (1e) Next, the resist layer 5 is removed by a conventional method (FIG. 1).
(E)).

Step (1f) Next, the insulating layer 6, the gate electrode layer 7 and the negative photoresist layer 8 are sequentially formed on the surface of the insulating substrate 1 (FIG. 1).
(F)).

The insulating layer 6 is a layer for insulating the gate electrode layer 7 and the emitter wiring layer 2 from each other, and can be formed by any film forming means. For example, it can be formed by an anisotropic vapor deposition method similar to the conventional one, a sputtering method, a CVD method, a spin coating method, a dipping method, or the like. Therefore, it becomes possible to appropriately select a formation method and conditions that can have high adhesion without pinholes, and as a result, the electron-emitting device can be provided with good electrical characteristics and high reliability. Can be granted.

As the insulating layer 6, it is preferable to use a light-transmissive one so that a negative photoresist layer 8 described later can be exposed from the back surface of the glass substrate 1. As such a material, an inorganic insulating material such as SiO ₂ , preferably SiN _x , or an organic polymer insulating material such as a photoresist can be appropriately selected according to the forming method. Although the thickness varies depending on the size and shape of the emitter layer 4, it is preferably about 0.5 to 2 μm.

The gate electrode layer 7 is an electrode for concentrating a strong electric field on the emitter layer 4. The gate electrode layer 7 is formed by the same anisotropic vapor deposition method, sputtering method, CV
It can be formed by the D method or the like.

As the gate electrode layer 7, it is preferable to use a light transmissive one so that a negative photoresist layer 8 described later can be exposed from the back surface of the glass substrate 1. As this material, ITO can be preferably exemplified. In the case of ITO, the thickness is 0.1 to 0.
It is preferably about 2 μm. Further, as the material of the emitter wiring layer 2, a metal thin film having a thickness of 50 nm or less, preferably a thin film of Cr, W, Ta or Nb can be used.

The thickness of the gate electrode layer 7 varies depending on the material used, but is preferably about 0.1 to 0.2 μm.

The negative type photoresist layer 8 functions as an etching mask for patterning the gate electrode layer 7 and the insulating layer 6, and as such, the negative type photoresist layer 8 is located at a higher position than the emitter layer 4 using the light shielding layer 3 as a photomask. It is a layer that is patterned with high precision. This negative photoresist layer 8
Can be formed by a spin coating method, a dipping method, or the like. As such a negative photoresist, known negative photoresists such as polyimide negative photoresists, Si-containing polymer negative photoresists such as Si-containing polystyrene negative photoresists and polysiloxane negative photoresists are used. The photoresist can be appropriately selected and used.

Step (1g) Next, using the light shielding layer 3 as a mask, the negative photoresist layer 8 is exposed from the back surface of the insulating substrate 1 to cure the exposed portion 8a (FIG. 3 (g)).

The direction of exposing the negative type photoresist layer 8 can be from either the front surface side or the back surface side of the insulating substrate 1. However, when performing from the front surface, the resist for patterning is used. Need to be further provided,
The process becomes complicated. In addition, the negative photoresist layer 8
It is also difficult to perform patterning on the emitter layer 4 with high positional accuracy. On the other hand, when exposure is performed from the back surface, patterning can be easily performed with high positional accuracy using the light shielding layer 3 as a mask.

Step (1h) Next, the unexposed portion 8b of the negative photoresist layer 8 is removed by a conventional method, and a mask (light-shielding layer 3) for etching the gate electrode layer 7 and the insulating layer 6 is patterned. (FIG. 1 (h)).

Step (1i) Next, the gate electrode layer 7 is etched, and further the insulating layer 6 is etched until the emitter layer 4 is exposed (FIG. 1).
(I)). The method of etching the gate electrode layer 7 differs depending on the types of materials of the gate electrode layer 7 and the insulating layer 6. For example, the gate electrode layer 7 is ITO and the insulating layer 6 is SiN.
_{If x} , the gate electrode layer 7 is removed by wet etching with a hydrochloric acid-based etching solution, and the insulating layer 6 is removed by RIE.
Thus, dry etching can be performed with a fluorine-based gas (CF ₄ or the like).

At the end of step (1j) , the remaining negative type photoresist layer 8 is removed by a conventional method to obtain the electron-emitting device shown in FIG. 1 (j).

FIG. 2 shows a method of manufacturing an electron-emitting device according to the present invention, in which an emitter underlayer 9 having a diameter smaller than that of the emitter layer 4 is formed between the light shielding layer 3 and the emitter layer 4. It is a process drawing. With such a configuration, the electric field can be more concentrated on the circular peripheral portion of the disc-shaped emitter layer 4, and the electron emission characteristics from the emitter layer 4 can be further improved.

Step (2a) First, similarly to the step (1a) in FIG. 1, a light-transmissive conductive film such as ITO is formed on the insulating substrate 1 by a sputtering method or a vacuum deposition method, and this is photolithographically processed. Method or a reactive ion etching method (RIE method) to perform patterning to form the emitter wiring layer 2 (FIG. 2A).

Step (2b) Next, the light shielding layer 3, the emitter underlayer 9, the emitter layer 4 and the resist layer 5 are sequentially laminated on the emitter wiring layer 2 (FIG. 2B). The emitter base layer 9 can be formed by a conventional anisotropic vapor deposition method, a sputtering method, a CVD method, or the like, and a material that is more easily side-etched than the material of the emitter layer 4 is used. Preferably. For example, when the emitter layer 4 is made of W, the emitter underlayer 9 is preferably made of Cr, and when the emitter layer 4 is made of Cr, the emitter underlayer 9 is preferably made of Al.

Step (2c) Next, as in the step (1c) of FIG.
Patterning is performed on the etching mask used when the emitter layer 4 is etched into a desired shape (see FIG. 2).
(C)).

Step (2d) Next, using the patterned resist layer 5 as a mask, the emitter layer 4, the emitter underlayer 9, and the light shielding layer 3 are etched until the emitter wiring layer 2 is exposed (FIG. 2).
(D)). At this time, the amount of side etching of the emitter base layer 9 is made larger than that of the emitter layer 4. For example, when the emitter underlayer 9 is made of Al,
By using a Cl-based gas such as CHCl ₃ and reactive ion etching at a gas pressure that increases the side etch amount, for example, about 40 Pa, or by wet etching using a phosphoric acid, nitric acid, or acetic acid-based etchant. The emitter base layer 9 can be etched into a desired shape. As a result, the diameter of the emitter underlayer 9 can be made smaller than the diameter of the emitter layer 4, and the emitter layer 4
The electron emission efficiency from the can be improved.

In this step, similarly to the step (1d) shown in FIG. 1, it is preferable that the emitter layer 4 be etched so that its cross-sectional shape in the film thickness direction becomes an inverse taper shape. Further, it is preferable to perform side etching so that the width x of the emitter layer 4 becomes smaller than the width of the light shielding layer.

Step (2e) Next, the resist layer 5 is removed by a conventional method (FIG. 2).
(E)).

Step (2f) Next, the insulating layer 6, the gate electrode layer 7, and the negative photoresist layer 8 are sequentially formed on the surface of the insulating substrate 1 (FIG. 2).
(F)).

Step (2g) Next, using the light shielding layer 3 as a mask, the negative photoresist layer 8 is exposed from the back surface of the insulating substrate 1 to cure the exposed portion 8a (FIG. 2 (g)).

Step (2h) Next, the unexposed portion 8b of the negative photoresist layer 8 is removed by a conventional method, and patterning is performed on a mask for etching the gate electrode layer 7 and the insulating layer 6 (FIG. 2).
(H)).

Step (2i) Next, the gate electrode layer 7 is etched, and further the insulating layer 6 is etched until the emitter layer 4 is exposed (FIG. 2).
(I)). The method of etching the gate electrode layer 7 can be appropriately determined according to the types of materials of the gate electrode layer 7 and the insulating layer 6, and the like.

At the end of step (2j) , the remaining negative type photoresist layer 8 is removed by a conventional method to obtain the electron-emitting device shown in FIG. 2 (j).

Although FIG. 1 and FIG. 2 show an example in which the emitter layer 4 has a disc shape, FIG.
With the shape as shown in (d), the electric field can be further concentrated on the surface of the emitter layer 4.

The electron-emitting device manufactured as described above is an FE of a flat display that utilizes the field emission phenomenon.
It is useful as A.

[0065]

In the present invention, a light-transmitting material is used as the insulating substrate, the emitter wiring layer, the insulating layer, and the gate electrode layer, and the light-shielding layer is provided between the emitter layer and the emitter wiring layer to form the insulating layer. After forming the gate electrode layer, the negative photoresist layer formed on the gate electrode layer is exposed from the side of the insulating substrate using the light shielding layer as a mask to pattern the emitter layer with high positional accuracy. Then, the insulating layer and the gate electrode layer are patterned using the resist pattern as a mask. Therefore, it is not necessary to pattern the insulating film by the lift-off method, and the insulating layer and the gate electrode layer can be formed by any film forming method other than the anisotropic vapor deposition method. Therefore, it is possible to select a film forming method and film forming conditions that can obtain a layer having high adhesion and a pinhole-free property. As a result, it becomes possible to provide the electron-emitting device with excellent electric characteristics and high reliability.

[0066]

EXAMPLES The method for manufacturing the electron-emitting device of the present invention having the embodiment shown in FIG. 2 will be described in detail below with reference to examples.

Example Process (a) First, an ITO layer having a thickness of 200 nm was formed as a first emitter on a transparent glass substrate (AN, manufactured by Asahi Glass Co., Ltd.) having a thickness of 1.1 mm as an insulating substrate by a sputtering method. It was formed as a wiring layer. A resist layer patterned by the photolithography method was formed on this ITO layer, and the ITO layer was etched using this resist layer as a mask and an etchant containing hydrochloric acid as a main component. After that, the emitter wiring layer was formed by peeling and removing the resist layer.

Step (b) Next, C of 100 nm is formed as a light shielding layer by a sputtering method.
An r layer is formed and an emitter underlayer of 700n is formed on the r layer.
An m-thick Mo layer was formed, and a 200 nm-thick W film as an emitter layer was continuously formed thereon. Further, a positive photoresist (S1400, manufactured by Shipley Co., Ltd.) was applied on the emitter layer by spin coating to a thickness of 1.4 μm to form a resist layer.

Step (c) Next, the resist layer was patterned into a disk-shaped emitter shape by photolithography.

Step (d) Using the patterned resist layer as a mask, the W layer as an emitter layer is first dry-etched by RIE using SF ₆ gas (condition: gas flow rate 25 sccm).
/ Gas pressure 70 mTorr / RF power 240 W).
Then, the Mo layer as the emitter underlayer was dry-etched by the RIE method under the same conditions as the etching of the W layer. Then, the Cr layer as the light-shielding layer is replaced with CHCl ₃ and O.
Dry etching (conditions: gas pressure 50 Pa / RF power 150 W) was performed by the RIE method using a mixed system gas with ₂ (flow rate ratio 3: 7). This dry etching was performed until the emitter wiring layer was reached.

After the dry etching, in order to increase the side etching amount of the Mo layer, wet etching was performed using an etchant containing phosphoric acid, nitric acid and acetic acid (liquid temperature 20 ° C./hour 15 seconds).

Step (e) After the completion of wet etching, the resist layer was removed by ashing with oxygen gas.

Step (f) Next, a 1 μm thick SiN _x film as an insulating layer is formed on the side surface of the emitter wiring layer of the glass substrate by parallel plate plasma CVD.
(Conditions: substrate temperature 300 ° C./RF power 180 W / Si
H ₄ 5sccm + NH ₃ 30sccm + H ₂ 23scc
The film was formed at m / gas pressure of 1 Torr). Subsequently, an ITO film having a thickness of about 200 nm was formed as a gate electrode layer by a sputtering method and annealed at 250 ° C. for 30 minutes.
On this gate electrode layer, a polyimide negative photoresist (Photo Nice UR3100, manufactured by Toray Industries, Inc.) was applied by spin coating to a thickness of about 1 μm, and then prebaked.

Step (g) Next, the entire back surface of the glass substrate was exposed by using a canona liner using a mercury lamp as a light source to cure the polyimide negative photoresist. At this time, the resist on the light shielding layer was not exposed and was not cured.

Step (h) Next, the unexposed portion of the polyimide negative photoresist was removed by a solvent-based stripping solution to pattern an etching mask for forming a disc-shaped emitter layer.

Step (i) Next, the negative photoresist is removed and the exposed I
The TO film is removed by wet etching with a hydrochloric acid-based etchant solution, and then SiN _x in the insulating layer is removed by RIE using CF ₄ gas (conditions: gas flow rate 20 sccm / gas pressure 30).
The gate electrode layer and the insulating layer were patterned by performing dry etching removal with mTorr / RF power of 300 W).

Step (j) Finally, the remaining negative photoresist was removed by an alkaline stripping solution to obtain an electron-emitting device shown in FIG.

[0078]

According to the present invention, after forming the insulating layer and the gate electrode layer, the negative photoresist layer formed on the gate electrode layer is positioned at a higher position than the emitter layer by using the light shielding layer as a mask. It can be patterned with high precision. Further, the insulating layer and the gate electrode layer can be patterned using the resist pattern as a mask. Therefore, it is not necessary to pattern the insulating layer by the lift-off method, and the insulating layer can be formed by any film forming method other than the anisotropic vapor deposition method. Therefore, it is possible to select a film forming method and film forming conditions that can obtain a high adhesion and a pinhole-free insulating layer. As a result, it becomes possible to provide the electron-emitting device with excellent electric characteristics and high reliability.

[Brief description of drawings]

FIG. 1 is a manufacturing process drawing of an electron-emitting device of the present invention.

FIG. 2 is a manufacturing process diagram of an electron-emitting device of the present invention.

FIG. 3 is a sectional view of a conventional electron-emitting device.

FIG. 4 is a sectional view of a conventional electron-emitting device.

FIG. 5 is a plan view of an emitter.

FIG. 6 is a manufacturing process diagram of a conventional electron-emitting device.

[Explanation of symbols]

 1 Insulating Substrate 2 Emitter Wiring Layer 3 Light-Shielding Layer 4 Emitter Layer 5 Resist Layer 6 Insulating Layer 7 Gate Electrode Layer 8 Negative Photoresist Layer 9 Emitter Underlayer

Claims (4)

[Claims] 1. An insulating substrate, an emitter wiring layer, an insulating layer, and a gate electrode layer are sequentially stacked, and an opening portion reaching the emitter wiring layer is provided in the gate electrode layer and the insulating layer, and inside the opening portion. In the method for manufacturing a field emission type electron-emitting device, in which a light-shielding layer and an emitter layer are sequentially stacked on the emitter wiring layer so as not to contact the insulating layer and the gate electrode layer, (a) a light-transmissive insulating property A step of forming a light-transmitting emitter wiring layer on the substrate; (b) a step of sequentially laminating a light shielding layer, an emitter layer, and a resist layer on the emitter wiring layer; (c) a step of patterning the resist layer; (d) ) Step of sequentially etching the emitter layer and the light-shielding layer using the patterned resist layer as a mask; (e) Step of removing the patterned resist layer; (f) The emitter layer side of the insulating substrate Step of sequentially forming a light-transmissive insulating layer, a light-transmissive gate electrode layer, and a negative photoresist layer on the front surface; Exposing the resist layer; (h) removing the unexposed portion of the negative photoresist layer; (i) using the remaining negative exposed photoresist layer as a mask, the gate electrode layer and the insulating layer, A manufacturing method comprising: a step of etching until the emitter layer is exposed; and (j) a step of removing the negative photoresist layer used as a mask. 2. A glass substrate is used as a light-transmissive insulating substrate, and an ITO layer or a metal thin film having a thickness of 50 nm or less is used as a light-transmissive emitter wiring layer and a gate electrode layer.
The manufacturing method according to claim 1, wherein SiN _x is used as the light-transmissive insulating layer. 3. A metal thin film having a thickness of 50 nm or less is Cr, W,
The manufacturing method according to claim 1, which is a thin film of Ta or Nb. 4. The emitter underlayer is further provided between the light shielding layer and the emitter layer in the step (b), and the emitter underlayer is also sequentially etched after the etching of the emitter layer in the step (d). The manufacturing method according to any one of to 3.