JPH09138671A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device provided with a sampling circuit surely sampling at all synchronizing signal timing. SOLUTION: A clock circuit 3 generates plural sampling signals 3A, 3B, 3C different from each other in phase from a horizontal synchronizing signal 1B to sample a vertical synchronizing signal 1C. Thus, the circuit 3 judges the timing between the vertical synchronizing signal 1C and the horizontal synchronizing signal 1B, and a synchronizing circuit 4 selects the sampling signal 4A not executing sampling in the data change period of the vertical synchronizing signal 1C, and the synchronizing circuit 4 samples the vertical synchronizing signal 1C to display the image data 1A on a liquid crystal panel 6 through a drive circuit 5 based on a dot clock 2A generated from a phase locked loop circuit 2 and the horizontal synchronizing signal 1B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a clock circuit for sampling a vertical synchronizing signal.

[0002]

2. Description of the Related Art A conventional liquid crystal display device, as shown in FIG.
The synchronizing circuit 104 for sampling the vertical synchronizing signal 1C with the horizontal synchronizing signal 1B is necessary, but the relationship between the input timings of the vertical synchronizing signal 1C and the horizontal synchronizing signal 1B is not constant, so that the sampling signal 104A is the vertical synchronizing signal 1C.
When it was close to the change period of, the setup time and hold time required for sampling could not be satisfied.

[0003]

In this conventional liquid crystal display device, the image data 1A sent from the host system 1 is used.
If the sampling signal 104A of 1 does not satisfy the setup time and the hold time, accurate sampling cannot be performed because there is no means for dealing with it, and the drive circuit is based on the dot clock 2A generated by the phase locked loop circuit 2. It was not possible to accurately display the image data 1A on the liquid crystal panel 6 via 5.

Therefore, an object of the present invention is to provide a liquid crystal display device for displaying image data by accurately sampling all input timings of a vertical synchronizing signal and a horizontal synchronizing signal.

[0005]

In order to solve the above-mentioned problems, a liquid crystal display device of the present invention comprises a liquid crystal panel for displaying image data output based on a horizontal synchronizing signal and a vertical synchronizing signal, and the above horizontal A phase locked loop circuit that generates a dot clock that is synchronized with a synchronization signal, a clock circuit that generates a plurality of sampling signals with different phases that sample the vertical synchronization signal from the horizontal synchronization signal, and a plurality of clock circuits that are generated by this clock circuit. From the sampling signal of the vertical synchronizing signal, the synchronizing circuit for selecting the sampling signal according to the setup time and the hold time, and based on the sampling signal and the horizontal synchronizing signal selected by the synchronizing circuit, the image data by the dot clock. To control to display on the above LCD panel. Characterized in that it consists of a circuit.

In order to solve the above-mentioned problems, the liquid crystal display device of the present invention is characterized in that it is constituted by the clock circuit for generating the sampling signal by a shift register.

Further, in order to solve the above-mentioned problems, the liquid crystal display device of the present invention is characterized by being constituted by the clock circuit for generating the sampling signal by a counter.

[0008]

Next, a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram (A) of a liquid crystal display device and a block diagram (B) of a clock circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of the reference clock and the shift register of the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is a time chart (A), (B), of a synchronizing circuit of a liquid crystal display device according to an embodiment of the present invention.
(C).

In the liquid crystal display device according to the embodiment of the present invention, as shown in FIG. 1A, an image output based on the horizontal synchronizing signal 1B and the vertical synchronizing signal 1C output from the host system 1 is displayed. Liquid crystal panel 6 for displaying data 1A and dot clock 2A synchronized with horizontal synchronizing signal 1B
, A clock circuit 3 for generating a plurality of sampling signals 3A, 3B, 3C having different phases for sampling the vertical synchronizing signal 1C from the horizontal synchronizing signal 1B, and a clock circuit 3 A synchronizing circuit 4 for selecting the sampling signals 3A, 3B, 3C according to the setup time and hold time of the vertical synchronizing signal 1C from the plurality of sampling signals 3A, 3B, 3C, and the sampling signal 4A and horizontal signal selected by the synchronizing circuit 4. The drive circuit 5 controls to display the image data 1A on the liquid crystal panel 6 by the dot clock 2A based on the synchronization signal 1B.

As shown in FIG. 1B, the clock circuit 3 includes a clock generation circuit 31 for sampling the vertical synchronization signal 1C from the horizontal synchronization signal 1B and generating the sampling signal 3A from the reference clock 32. A shift register 331 for generating a sampling signal 3B having a different phase from the sampling signal 3A generated by the clock generating circuit 31, and a shift register 331 for generating a sampling signal 3C having a different phase from the sampling signal 3B generated by the shift register 331. And 332.

Next, the operation of the liquid crystal display device according to one embodiment of the present invention will be described with reference to the drawings.

The operation of the liquid crystal display device according to one embodiment of the present invention is, as shown in FIG. 1, phase locked with the dot clock 2A synchronized with the horizontal sync signal 1B by the horizontal sync signal 1B output from the host system 1. The clock circuit 3 generates the negative polarity sampling signal 3A generated by the droop circuit 2 and generated by the clock generating circuit 31 using the reference clock 32 and the horizontal synchronizing signal 1B.

Further, in the shift register 331, as shown in FIG. 2, the negative polarity sampling signal 3A generated by the reference clock 32 is shifted by the reference clock 32, so that the negative polarity sampling signal 3A becomes the reference. A negative sampling signal 3B whose phase is shifted by one clock of the clock 32 is generated, and the negative sampling signal 3B is similarly shifted in the shift register 332 by the reference clock 32. A negative sampling signal 3C having a phase difference of one clock of the reference clock 32 with respect to 3B is generated.

Therefore, the reference clock 32, the clock generation circuit 31, the shift register 331, and the shift register 33.
Sampling signals 3A, 3 of different phases generated in 2
B and 3C are selected by the synchronizing circuit 4, the vertical synchronizing signal 1C is sampled at the rising edge of the selected sampling signal 4A selected by the synchronizing circuit 4, and the dot clock 2A and horizontal synchronizing generated by the phase locked loop circuit 2 are performed. The image data 1A is displayed on the liquid crystal panel 6 via the drive circuit 5 based on the signal 1B.

Further, as shown in FIG. 2, the operation of the synchronizing circuit of the liquid crystal display device according to the embodiment of the present invention is performed by sampling the sampling data when the vertical synchronizing signal 1C is sampled by the sampling signals 3A, 3B and 3C. SD1, respectively
If SD2 and SD3 are set, firstly, as shown in FIG. 3A, the sampling data SD1, the sampling data SD2, and the sampling data SD3 are the same when the data change point of the vertical synchronizing signal 1C rises and falls. When the value is “0”, there is no rising or falling edge that is a data change point of the vertical synchronizing signal 1C from the rising edge of the sampling signal 3A to the rising edge of the sampling signal 3C, and all the sampling signals 3A, 3B, and 3C. Even if the signal is sampled, sampling is not performed at the data change point of the vertical synchronizing signal 1C.

Second, as shown in FIG. 3B, the sampling data SD1 and the sampling data SD2 have the same value at the rising and falling edges of the data change point of the vertical synchronizing signal 1C and the sampling data SD2.
And the sampling data SD3 have different values, if the data change point of the vertical synchronizing signal 1C is between the rising edges of the sampling signal 3B and the sampling signal 3C, the sampling data SD2 and sampling data SD3 are the data changes of the vertical synchronizing signal 3B. The data is indeterminate because it may have been sampled at a point, that is, the data is “1”
Or the sampling signal 3B
Since the sampling signal 3C cannot be used as the selected sampling signal 4A of the vertical synchronizing signal 1C, only the sampling signal 3A is used as the selected sampling signal 4A of the vertical synchronizing signal 1C.

Thirdly, as shown in FIG. 3C, the sampling data SD1 and the sampling data SD2 have different values at the rising and falling edges of the data change point of the vertical synchronizing signal 1C, and the sampling data SD2 is different. S
When the change point of the vertical synchronizing signal 1C is between the rising edge of the sampling signal 3A and the rising edge of the sampling signal 3B when D2 and the sampling data SD3 have the same value, the sampling data SD1 and the sampling data S
Since D2 may have been sampled at the data change point of the vertical synchronizing signal 3B, the sampling data SD1
Since the sampling data SD2 and the sampling data SD2 may be indefinite, the sampling signal 3A and the sampling signal 3B cannot be used as the selected sampling signal 4A of the vertical synchronization signal 1C, so only the sampling signal 3C is the vertical synchronization signal 1C. Selection sampling signal 4A
Can be used as

Therefore, normally, the sampling signal 3C is used as the selected sampling signal 4A of the vertical synchronizing signal 1C input to the drive circuit 5, and the relationship between the input timings of the vertical synchronizing signal 1C and the horizontal synchronizing signal 1B is every cycle. In consideration of the same, if the sampling signal 3C cannot be used as the selected sampling signal 4A even once, the selected sampling signal 4A input to the drive circuit 5 is changed from the sampling signal 3C to the sampling signal 3A.
By changing the setting to, the vertical synchronization signal 1 that satisfies the setup and hold times at all input timings of the vertical synchronization signal 1C and the horizontal synchronization signal 1B in the synchronization circuit 4 is changed.
C sampling is possible.

In the clock circuit 3 of the liquid crystal display device according to the embodiment of the present invention, the shift register 331,
However, the counter may generate the sampling signals 3A, 3B, and 3C.

[0023]

As described above, in the image display device according to the present invention, before sampling the vertical synchronizing signal,
The clock circuit that checks the position of the data change point of the vertical sync signal in advance using sampling clocks with different phases and determines the sampling clock ensures reliable vertical sync regardless of the input timing of all vertical sync signals and horizontal sync signals. It has the effect of sampling the signal.

[Brief description of the drawings]

FIG. 1 is a block diagram (A) of a liquid crystal display device and a block diagram (B) of a clock circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of a reference clock and a shift register of the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is time charts (A), (B) and (C) of the synchronizing circuit of the liquid crystal display device according to the embodiment of the present invention.

FIG. 4 is a block diagram of a conventional liquid crystal display device.

[Explanation of symbols]

 1 liquid crystal display device (host system) 2 phase locked loop circuit 3 clock circuit 4 synchronizing circuit 5 driving circuit 6 liquid crystal panel 1A image data 1B horizontal synchronizing signal 1C vertical synchronizing signal 2A dot clock 3A, 3B, 3C sampling signal 4A synchronizing circuit ( Selection sampling signal) 31 Clock generation circuit 32 Reference clock 331, 332 Shift register

Claims (3)

[Claims] 1. A liquid crystal panel for displaying image data output based on a horizontal synchronizing signal and a vertical synchronizing signal, a phase locked loop circuit for generating a dot clock synchronized with the horizontal synchronizing signal, and the horizontal synchronizing signal. A clock circuit that generates a plurality of sampling signals with different phases for sampling the vertical synchronizing signal, and a plurality of sampling signals generated by the clock circuit, and the sampling signal is selected according to the setup time and hold time of the vertical synchronizing signal. A synchronous circuit
A liquid crystal display device comprising: a drive circuit that controls the image data to be displayed on the liquid crystal panel by the dot clock based on the sampling signal selected by the synchronization circuit and the horizontal synchronization signal. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device comprises the clock circuit for generating the sampling signal by a shift register. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device comprises the clock circuit for generating the sampling signal by a counter.