JPH09134986A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH09134986A JPH09134986A JP29252095A JP29252095A JPH09134986A JP H09134986 A JPH09134986 A JP H09134986A JP 29252095 A JP29252095 A JP 29252095A JP 29252095 A JP29252095 A JP 29252095A JP H09134986 A JPH09134986 A JP H09134986A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- fin
- group
- groups
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体装置等の
電子部品に使用されるリードフレームに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for electronic parts such as semiconductor devices.
【０００２】[0002]
【従来の技術】従来、図５に示すような電力用トランジ
スタ等の大電力用半導体装置に用いられる樹脂封止型リ
ードフレーム４０は、銅板をプレス加工して形成されて
いる。図において、４１は整列した半導体素子搭載部と
なるフィン群、４２は各フィン４１からそれぞれ３本ず
つ導出したリード群、４３はリード群４２を接続する共
通接続部である。そして、このリードフレーム４０を用
い、半導体素子４５の搭載、ワイヤボンド４６、樹脂封
止４７、および素子分割４８等の加工を行い、半導体装
置を得る。2. Description of the Related Art Conventionally, a resin-sealed lead frame 40 used in a high power semiconductor device such as a power transistor as shown in FIG. 5 is formed by pressing a copper plate. In the figure, 41 is a group of fins to be aligned semiconductor element mounting parts, 42 is a lead group derived from each of the fins 41, and 43 is a common connection part for connecting the lead groups 42. Then, using this lead frame 40, the mounting of the semiconductor element 45, the wire bond 46, the resin sealing 47, the element division 48, and the like are processed to obtain a semiconductor device.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来のリード
フレーム４０によると、銅板のリード群４２を形成する
部分は、大半がプレス加工で切り取られ、大きな材料ロ
スが発生する。また、１列にフィン群４１を整列したも
のであって、生産性の向上は望めない。さらに、フィン
群４１，リード群４２，共通接続部４３を分割，分離す
る工程においても、リード群４２の先端と共通接続部４
３の接合断面が広く、よってカット時にプレス金型に無
理な力が加わり、金型の寿命が短くなる。以上の結果、
リードフレーム４０の製造コストが高くなるという課題
があった。However, according to the conventional lead frame 40, most of the portion forming the lead group 42 of the copper plate is cut off by press working, resulting in a large material loss. Further, since the fin groups 41 are arranged in one row, it is not possible to expect improvement in productivity. Further, even in the step of dividing and separating the fin group 41, the lead group 42, and the common connecting section 43, the tips of the lead group 42 and the common connecting section 4 are separated.
The joining cross section of No. 3 is wide, so that an excessive force is applied to the press die at the time of cutting and the life of the die is shortened. As a result of the above,
There is a problem that the manufacturing cost of the lead frame 40 increases.
【０００４】この発明は、材料の有効利用ならびに生産
性の向上が図れ、また分割時のストレスを軽減でき、低
コスト化が図れるリードフレームを提供することを目的
とする。An object of the present invention is to provide a lead frame which can effectively utilize materials and improve productivity, can reduce stress at the time of division, and can reduce cost.
【０００５】[0005]
【課題を解決するための手段】請求項１記載のリードフ
レームは、整列した第１のフィン群と、この第１のフィ
ン群に対し間隔をあけて平行に整列した第２のフィン群
と、第１および第２のフィン群の間において各フィン群
に沿って配置した第１および第２の共通接続部と、第１
のフィン群側から第１の共通接続部を介して延出され先
端が第２の共通接続部に達した第１のリード群と、第２
のフィン群側から第２の共通接続部を介して延出され先
端が第１の共通接続部に達した第２のリード群とを備え
たものである。According to a first aspect of the present invention, there is provided a lead frame having a first group of fins aligned with each other, and a second group of fins arranged in parallel with the first group of fins at a distance. First and second common connecting portions arranged along the respective fin groups between the first and second fin groups;
A first lead group extending from the fin group side through the first common connecting portion and having a tip reaching the second common connecting portion;
A second lead group extending from the fin group side through the second common connecting portion and having a tip reaching the first common connecting portion.
【０００６】請求項１記載のリードフレームによると、
第１および第２のフィン群を互いに間隔をあけて平行に
整列させ、各フィンからリード群を導出させたので、１
枚のリードフレームから大量の素子を得ることができ、
生産性が向上する。請求項２記載のリードフレームは、
請求項１において、第１および第２のリード群の各リー
ドは交互に配置され、各リードの先端が幅狭となってい
るものである。According to the lead frame of claim 1,
Since the first and second fin groups are aligned in parallel with each other with a space between them, the lead group is derived from each fin.
A large number of elements can be obtained from a single lead frame,
Productivity is improved. The lead frame according to claim 2,
In claim 1, the leads of the first and second lead groups are alternately arranged, and the tips of the leads are narrow.
【０００７】請求項２記載のリードフレームによると、
第１および第２のフィン群から導出した第１および第２
のリード群の各リードを交互に配置したので、隣接する
リードの間隔が密になり、材料のロスが少なくなる。ま
た、各リード先端を幅狭としたので、第１および第２の
リード群の先端と第２および第１の共通接続部との接合
断面が小さくなり、カット時に無理な力がプレス金型に
加わらず、金型の寿命が延びる。According to the lead frame of claim 2,
First and second derived from first and second fin groups
Since the leads of the lead group are alternately arranged, the intervals between the adjacent leads are narrowed and the loss of material is reduced. Further, since the tips of the leads are made narrower, the joining cross section between the tips of the first and second lead groups and the second and first common connection portions becomes smaller, and an excessive force is applied to the press die during cutting. Without adding, the life of the mold is extended.
【０００８】請求項３記載のリードフレームは、請求項
１または２において、第１および第２のフィン群の相対
するフィンが各フィン群の整列方向にずれているもので
ある。請求項４記載のリードフレームは、請求項３にお
いて、各フィン群の相対するフィンのずれ幅が第１およ
び第２のリード群の各リードのピッチに略等しいもので
ある。According to a third aspect of the present invention, in the lead frame according to the first or second aspect, the opposing fins of the first and second fin groups are displaced in the alignment direction of the fin groups. A lead frame according to a fourth aspect of the present invention is the lead frame according to the third aspect, in which the displacement width of the fins facing each other in the fin group is substantially equal to the pitch of the leads in the first and second lead groups.
【０００９】請求項３または４記載のリードフレームに
よると、第１および第２のリード群を交互に配置するこ
とが可能となり、隣接するリード間隔が密になり、材料
ロスを少なくすることができる。請求項５記載のリード
フレームは、請求項４において、リードの導出側近傍が
リード先端より幅広であり、かつリード先端に対しセン
タ位置をずらして配置したものである。According to the lead frame of the third or fourth aspect, it is possible to alternately arrange the first and second lead groups, the adjacent lead intervals become close, and the material loss can be reduced. . A lead frame according to a fifth aspect of the present invention is the lead frame according to the fourth aspect, wherein the vicinity of the lead-out side of the lead is wider than the tip of the lead, and the center position is displaced from the tip of the lead.
【００１０】請求項５記載のリードフレームによると、
リード先端が幅狭となり、カット時に無理な力がプレス
金型に加わらず、またリードの導出側が幅広となり、ダ
イスボンド，ワイヤボンド，封止工程等においてフィン
部を確実に支えることができ、フィン部の変形を防ぐこ
とができる。さらに、センタ位置をずらすことで、リー
ド間隔が広がり、リード間の絶縁耐圧を大きくすること
ができる。According to the lead frame of claim 5,
The tip of the lead becomes narrower, unreasonable force is not applied to the press die at the time of cutting, and the lead-out side becomes wider, so that the fin portion can be reliably supported during die bonding, wire bonding, sealing process, etc. The deformation of the part can be prevented. Furthermore, by displacing the center position, the lead interval is widened, and the withstand voltage between the leads can be increased.
【００１１】[0011]
【発明の実施の形態】この発明の一実施の形態について
図１ないし図３を参照しながら説明する。図１におい
て、１０はリードフレームであり、半導体素子搭載部と
なる第１および第２のフィン群１１，１２と、これら第
１および第２のフィン群１１，１２の間において各フィ
ン群１１，１２に沿って配置した第１および第２の共通
接続部１３，１４と、第１のフィン群１１から導出した
第１のリード群１５ならびに第２のフィン群１２から導
出した第２のリード群１６とからなり、プレス金型を用
いて銅材を加工して形成されている。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, reference numeral 10 denotes a lead frame, which is a first and second fin group 11 and 12 which is a semiconductor element mounting portion, and each fin group 11 and 12 between the first and second fin group 11 and 12. First and second common connecting portions 13 and 14 arranged along the first and second fin groups 11, and second lead groups 15 and 12 derived from the first fin group 11 and the second fin group 12, respectively. 16 and is formed by processing a copper material using a press die.
【００１２】第１のフィン群１１と第２のフィン群１２
は、互いに間隔をあけて平行に整列されており、相対す
るフィン１１，１２のセンタをフィン群の整列方向にず
らしてある。当該ずれ幅Ａは、第１および第２のリード
群１５，１６の各リードのピッチに略等しい１．３ｍｍ
である。また、第１および第２の共通接続部１３，１４
間には、隣接するフィン１１，１１（１２，１２）間に
て補強部１７が掛け渡してある。First fin group 11 and second fin group 12
Are aligned parallel to each other with a space therebetween, and the centers of the opposing fins 11 and 12 are displaced in the alignment direction of the fin group. The deviation width A is 1.3 mm which is approximately equal to the pitch of the leads of the first and second lead groups 15 and 16.
It is. In addition, the first and second common connection portions 13 and 14
A reinforcing portion 17 is provided between the adjacent fins 11, 11 (12, 12).
【００１３】また、各フィンから導出される第１および
第２のリード群１５，１６は、それぞれ３本のリードか
らなり、交互に配設されている。第１のリード群１５
は、第１のフィン群１１側から第１の共通接続部１３を
介して延出され、先端が第２の共通接続部１４に達して
いる。また、第２のリード群１６は、第２のフィン群１
２側から第２の共通接続部１４を介して延出され、先端
が第１の共通接続部１３に達している。なお、各リード
の先端１５ａ，１６ａは、幅狭となっており、第１およ
び第２の共通接続部１３，１４に接続されている。さら
に、各リード１５，１６の導出側近傍がリード先端より
幅広であり、かつリード先端に対してセンタ位置をずら
して配置してある（図３中、リード１５′，１６′参
照）。The first and second lead groups 15 and 16 led out from the respective fins are each composed of three leads and are arranged alternately. First lead group 15
Extends from the first fin group 11 side through the first common connecting portion 13, and the tip thereof reaches the second common connecting portion 14. Further, the second lead group 16 is the second fin group 1
It is extended from the second side through the second common connecting portion 14, and the tip thereof reaches the first common connecting portion 13. The tips 15a and 16a of the leads are narrow and are connected to the first and second common connecting portions 13 and 14. Further, the vicinity of the lead-out side of each of the leads 15 and 16 is wider than the tip of the lead, and the centers of the leads 15 and 16 are displaced from each other (see leads 15 'and 16' in FIG. 3).
【００１４】つぎに、リードフレーム１０を用いた大電
力用半導体装置の組立について、図２を用いて説明す
る。まず、図２（ａ）に示すように、相対ならびに隣接
する各フィン１１，１２に、半導体素子２０を半田（Ｐ
ｂ：Ｓｎ＝９７：３）２１を用いて連続して接着する。
つぎに、図２（ｂ）に示すように、相対ならびに隣接す
る各半導体素子２０をアルミ細線（直径２００μｍ）２
２を用いてリード１５，１６に超音波ボンド方式にて連
続してボンドする。なお、相対する半導体素子２０の接
着およびアルミ細線２２の超音波ボンドは、各々相対す
る設備を増設することにより、隣接する部分のインデッ
クスは従来と同等であり、相対する部分も同等のインデ
ックスで生産することができ、生産性が２倍となる。Next, assembly of a high power semiconductor device using the lead frame 10 will be described with reference to FIG. First, as shown in FIG. 2A, the semiconductor element 20 is soldered (P
b: Sn = 97: 3) 21 and continuously adhere.
Next, as shown in FIG. 2B, the semiconductor elements 20 adjacent to each other and the adjacent semiconductor elements 20 are connected to each other by an aluminum thin wire (diameter 200 μm) 2
2 is used to continuously bond the leads 15 and 16 by an ultrasonic bonding method. For the bonding of the semiconductor elements 20 facing each other and the ultrasonic bonding of the aluminum thin wires 22, the index of the adjacent portion is the same as that of the conventional one by adding the equipment facing each other. And productivity is doubled.
【００１５】図２（ｃ）に示すように、半導体素子２０
を外部環境から保護するためエポキシ樹脂２３にて封止
する。その後、図２（ｄ）に示すように、相対ならびに
隣接するフィン１１，１２を接続していたリードフレー
ム１０の不要な部分である共通接続部１３，１４ならび
に補強部１７を切断分割する。その後、リード１５，１
６に半田（Ｐｂ：Ｓｎ＝６３：３７）を接着すること
で、外部装置に取り付け易くして大電力用半導体装置を
得る。As shown in FIG. 2C, the semiconductor device 20
Is sealed with an epoxy resin 23 to protect it from the external environment. After that, as shown in FIG. 2D, the common connection portions 13 and 14 and the reinforcement portion 17, which are unnecessary portions of the lead frame 10 connecting the relative and adjacent fins 11 and 12, are cut and divided. Then leads 15,1
Bonding solder (Pb: Sn = 63: 37) to 6 facilitates attachment to an external device to obtain a high-power semiconductor device.
【００１６】なお、図３に、半導体素子２０，アルミ細
線２２，エポキシ樹脂２３，リードフレーム１０の切断
箇所２４を示す。このように構成されたリードフレーム
１０によると、第１および第２のフィン群１１，１２か
ら導出された第１および第２のリード群１５，１６を交
互に配置したので、隣接するリード１５，１６の間隔が
密になり、銅板を加工して各リード１５，１６を形成す
る際、切り取られる部分が少なく、材料のロスが低減
し、材料の有効利用が図れ、材料費を２５％削減でき
る。Incidentally, FIG. 3 shows the semiconductor element 20, the thin aluminum wire 22, the epoxy resin 23, and the cut portion 24 of the lead frame 10. According to the lead frame 10 configured as described above, the first and second lead groups 15 and 16 derived from the first and second fin groups 11 and 12 are alternately arranged, so that the adjacent leads 15 and The intervals of 16 become close, and when the copper plate is processed to form the leads 15 and 16, there are few parts to be cut off, material loss is reduced, effective use of material can be achieved, and material cost can be reduced by 25%. .
【００１７】また、第１および第２のフィン群１１，１
２を２列に平行に整列させたので、１枚のリードフレー
ム１０から大量の素子を得ることができ、生産性が向上
し、ダイスボンド〜封止までの生産工数を５０％削減で
きる。また、各リード１５，１６の先端１５ａ，１６ａ
を幅狭として共通接続部１３，１４に接続したので、リ
ード１５，１６と共通接続部１３，１４の接合断面が小
さくなり、カット時に無理な力がプレス金型に加わら
ず、金型の寿命が延び、製造コストを低減できる。Further, the first and second fin groups 11, 1
Since 2s are arranged in parallel in two rows, a large amount of elements can be obtained from one lead frame 10, the productivity is improved, and the production man-hours from die bonding to sealing can be reduced by 50%. In addition, the tips 15a and 16a of the leads 15 and 16, respectively.
Is connected to the common connection parts 13 and 14 with a narrow width, the joint cross section of the leads 15 and 16 and the common connection parts 13 and 14 becomes small, and unreasonable force is not applied to the press mold during cutting, and the life of the mold is reduced. And the manufacturing cost can be reduced.
【００１８】また、センタをずらして第１および第２の
フィン群１１，１２を配置することで、第１および第２
のリード群１５，１６を交互に配置でき、隣接するリー
ド１５，１６の間隔が密になり、材料ロスを低減でき
る。さらに、リード１５′，１６′のように、導出側近
傍をリード先端より幅広としたことで、リードフレーム
１０の切断時の負荷を軽減でき金型の寿命が延び、また
ダイスボンド，ワイヤボンド，封止工程等においてフィ
ン部を確実に支えることができ、フィン部の変形を防ぐ
ことができる。さらに、リード先端に対してセンタ位置
をずらして配置したことで、リード間隔が広がり、リー
ド間の絶縁耐圧を大きくすることができる。Further, by arranging the first and second fin groups 11 and 12 with the center shifted, the first and second fin groups are arranged.
The lead groups 15 and 16 can be alternately arranged, and the intervals between the adjacent leads 15 and 16 can be narrowed to reduce material loss. Further, as in the leads 15 'and 16', by making the vicinity of the lead-out side wider than the lead tips, the load at the time of cutting the lead frame 10 can be reduced, the life of the die can be extended, and the die bond, wire bond, The fin portion can be reliably supported in the sealing step and the like, and deformation of the fin portion can be prevented. Further, by arranging the center position with respect to the tips of the leads, the lead interval can be widened and the withstand voltage between the leads can be increased.
【００１９】なお、半導体素子２０とフィン１１，１２
との接合は、半田２１の他、金，銀ペースト等の接合材
を使用してもよい。また、半導体素子２０とリード１
５，１６の接続は、アルミ細線２２の他、金，銅等の導
電性細線を使用してもよい。また、相対するフィン１
１，１２のずれ寸法Ａは、１．３ｍｍに限るものではな
く、第１および第２のリード群１５，１６を交互に配置
できる寸法であればよい。The semiconductor element 20 and the fins 11 and 12
In addition to the solder 21, a joining material such as gold or silver paste may be used for the joining with. In addition, the semiconductor element 20 and the lead 1
For the connection of 5 and 16, in addition to the aluminum thin wire 22, a conductive thin wire such as gold or copper may be used. Also, the opposing fin 1
The displacement dimension A of 1 and 12 is not limited to 1.3 mm, but may be any dimension that allows the first and second lead groups 15 and 16 to be alternately arranged.
【００２０】さらに、前記実施の形態では、大電力用の
リードフレーム（例えば、大電力用ＴＯー２２０タイプ
／一般的に使用されているパッケージ）１０について示
したが、半導体素子を搭載するフインと外部機器と接続
するためのリードを有する樹脂封止型リードフレームす
べてにおいて、本発明の構成を適用できる。この発明の
他の実施の形態を図４に示す。Further, in the above-described embodiment, the lead frame 10 for high power (for example, TO-220 type for high power / package generally used) 10 is shown. The configuration of the present invention can be applied to all resin-sealed lead frames having leads for connecting to external devices. Another embodiment of the present invention is shown in FIG.
【００２１】図４において、３０はリードフレームであ
り、３１，３２は２列に平行に整列した第１および第２
のフィン群、３３，３４は第１および第２のフィン群３
１，３２に沿って配置した第１および第２の共通接続
部、３５，３６は第１および第２のフィン群３１，３２
から導出した第１および第２のリード群である。第１お
よび第２の共通接続部３３，３４間には補強部３７が掛
け渡してある。第１のリード群３５は、第１のフィン群
３１から第１の共通接続部３３を介して延出され、先端
が第２の共通接続部３４に達し、第２のリード群３６
は、第２のフィン群３２から第２の共通接続部３４を介
して延出され、先端が第１の共通接続部３３に達してい
る。In FIG. 4, 30 is a lead frame, and 31 and 32 are first and second rows arranged in parallel in two rows.
Fin groups 33, 34 are first and second fin groups 3
1, 32 are first and second common connecting portions, and 35 and 36 are first and second fin groups 31 and 32.
3 is a first lead group and a second lead group derived from FIG. A reinforcing portion 37 is bridged between the first and second common connecting portions 33 and 34. The first lead group 35 extends from the first fin group 31 via the first common connecting portion 33, the tip thereof reaches the second common connecting portion 34, and the second lead group 36.
Extends from the second fin group 32 via the second common connecting portion 34, and the tip thereof reaches the first common connecting portion 33.
【００２２】各フィン３１，３２に半導体素子（図示せ
ず）を接着し、各半導体素子をリード３５，３６に細線
（図示せず）にて接続する。さらに、半導体素子を封止
し、共通接続部３３，３４ならびに補強部３７を切断分
割して、大電力用半導体装置を得る。このように構成さ
れたリードフレーム３０においても、材料の有効利用、
生産性の向上が図れる。A semiconductor element (not shown) is adhered to each of the fins 31 and 32, and each semiconductor element is connected to leads 35 and 36 by a thin wire (not shown). Further, the semiconductor element is sealed and the common connection portions 33, 34 and the reinforcing portion 37 are cut and divided to obtain a high power semiconductor device. Also in the lead frame 30 configured as described above, effective use of materials,
Productivity can be improved.
【００２３】[0023]
【発明の効果】請求項１記載のリードフレームによる
と、第１および第２のフィン群を互いに間隔をあけて平
行に整列させ、各フィンからリード群を導出させたの
で、１枚のリードフレームから大量の素子を得ることが
でき、生産性が向上し、低コスト化が図れる。According to the lead frame of the first aspect of the present invention, the first and second fin groups are aligned in parallel with each other with a space therebetween, and the lead groups are led out from the respective fins. Therefore, a large amount of elements can be obtained, productivity is improved, and cost can be reduced.
【００２４】請求項２記載のリードフレームによると、
第１および第２のフィン群から導出した第１および第２
のリード群の各リードを交互に配置したので、隣接する
リードの間隔が密になり、材料のロスが少なくなる。ま
た、各リード先端を幅狭としたので、第１および第２の
リード群の先端と第２および第１の共通接続部との接合
断面が小さくなり、カット時に無理な力がプレス金型に
加わらず、金型の寿命が延び、生産コストを低減するこ
とができる。According to the lead frame of claim 2,
First and second derived from first and second fin groups
Since the leads of the lead group are alternately arranged, the intervals between the adjacent leads are narrowed and the loss of material is reduced. Further, since the tips of the leads are made narrower, the joining cross section between the tips of the first and second lead groups and the second and first common connection portions becomes smaller, and an excessive force is applied to the press die during cutting. In addition, the life of the mold can be extended and the production cost can be reduced.
【００２５】請求項３または４記載のリードフレームに
よると、第１および第２のリード群を交互に配置するこ
とが可能となり、隣接するリード間隔が密になり、材料
ロスを少なくすることができる。請求項５記載のリード
フレームによると、リード先端が幅狭となり、カット時
に無理な力がプレス金型に加わらず、またリードの導出
側が幅広となり、ダイスボンド，ワイヤボンド，封止工
程等においてフィン部を確実に支えることができ、フィ
ン部の変形を防ぐことができる。さらに、センタ位置を
ずらすことで、リード間隔が広がり、リード間の絶縁耐
圧を大きくすることができる。According to the lead frame of the third or fourth aspect, it is possible to alternately arrange the first and second lead groups, the adjacent lead intervals become close, and the material loss can be reduced. . According to the lead frame of claim 5, the tip of the lead becomes narrower, unreasonable force is not applied to the press die at the time of cutting, and the lead-out side of the lead becomes wider, and the fins are used in the die bonding, wire bonding, sealing step, etc. The part can be reliably supported, and the fin part can be prevented from being deformed. Furthermore, by displacing the center position, the lead interval is widened, and the withstand voltage between the leads can be increased.
【図１】この発明の一実施の形態のリードフレームの平
面図である。FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention.
【図２】この発明の一実施の形態のリードフレームを用
いた半導体装置の組立工程図である。FIG. 2 is an assembly process diagram of a semiconductor device using a lead frame according to an embodiment of the present invention.
【図３】この発明の一実施の形態のリードフレームの拡
大平面図である。FIG. 3 is an enlarged plan view of the lead frame according to the embodiment of the present invention.
【図４】この発明の他の実施の形態のリードフレームの
平面図である。FIG. 4 is a plan view of a lead frame according to another embodiment of the present invention.
【図５】従来例のリードフレームの平面図である。FIG. 5 is a plan view of a conventional lead frame.
１０，３０ リードフレーム １１，３１ 第１のフィン群 １２，３２ 第２のフィン群 １３，３３ 第１の共通接続部 １４，３４ 第２の共通接続部 １５，３５ 第１のリード群 １６，３６ 第２のリード群 10, 30 Lead frame 11, 31 First fin group 12, 32 Second fin group 13, 33 First common connection portion 14, 34 Second common connection portion 15, 35 First lead group 16, 36 Second lead group
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 勇 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isamu Kobayashi 1-1 Sachimachi Takatsuki City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.
Claims (5)
フィン群に対し間隔をあけて平行に整列した第２のフィ
ン群と、前記第１および第２のフィン群の間において各
フィン群に沿って配置した第１および第２の共通接続部
と、前記第１のフィン群側から前記第１の共通接続部を
介して延出され先端が前記第２の共通接続部に達した第
１のリード群と、前記第２のフィン群側から前記第２の
共通接続部を介して延出され先端が前記第１の共通接続
部に達した第２のリード群とを備えたリードフレーム。1. A first group of fins aligned with each other, a second group of fins aligned in parallel with the first group of fins at intervals, and each of the first and second groups of fins. First and second common connecting parts arranged along the fin group, and a tip extending from the first fin group side through the first common connecting part so that the tip reaches the second common connecting part. And a second lead group extending from the second fin group side through the second common connecting portion and having a tip reaching the first common connecting portion. Lead frame.
交互に配置され、各リードの先端が幅狭となっている請
求項１記載のリードフレーム。2. The lead frame according to claim 1, wherein the leads of the first and second lead groups are alternately arranged, and the tips of the leads have a narrow width.
ィンが各フィン群の整列方向にずれている請求項１また
は２記載のリードフレーム。3. The lead frame according to claim 1, wherein the opposing fins of the first and second fin groups are displaced in the alignment direction of each fin group.
第１および第２のリード群の各リードのピッチに略等し
い請求項３記載のリードフレーム。4. The lead frame according to claim 3, wherein the offset width of the fins facing each other in the fin groups is substantially equal to the pitch of the leads in the first and second lead groups.
広であり、かつリード先端に対しセンタ位置をずらして
配置した請求項４記載のリードフレーム。5. The lead frame according to claim 4, wherein the vicinity of the lead-out side of the lead is wider than the tip of the lead, and the center position is offset from the tip of the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29252095A JPH09134986A (en) | 1995-11-10 | 1995-11-10 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29252095A JPH09134986A (en) | 1995-11-10 | 1995-11-10 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09134986A true JPH09134986A (en) | 1997-05-20 |
Family
ID=17782877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29252095A Pending JPH09134986A (en) | 1995-11-10 | 1995-11-10 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09134986A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763962B1 (en) * | 2001-07-03 | 2007-10-05 | 삼성테크윈 주식회사 | Manufacturing method of one-way lead frame |
| JP2012235011A (en) * | 2011-05-06 | 2012-11-29 | Shindengen Electric Mfg Co Ltd | Metallic mold, device manufacturing apparatus and device manufacturing method |
-
1995
- 1995-11-10 JP JP29252095A patent/JPH09134986A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763962B1 (en) * | 2001-07-03 | 2007-10-05 | 삼성테크윈 주식회사 | Manufacturing method of one-way lead frame |
| JP2012235011A (en) * | 2011-05-06 | 2012-11-29 | Shindengen Electric Mfg Co Ltd | Metallic mold, device manufacturing apparatus and device manufacturing method |
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