JPH09127198A - Improved-type tester-timing architecture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up a test period by providing a test system with a normal mode and an acceleration mode and giving a proper signal with respect to a signal band. SOLUTION: In a normal mode, a global address GA01 and a global higher address bit GA01-MSB are supplied to event sequence start memories ESSM01 350 and ESSM23352. In the case of a signal AM=0, the same global address GA01 is supplied to both the memories ESSN01 and ESSM23. On the other hand, in the case of an acceleration mode AM=1, a start address generated by the memory ESSM23 is selected by the memory EGA23 and respectively different addresses are given, and a two-times test period can be started in a given time range in which start is made possible in the case of AM-0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic test device for testing a circuit, and more particularly to an automatic test device for testing an integrated circuit. One such system is US Pat. No. 5,212,443, inventor WESTet a.
l. , "Event sequencer for automatic test equipment (Eve
nt Sequencer For Automati
c Test Equipment) ", which is incorporated herein by reference.

[0002]

2. Description of the Prior Art In this type of system, the device under test or device under test ("DUT" or simply "device")
At each given time, at most one of the following state changes can occur.

Drive to high state Drive to low state Drive to off state Start test for high state Start test for low state Start test for Z state (high impedance state) Normally end function in this type of system A memory is provided for storing target data (also called a test vector). Therefore, the state change can be expressed directly by the state as done above, or indirectly by referring to the functional data provided by the functional data memory. Is. For example, if n bits of functional data are provided, the event type area can include the following event types:

Drive to D0 0 Drive to D1 1 DFn Drive to nth bit of functional data DFn_ Drive to complement of nth bit of functional data DZ drive turn off Test to T0 0 T1 1 Test for TFn Test for nth bit of functional data TFn_ Test for complement of nth bit of functional data TZ Test for high impedance X Wind strobe Turn off NOP No operation (dummy event) One “event” is state − A pair of times, indicating that a transition to a particular state should be made at a particular time. For example, as shown in FIG. 2A, a non-return-to-zero (NRZ) or no return to zero format can be specified by programming one event as follows.

DF1 @ 1 ns This is 1 nanosecond (1n) after the start of the test period indicated by the test period boundary marker TZ16.
Instructing the hardware to drive the pin to the current first bit of functional data at time s),
(Time zero) is for the test period in which the event is run. FIG. 2A shows two events DF1 @ 1 ns in two consecutive event sequences with consecutive period boundary markers TZ16 as shown, in the first event F1 is 1 and therefore signal 17 at the pin. Goes high and 2
In the second event, F1 is 0, so signal 17 at the pin goes low.

In order to accommodate the ever increasing speed of integrated circuit devices, automated test equipment for testing the devices must increase operating speed.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is a frequency that can solve the above-mentioned drawbacks of the prior art and start a test period for an automatic test apparatus. It is an object of the present invention to provide a test system and method for increasing

[0008]

SUMMARY OF THE INVENTION In general, in one aspect, the invention features a test system for testing a circuit. The test system has operating modes including a normal mode and an acceleration mode.
The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memory provides a sequence memory address for addressing the sequence memory, and the sequence memory provides an event sequence in response to the sequence memory address. When the test system is operating in normal mode, the start memory is electronically coupled (switched) to provide a single sequence memory address for both sequence memories, and When the test system is operating in accelerated mode, the start memory is a second sequence memory in which the first start memory supplies the first sequence memory address to the first sequence memory and the second start memory is independent. Electronically coupled to provide the address to the second sequence memory.
In an embodiment of the invention, the first and second start memories are of the same size, the first and second sequence memories are of the same size, and the words generated by the sequence memory (responsive to the sequence memory address Is wide enough to hold at least two events.

In general, in another aspect, the invention has a basic test period and each basic test when operated in either normal mode or acceleration mode. It is characterized by providing a test system for supplying some sequence memory address to both the first and second sequence memories for a period of time.

In general, in another aspect, the invention features a functional data memory that provides a test vector, the memory being, in normal mode, a complete test sequence for all event sequences. Supplying a vector and, in accelerated mode, supplying a first partial test vector from the first sequence memory to the event sequence and a second partial test vector from the second sequence memory to the event sequence. In one embodiment, the functional data memory provides a complete test vector of functional data of at least 2 bits and a partial test vector of functional data of at least 1 bit. In another embodiment, the functional data memory provides a complete test vector of functional data of at least 4 bits and a partial test vector of functional data of at least 2 bits.

In general, in another aspect, the invention features:
It features a test system having first, second, third and fourth start memories and first, second, third and fourth sequence memories. When the test system is operating in normal mode, these start memories are electronically coupled to provide a single sequence memory address to all four sequence memories to accelerate the test system. When operating in mode, these start memories are such that the first two start memories supply the first sequence memory address to the first two sequence memories and the next two start memories the next two. When the test system is electronically coupled to provide independent second sequence memory addresses to two sequence memories and the test system is operating in dual acceleration mode, these start memories are Electronically coupled to provide a sequence memory address to a corresponding one of the memories.

The advantages of the present invention are as follows. The present invention is useful at apparent speeds (ie, the number of event sequences or test vectors that can be initiated in a unit time) without increasing the operating speed of the components or the amount of local memory required. Cost-effective manner of providing a large increase.
The present invention provides dynamic compatibility with previous architectures without reducing the user's flexibility in programming events and test vectors into event sequences.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1A, an automated test system for testing integrated electronic circuits is also provided as a global section 100 and as a local section which is normally provided for all pins of the device under test. It has a known per-pin (ie, per-pin) section 101. The global section 100 has a global address counter (AC) 111, which provides global address signals that address a global sequence control memory (GSCM) 121 and a per-pin functional data memory (FDM) 131. The global section 100 further includes a test period boundary marker signal time zero (TD) 16 (that is, for marking a test period boundary on the drive side of the device under test (DUT)).
It is also a global time zero clock signal).
It further includes a test period boundary marker signal STZ (not shown) for marking a period on the strobe (test) side of the device under test (DUT), and a global basic clock signal 14 and a global period vernier offset (PV). ) 18 (both shown in FIG. 3) are also given. On the other hand, it is possible to give a global period vernier address instead of the period vernier offset (PV) 18, in which case the local section 101
Has a period vernier storage (not shown) that provides a period vernier value according to the global period vernier address.

Global sequence control memory (GSC
M) 121 supplies the global sequence address 120 to each local section 101 for each test period in response to the global address signal from the address counter (AC) 111. Address counter (AC)
Responsive to 111 in parallel, local functional data memory (FDM) 131 further provides one or more bits of functional data for each test period.

As will be recalled, an event is a state-time pair that represents a transition for a given state occurring at a given time. Referring to FIG. 2A, a non-return-to-zero (NRZ) or no return to zero format can be specified by programming an event as follows.

DF1 @ 1 ns This is the test period boundary marker time zero (T) which is the time zero for the test period in which the event is executed.
Z) Instructs the hardware to drive the pin to the current first bit of functional data at the start of the test period indicated by 16 at the time of 1 nanosecond (1 ns) after the start. FIG. 2A shows two events DF1 in two consecutive event sequences with consecutive period boundary markers (TZ) 16 as shown.
@ 1 ns, in the first event F1 is 1 and thus signal 17 goes high, in the second event F1 is 0 and thus signal 17 goes low. Transition.

As shown in FIG. 2B, the Complementary Surrounding (SBC) format can be specified by programming the following event sequence.

DF1_ @ 2 ns DF1 @ 11 ns DF1_ @ 22 ns In FIG. 2B, the signal 17 has a value of F1 of 0 (low state).
The above sequence occurs when

As shown in FIG. 2C, the clock pin signal 17 can be generated without any functional data by programming the following event sequence.

D1 @ 0 ns D0 @ 4 ns D1 @ 8 ns D0 @ 12 ns FIG. 2D shows a more complex program, which
The DUT pin is driven with a Complemented Surround (SBC) waveform, then the driver is turned off and the output is first strobed to tristate, then to 1, then 1 bit that may differ from the drive data. I / O when strobed to the functional data of
5 illustrates the generation of a waveform for a cycle. This is specified by the following event sequence.

DF1_ @ 2 ns Driving 1st bit functional data complement DF1 @ 9 ns Driving 1st bit functional data DF1_ @ 18 ns Driving 1st bit functional data complement DZ @ 22 ns Turning off driving TZ @ 24 ns Tri-state test X @ 26 ns Wind strobe turn off T1 @ 32 ns 1 test X @ 34 ns Wind strobe turn off TF2 @ 40 ns Second bit functional data test X @ 42 ns Wind strobe test Turn-off In FIG. 2D, F1 is 0 (low state) and the strobe region is indicated by the shaded box. Although FIG. 2D shows both possible values for F2, there is only one value for any sequence of events.

It will be appreciated that in these examples, the functional data memory (FDM) 131 delivers at least 2 bits of functional data for each test period (ie, each event sequence). The functional data memory (FDM) 131 can be implemented to have a width of 1 bit, 2 bits, 4 bits, or any other number of bits. However, it is desirable that the number of bits is an even number for the reasons described below. Furthermore, the test system can be operated in a mode in which the bits of functional data are used as mask bits rather than as state data. In this mode, the mask bit may represent, for example, whether a test of the test event in the event sequence (eg, TZ or T1) should be performed. Otherwise, they are treated as NOPs by the system.

The system is capable of implementing test periods that are not integral multiples of the basic clock period. For convenience of explanation, in this specification, as shown in FIG.
Using a clock cycle of 3.2 ns and a test period of 10 ns (the preferred time may be shorter, ie if the basic clock cycle is 2.5 ns and the test period is 5 ns, however, , The values given above are for convenience of explanation, and the values chosen do not affect the principles of the invention).

If a test period of 10 ns is developed from the basic clock signal (CLK) 14 having a period of 3.2 ns, then 3 basic clock cycles are 9.
It can be seen that it gives one period of 6 ns, while four basic clock cycles give one period of 12.8 ns. The time zero signal time zero (TZ) 16 at time 50 represents the start of the test period. The second time zero signal time zero (TZ) 16 is generated at time 52, which corresponds to the rising edge of clock signal 14 at 9.6 ns. To realize the 10ns test period,
A digital value representing 0.4 ns is given as the period vernier offset 18. Therefore, this offset represents part of the basic clock cycle 14. As will be described later, the system uses this value to actually start the next test period at time 54.
, Which is 50 to 10 ns.

Similarly, the next time zero signal time zero (T
Z) 16 is generated at time 56 and has a vernier offset 18 of 0.8 ns at time 58 for 10 ns.
Need to generate a period. This process continues until the offset value is 2.8 to generate the test period starting at time 60. Then, on the next time period, there are four clock pulses between the time zero signal time zero (TZ) 16 at time 62 and the next at time 64. At this point, no offset value is applied. Because the start of the test period is aligned with the rising edge of the basic clock pulse.

Thus, the test period of any period (greater than the basic clock period) can be programmed simply by varying the step size by which the period vernier offset 18 is incremented (however, for example: Other considerations such as pipelined memory bandwidth may limit the range of test periods that can be selected).

Referring again to FIG. 1A, at the beginning of each test period, local event sequence start memory (ESSM) 122 provides local event sequence start address 124. The event sequence start address 124 is attached to the local event sequence store (ESS) 140 to select the event sequence to be attached to the local device pin, ie the pin associated with the local section 101.
In practice, a pipelined structure (not shown) is used to pass signals between the functional blocks shown in order to achieve high data rates.

One event sequence start address 124 selects an event of one word from ESS 140. The preferred number of events per word is four, but it is possible to use any range of numbers, mainly due to cost constraints. Events in ESS 140 carry the following information: event time, event type, address increment bit (used to flag the last event in the event sequence). When the event sequence start address 124 is given, a sequence consisting of a plurality of events is selected (that is, the start address 12
4 stored in ESS 140), starting from the first event in the selected word and continuing through the last event in the sequence to the next event in the word (or ESS1
The event in the next word at 40), the last event in the sequence is the one where the increment bit is clear. Therefore, an ESS 140 with 64 words of 4 events each is a sequence of up to 256 events, or
Or 6 consisting of up to 4 events per sequence
It is possible to store four sequences. ESS
The events in the word are passed to the time and event decoder 142 for processing, where one event per decoder is passed.

Event times are represented as integers and fractions of the base clock 14 cycle. If the fraction is 8 bits wide, it can represent a time resolution of 1/256 of the base clock period. In the time and event decoder 142, the event time is added to the period vernier offset 18 to generate the cycle count + vernier time for the event. The number of time and event decoders 142 is preferably ESS 140.
Matches the number of events in one of the words.

Time and Event Decoder (TED) 14
2 further processes the event type and transforms it into a "marker type" that defines a complete state transition from the old state to the new state. For example, the event type is D
If F1, the first bit of the current functional data (ie, the current test vector) is "1", and the previous state of the pin driver is low, then the marker type is low To high state (abbreviation “D 1
<Represented by "-0"). Time and event decoder 1 when converting event type to marker type
42 is the functional data for that test period (that is,
(May be mask data) and the previous state programmed for the pin. The process of loading the events in the event sequence into ESS 140 ensures that they are in chronological order, so the previous state is derived from the previous effective event (NOP or reduce to it). Events are not effective in changing the state of pins). The time and event decoder 142 further includes a NOP (no action) event, an event resulting in a NOP event (eg, an event that drives the pin to its previous state),
And take other events to be skipped (eg, the events in the ESS word following the event flagged as the last event in the sequence) and remove them from the stream of events to process.

The following marker types result from the decoding of the event types listed above.

D 1 <−0 Drive from low state to high state D 1 <−Z Drive from drive off to high state D 0 <−1 Drive from high state to low state D 0 <−Z Drive off to low state Drive to DZ 0 Drive from low state to inhibit state DZ 1 Drive from high state to inhibit state T0 Test for low state (previous state to test is always drive to inhibit state) T1 Test for high state TZ Tristate test X <-T0 Termination Test for Low State X <-T1 Termination Test for High State X <-TZ Termination Test for Tri-State Referring to FIG.
Each of them had their marker type and cycle count + vernier time windmilled.
Barrel (B) via multiplexer (WMUX) 150
ARREL) circuit (BC) 200 is passed. The windmill multiplexer (WMUX) 150 is a barrel circuit (BC) in a round robin manner without considering word boundaries in the event sequence storage 140.
Assign the decoded event to 200. This is accomplished with two counters. One counter steps through the event in the current word of ESS 140, skips the NOP event and restarts from the beginning if a new word appears. The other counter is squeezed around the barrel circuit (BC) 200 so that the barrel circuit (BC) 200
Count the modulo of the number of. In this way, the windmill multiplexer (WMUX) 150 connects the time and event decoder 142 with the next actual event in the time sequence to the least recently used barrel circuit (BC) 200.

Referring to FIG. 4, each barrel circuit 200 performs a final time calibration to cycle count + vernier time (TM) 304 received via marker type (MRK) 302 and windmill multiplexer (WMUX) 150. To do. Each barrel circuit (BC) 200 has a calibration storage unit (CALS).
T) 310. Marker type (MKR) 3
02, the calibration storage unit (CAL
ST) 310 provides a calibration offset 312, which is added to the cycle count + vernier time (TM) 304 in adder (ADD) 314 to generate the calibrated time for that event. This calibrated time has an integer part (IP) 316 and a fractional part (FP) 317. For an 8-bit fraction, the calibrated time has a resolution of 256 in the base clock period. For a basic clock period of 3.2 ns, the resolution is 12.5 picoseconds (ps).

To achieve the required resolution, a linear delay line is used, as described below. For a delay line with a retrigger rate of about 10 ns, four delay lines (and thus four barrel circuits 20) are needed to allow four events to occur in the 10 ns test period.
0) is used. For higher overall event rates, more or faster delay lines are needed.

In addition to the event type and event time, the event sequence has associated therewith a period counter number (PCT) (not shown). This allows a strobe (test) event to occur after the end of the event's test period. For example, D
In an event sequence that requires a response from memory in the UT, that response, which depends on the speed of the DUT, may occur after the end of the period of the event sequence. For that reason, the response must be read by a strobe (test) event having a time after the end of the test period of the event sequence. Therefore, the period counter 113 is provided, and the PCT sets each test period (that is, each address is E
(Provided by SSM122) increments the modulo of the number of period counters at the beginning of period counter 1 as the period counter for that test period.
Identify the next of thirteen. To avoid collisions, the number of period counters times the length of the test period should exceed the maximum event time in the event sequence.

At the beginning of the test period, the period vernier offset 18 is saved and a new count is started in the period counter (PC) 113 of the test period, which is incremented at every timing of the base clock 14. In the barrel circuit 200, an integer part 316 of the calibrated event time is compared with a counter 113 by a comparator (COMP) 202. If they are equal, a fractional portion 317 of the calibrated time is implemented using a linear delay line (LDL) 204. If there is a match in the comparator 202, trigger a linear ramp (LR) 206,
It produces a signal that rises linearly over its range in the basic clock cycle. The fractional part of the calibration time is the digital-to-analog converter (DA
C) Converted to analog form at 208, which has been calibrated, so the input to DAC 206 of 255 (assuming an 8 bit fraction) triggers ramp 206 from the output of linear ramp 206 at one basic clock cycle time. Then, an output equal to the one-bit resolution (12.5 ps) is subtracted. Therefore, the output of the comparator 210 is the edge at the calibrated event time.

Not shown is the processing of events on the strobe (test) side where the pin state is tested. The logic is driven except that the round trip delay time is added when calculating the calibrated time and signal STZ (not shown) is used to define the test period boundaries. Corresponds to side logic. Separate linear delay lines (not shown) are provided, one in each barrel circuit 200 for timing strobe events. The round trip delay is implemented in a shift register inserted between the comparator 202 and a separate delay line, so that the edge generated in the comparator 202 will be delayed before it triggers the separate delay line. It is delayed by a programmable number of clock cycles. This round trip delay is typically fixed for a particular test setup to reflect certain factors in the setup, such as cable length. The PCT value for the event sequence and the corresponding period counter 113 are used to associate the strobe event with the test period and event.

Acceleration Mode The architecture described above is one operation of the architecture in acceleration mode that doubles the apparent test rate without increasing the frequency of the base clock 14 or the speed of the test system components. It can be realized as a mode (normal mode). Referring to FIG. 5, a test system as described above is operated in acceleration mode when the signal AM = 1,
When the signal AM = 0, the operation is performed in the normal mode. The addresses and other signals shown in FIG. 5 can be transmitted via any type of signal path appropriate to the signal bandwidth.

In the normal mode, the global address GA01 and the global high-order address bit GA01_
MSB is event sequence start memory ESSM0
1350 and ESSM23 352. AM
If = 0, the selector 340 selects the address GA0.
Pass 1 (0 input of selector) to ESSM 23.
Therefore, the same global address GA01 is the ESSM
01 and ESSM 23, and one or the other output is used, depending on the value of the higher order address bit GA01_MSB. In normal mode, the output of gate 355 is GA01_MSB. GA01_M
If SB is 0, the output of gate 355 is 0 and selector 354 has its 0 input, namely ESSM01.
From the start address to the event sequence storage section ESS01, and the selector 35
6 to the event sequence store ESS23 (these event sequence stores are ESS0
1 and ESS23, because when used together in normal mode as one memory, they are four event words ESS1.
Events 0 and 1 corresponding to 40 (ESS01 36
0) and event sequence start addresses for those that are events 2 and 3 (ESS23 362). The designations ESSM01 and ESSM23 are also selected for the same reason).

GA01_MSB is 1 in normal mode
, The output of gate 355 is 1 and it is provided to both ESS01 and ESS23 E
This is the start address from the SSM 23. In either case, when AM = 0, the global address formed by the union of GA01 and GA01_MSB selects the start address supplied to both event sequence stores ESS01 and ESS23, which are: A pair of time and event decoders 1 each
Two events are provided, one for each of the 42. Therefore, when AM = 0, the test system operates as described above.

On the other hand, in the acceleration mode, when AM = 1, the start address generated by ESSM01 is selected by GA01, and ESSM23
The start address generated by is selected by GA23, and GA01_MSB has no effect.
This is because the output of the gate 355 is always 0 in the acceleration mode. Therefore, ESS01 and ESS2
3 is able to start twice the test period in a given time frame, which can be started if two different addresses are given and AM = 0.

As is clear from FIG. 5, GA01_MS
Neither B nor GA 23 are active. In the acceleration mode, GA23 is used but GA01_MSB is not used, and in normal mode, GA01_MSB is used, but GA23
Is not used. Therefore, in order to minimize the width of the data path needed to supply the global address to the per-pin section 101, one of the bits of GA23 is GA01_MSB in normal mode.
It is possible to play a double role in giving.

As previously mentioned, each event carries an address increment bit, which is used to flag the last event that ends the event sequence. In acceleration mode,
The ESS01 and ESS23 event sequences are terminated separately, and the event sequences sharing a major period need not be the same length. On the other hand, in the normal mode, the event sequence is ESS01 or ESS2.
It can be terminated at any of the three, and its termination triggers the start of the next event sequence.

To enable reconfiguration when all event sequence start memories (ESSM01 and ESSM23) are used regardless of whether acceleration mode is selected or not, the global sequence control memory 121 is The width is expanded to provide twice the number of addresses, so all positions in both ESSM01 and ESSM23 can be addressed separately.

The time calculated in barrel circuit 200, and thus ESS 140 (or E in acceleration mode)
The event times of the events stored in SS01 and ESS23) are all defined by the signal TIME ZERO (time zero) 16 which defines what is called the main period.
(Ie, signal STZ for strobe event) is calculated (and thus defined). It is possible to implement a boundary marker signal for half the period of use to act as a time reference for events in ESS 23 in accelerated mode. However, this is not absolutely necessary. Instead, the test compilation process (computer program) that translates the test program expressed by the test engineer into instructions for the test system, if the test engineer requires testing in accelerated mode,
It takes the event sequences stored in the odd event sequence store (ESS23) and increments their event times by half the period of use. Therefore, the test engineer can easily program the event sequence with a test period frequency that is twice as fast as the actual time 0 frequency.

In normal mode, if the functional memory provides 4 bits of functional data for each test period, all the bits that make up one complete test vector go to each time and event decoder 142. Supplied. In accelerated mode, the event sequence from ESS01 is independent of that from ESS23,
And logically the test vectors for these event sequences are also independent. To provide independent test vectors in accelerated mode, functional data memory 131 can be partitioned in the same manner that ESSM 122 and ESS 140 are partitioned, thereby allowing independent shorter test vectors in accelerated mode. It is possible to provide (partial test vector) (remember that 2 bits of functional data in the 2-bit partial test vector are sufficient to program the sequence shown in FIG. 2D). is there). However, it is possible for the program to achieve the same effect in the test program compilation process. For example, if a test engineer programs a test for accelerated mode with an event sequence having two data bits per event sequence, all event sequences in the engineer's program will be F1 and F2 (these symbols are defined earlier). There is only). Once translated for operation in the test system, the event sequences assigned to the odd event sequence store (ESS23) are modified to reference F3 and F4, respectively, and the data is thus stored in the functional data memory 131. The loaded and functional data memory 131 is configured to provide 4 bits of data for each test period. Thus, in order to support the acceleration mode, the barrel circuit 20
No changes to the 0 or functional data memory 131 are required.

Using the techniques described above, the output of the event sequence start memory, the event sequence store, and the functional data memory is subdivided, and the width of the global sequence control memory is increased again, 4 per event sequence. It is possible to provide four times the event period frequency with one part functional data. This 4-fold increase in test period frequency can be referred to as the dual acceleration mode.

Referring to FIG. 6, a test system as described above is operated in dual acceleration mode (DAM) when signal 671 is 1 and in acceleration mode (AM) when signal 672 is 1. It is operated and in normal mode (NM) when signal 673 is one. Signal 67
It is 1 at the time when only one of 1,672,673 exists. The output of OR gate 674 is 1 when the test system is in normal mode or acceleration mode. The output of OR gate 675 is 1 when the test system is in acceleration mode or dual acceleration mode. Address paths GA0, GA1, GA2, GA3 provide addresses from global section 100. For convenience of explanation, each of these four paths is taken as providing 10 bits. Also, as in the prior art, the terms GA0, GA1, GA2, GA3 can be used to mean the addresses on the address path.

In dual acceleration mode, four event sequence start memories, namely ESSM0 65
0, ESSM1 651, ESSM2 652, ESS
Each M3653 is an independent 10-bit (eg)
"Addressed by address, therefore GA0, GA
1, GA2 and GA3 are memories ESSM0 and ESS, respectively.
In each of M1, ESSM2, ESSM3, a 10-bit address must be provided to address a 1K word (corresponding excitation value of the size of the address).

In the acceleration mode, the four event sequence start memories are pairwise, ie ESSM0 and ESS.
M1 and ESSM2 and ESSM3. Therefore, for a 1K memory, two independent 11-bit addresses are needed. As shown in FIG. 6, these two addresses are GA0, each providing 10 bits.
, And GA2, and two bits, which can be taken from any of the 20 bits in GA1 and GA3, which give the eleventh bit in each address. These two bits are GA0MSB and GA in order to represent their role in the acceleration mode, ie to act as the higher order bits of GA0 and GA2.
Shown as 2 MSBs.

In the normal mode, four event sequence start memories, namely ESSM0, ESSM1,
ESSM2 and ESSM3 operate as one memory. Therefore, in the case of 1K memory, one 12-bit address is required. As shown in FIG. 6, 10 bits of the 12-bit address are provided by GA0 and the other two bits are GA1, GA2, GA.
It can be taken from any of the 30 bits in 3. These two bits are designated as GA0MSB and GA0SMSB, indicating that they serve as the most significant bit and the second most significant bit of that address (note that it is used as GA0MSB in accelerated mode). The address bits are not required, but can be the same bits used as GA0MSB in normal mode).

In the normal mode, the address GA0 is AN
It is gated through the D gates 610, 613, 616 and then through the OR gates 614, 616, 618, while addressing GA1, GA2, GA3.
Are blocked by AND gates 612, 615, 617, 619. Therefore, the same address has four memories ESSM0 650, ESSM in the normal mode.
1 651, ESSM2 652, ESSM3 653
Is supplied to each. One of the four memories outputs the event sequence storage units ESS0 660, ESS1 661, ES by the operation of the selector 655.
Supplied as an address to S2 662, ESS3 663. The selector 655 operates as two higher-order bits of the 12-bit address supplied to the event sequence start memory, GA0MSB and GA0S.
Depending on the state of the MSB, its four inputs (ESSM0,
One of ESSM1, ESSM2, ESSM3). The output of the selector 655 is the AND gate 63.
3, 637, 638, 642 gated to four event sequence stores and then O
Gated through R gates 632, 636, 640, 644, while the other paths to these four event sequence stores are AND gates 630, 631, 6
Blocked by 34, 635, 639, 641, 643, 645. Therefore, in the normal mode, the same address has four event sequence storage units ESS.
0 660, ESS1 661, ESS2 662, E
Supplied to each of SS3 663.

In the acceleration mode, the address GA0 is A
Gated through ND gate 610 and then through OR gate 611, and address GA2 is then OR gate 618 through AND gates 615 and 617.
Gated through the other, while addresses GA1 and GA
3 is blocked by AND gates 612 and 619. Thus, in accelerated mode, GA0 is provided to each of memories ESSM0 650 and ESSM1 651, and GA2 is stored to memories ESSM2 652 and E.
Supplied to each of the SSM3 653. One of the outputs of ESSM0 and ESSM1 is output by the operation of the selector 654 to the event sequence storage units ESS0660 and ESS.
It is supplied as an address to 1661. Similarly, E
The output of one of SSM2 and ESSM3 is output by the operation of the selector 656 to the event sequence storage unit ES.
It is supplied as an address to S2 and ESS3. The selector 654 is an event sequence start memory ES
Depending on the state of bit GA0MSB, which acts as the higher order bit of the 11-bit address supplied to S0 and ESS1, its two inputs (ESSM0 or ESSM
Select one of 1). Similarly, selector 656
Are event sequence start memories ESS2 and E
One of its two inputs (ESSM2 or ESSM3) is selected according to the state of the bit GA2MSB operating as the higher order bit of the 11-bit address supplied to SS3. The outputs of selectors 654 and 656 are gated to the four event sequence stores via AND gates 632, 634, 641, 643 and then OR gates 632, 636, 640, 644, while the four events are Other routes to the sequence store are AND gates 630, 633, 635,
Blocked by 637, 638, 639, 642, 645. Therefore, in the acceleration mode, one address is stored in the event sequence storage unit ESS0 660.
And ESS1 661, and an independent address is provided to each pair of event sequence stores ESS.
2 662 and ESS3 663 respectively.

In the double acceleration mode, the address GA
0 is fed directly to ESSM0 650 (because they are in the other two modes) and address GA1 is passed through AND gate 612 and then OR gate 6
11 to ESSM1 651 and address GA2 is gated to ESSM2 652 via AND gate 615 and then OR gate 614, and address GA3 is via AND gate 619 and then. Gated to ESSM3 653 via OR gate 618, while other addresses are AND gates 610, 613, 616, 616.
Other event sequence start memory is blocked by 617. Therefore, in dual acceleration mode, only GA0 is fed to ESSM0 650,
Only GA2 is fed to ESSM1 651, only GA1 is fed to ESSM2 652, and only GA3 is fed to ESSM3 653. Similarly, the AND gates 630, 635, 639, and 645 respectively cause E
Only the output of SSM0 is fed to ESS0 660, and E
The output of SSM1 is fed to ESS1 661 only, and E
The output of SSM2 feeds only ESS2 662, and the output of ESSM3 feeds only ESS3 663. All other circuit paths extending through the selectors 654, 656, 656 are AND gates 631, 633.
Blocked by 634, 637, 638, 641, 642, 643. Therefore, in the double acceleration mode, independent addresses are stored in the event sequence storage section ES.
S0 660, ESS1 661, ESS2 662,
Supplied to each of the ESS3 663.

It should be understood that the addresses and other signals shown in FIG. 6 can be transmitted via any type of signal path appropriate to the signal bandwidth. It should also be noted that the memories in the perpin section 101 need not be the same size, nor are they required to be divided into the same number of parts or to be the same size.

By using the acceleration mode, the apparent speed of the test system (the number of event sequences that can be started in a unit time) is doubled, with the amount of local memory required increasing. It is not necessary to increase or increase the speed of operation of the components and still maintain compatibility with previous architectures and reduce the user's flexibility when combining event and functional data into event sequences. Not even a thing. For example, without being limited to starting one event sequence every 10 ns, the user can start two event sequences at that time, in which case separate global sequence addresses GA01 and GA23 and separate Use the functional data of. The cost in this increase in test cycle speed is that the single-period event sequence
That is, it does not have the number of events stored in each word of 0, but only the number of events stored in each word of ESS01 or ESS23.

The present invention is an architecture that does not divide physical resources into global and local sections, an architecture that provides the function of a global address with locally replicated address resources, or a globally or commonly assigned architecture. It can be implemented in an architecture that provides a local memory function from memory to memory resources.

Although the specific embodiments of the present invention have been described in detail, the present invention should not be limited to these specific examples, but may be variously modified without departing from the technical scope of the present invention. Of course is possible.

[Brief description of the drawings]

FIG. 1A is a schematic block diagram showing a part of a test system.

FIG. 1B is a schematic block diagram showing a part of a test system.

FIG. 2A is a graph illustrating a test pattern generated by a test system for an event sequence.

FIG. 2B is a graph showing a test pattern generated by a test system for an event sequence.

FIG. 2C is a graph showing a test pattern generated by a test system for an event sequence.

FIG. 2D is a graph showing a test pattern generated by a test system for an event sequence.

FIG. 3 is a schematic diagram showing a clock signal.

FIG. 4 is a schematic block diagram showing matching and linear delay line circuits, also called barrel circuits.

FIG. 5 is a schematic block diagram showing a memory connected to provide improved tester timing in normal mode and acceleration mode.

FIG. 6 is a schematic block diagram illustrating a memory connected to provide improved tester timing in normal mode, acceleration mode, and dual acceleration mode.

[Explanation of symbols]

 100 Global Section 101 Per Pin Section 111 Global Address Counter (AC) 121 Global Sequence Control Memory (GSCM) 131 Per Pin Functional Data Memory (FDM) 140 Local Event Sequence Store (ESS) 142 Event Decoder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Egbert Glebe United States, California 94022, Los Altos, Arbor Avenue 1400

Claims (11)

[Claims] 1. A test system having an operation mode including a normal mode and an acceleration mode and providing an event sequence for testing a circuit, comprising: (a) a first start memory and a second start memory; A first sequence memory and a second sequence memory each providing an event sequence in response to a sequence memory address, (c) means responsive to an operating mode of the system, wherein in the normal mode the first start memory and A second start memory is electronically coupled to both the first sequence memory and the second sequence memory so that a single sequence memory address is provided to the first and second sequence memories from the first and second start memories. And in the acceleration mode, the first start memory Is electronically coupled to the first sequence memory and the second start memory is electronically coupled to the second sequence memory, so that a first sequence memory address is provided by the first start memory to the first sequence memory. Means for responding to an operating mode of the test system in which a supplied and independent second sequence memory address is supplied by the second start memory to the second sequence memory. 2. The test system according to claim 1, wherein the first start memory and the second start memory have the same size. 3. The test system according to claim 1, wherein the first sequence memory and the second sequence memory have the same size. 4. The test system of claim 3, wherein the first sequence memory generates one word wide enough to hold at least two events. 5. The test system according to claim 4, wherein the test system operates on a basic test period, and during a test period in which the test system is operated in both the normal mode and the acceleration mode,
A test system characterized in that for each basic test period, a sequence memory address is supplied to both the first sequence memory and the second sequence memory. 6. The functional data memory according to claim 5, further comprising: a functional data memory for supplying a test vector, the functional data memory comprising a complete test in the normal mode for each basic test period. A test system characterized by providing at least 2 bits of functional data in a vector. 7. The test of claim 6, wherein the functional data memory provides at least 4 bits of functional data in a complete test vector in the normal mode for each elementary test period. system. 8. The test system according to claim 1, further comprising a dual acceleration mode, further comprising: (a) a third start memory and a fourth start memory; and (b) a sequence memory address. A third sequence memory and a fourth sequence memory for giving an event sequence in response to the following: (c) means for responding to an operation mode of the test system, wherein in the normal mode, the first, second, third and A fourth start memory is electronically coupled to all of the first, second, third and fourth sequence memories so that a single sequence memory address is the first, second,
The first and second start memories are supplied from the third and fourth start memories to the first, second, third and fourth sequence memories, and in the acceleration mode. Electronically and both the third and fourth start memories are electronically coupled to both the third and fourth sequence memories, so that the first sequence memory address is the first and second start memories. Is supplied to the first and second sequence memories and an independent second sequence memory address is supplied to the third and fourth sequence memories by the third and fourth start memories, and in the double acceleration mode. , The first, second, third and fourth start memories respectively, and the first, second, third and fourth sequence memories respectively. Electronically coupled to the second sequence memory, so that a first sequence memory address is provided by the first start memory to the first sequence memory and an independent second sequence memory address is provided by the second start memory to the second sequence memory. An independent third sequence memory address is provided to the third sequence memory by the third start memory,
And a means for responding to an operating mode of the system in which an independent fourth sequence memory address is provided to the fourth sequence memory by the fourth start memory. 9. The functional data memory according to claim 8, further comprising a functional data memory for supplying a test vector, said functional data memory comprising a complete test in said normal mode for each basic test period. A test system characterized by providing at least 2 bits of functional data in a vector. 10. The method according to claim 1, further comprising: (a) a first global address path for a first global address, a second global address path for a second global address, and a higher order bit address for a global higher order address bit. A path is provided, (b) the first start memory is coupled to the first global address path, and (c) the second start memory is responsive to an operating mode of the test system. Via the first global address path if the operation mode is the normal mode, and to the second global address path if the operation mode is the acceleration mode, d) The output of the first start memory as its first input and the second start memory as its second input. A first input as its output when said operating mode is said accelerating mode in response to said operating mode and global higher order address bits and said operating mode. Is in the normal mode, a second selector is provided which supplies either its first or second input as its output in accordance with the value of the global higher order address bit, and (e) its first input Is connected to receive the output of the second selector as the second input and the output of the second start memory as its second input, and outputs the operation mode in the normal mode in response to the operation mode. As a third selector for supplying its first input and its second input when the operation mode is the acceleration mode (F) a gate circuit connected to receive the operating mode of the test system as its first input and the global higher order address bits as its second input, the output of which is A gate circuit that is the global higher-order address bit input when in the normal mode and is 0 when the operation mode is the acceleration mode, (g) a sequence memory address output by the second selector A first sequence memory is provided for supplying an event sequence in response to, and (h) a second sequence memory is provided for supplying an event sequence in response to the sequence memory address output by the third selector. A test system characterized by the fact that 11. The method according to claim 8, further comprising: (a) a first global address route for a first global address, a second global address route for a second global address, a third global address route for a third global address, and a fourth. A fourth global address path for global addresses is provided, and (b) is responsive to the operating mode of the test system and connects the first, second, third and fourth global address paths to the first, second, The third and fourth start memories are coupled to each other so that the same address in the normal mode is the first,
Supplied to the second, third and fourth start memories, and in the acceleration mode a first address is supplied to the first and second start memories and different second addresses are supplied to the third and fourth start memories. And in the dual acceleration mode separate addresses are provided for the first, second,
A logic circuit is provided to be supplied to each of the third and fourth start memories, and (c) the first, second, third and fourth start memories are responsive to the operation mode of the test system. Coupled to the first, second, third and fourth sequence memories, so that in the normal mode the same address is supplied to the first, second, third and fourth sequence memories and in the acceleration mode. , A first address is provided to the first and second sequence memories and different second addresses are provided to the third and fourth sequence memories, and in the double acceleration mode, separate addresses are provided for the first, A test system characterized in that a logic gate is provided to each of the second, third and fourth sequence memories.