JPH09121152A - Mosfet circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed operation and low power consumption while employing a wide range of a power supply voltage. SOLUTION: A MOSFET circuit 111 (112) being power supply control circuits to control standby/operation is connected between a low threshold voltage CMOS circuit group 3 and a power supply voltage point VDD (ground point). AMOS FET M1 (M3) with a high threshold voltage of the MOSFET circuit 111 (112) receives a back gate bias with a MOS FET M2 (M4) with a low threshold voltage to block a current between a back gate terminal and a gate terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET capable of realizing high speed operation and low power consumption in a wide power supply voltage range from low voltage to high voltage, and more particularly to SOI.
(Silicon On Insulator) MOSFE suitable for integrated circuits
T and a CMOS logic circuit using the same.

[0002]

2. Description of the Related Art As a conventional low-voltage CMOS logic circuit, there is a circuit described in JP-A-6-29834. As shown in FIG. 1, this CMOS logic circuit uses a plurality of MOSFETs having a low threshold voltage (for example, 0.2 V) and a high threshold voltage (for example, 0.6 V) to provide a dry battery power source ( It is operable at about 1V). That is, a low threshold voltage MOSFET, which has a large leak current at the time of interruption but can operate at high speed, and a MOSFET with a high threshold voltage, which has a slow operation speed but a small leakage current at the time of interruption, are skillfully combined. Circuit.

Specifically, a high potential power (VDD) line 1,
In addition to the low-potential power supply (VSS) line 2 (which is normally grounded in FIG. 1 and is therefore grounded), a high-potential pseudo power supply (VDDv) line 41 and a low-potential pseudo power supply (VDDs) line 51 are connected. A low-threshold CMOS logic circuit group 3 composed of a low-threshold voltage p-channel MOSFET M11 and an n-channel MOSFET M12 is connected between the pseudo power supply lines 41 and 51. High potential pseudo power line 41
A high threshold voltage p-channel MOSFET M13 is connected between the high-potential power supply line 1 and the high-potential power supply line 1, and a high threshold voltage n-channel type is further provided between the low-potential pseudo power supply line 51 and the low-potential power supply line 2. It is configured by connecting MOSFET M14. 4 is MOSFET / M13 and high potential pseudo power line 4
High-potential-side power supply control circuit consisting of 1 and 5 are MOSFETs
A low-potential-side power supply control circuit including M14 and a low-potential pseudo power supply line 51.

In this circuit, the logic circuits of the CMOS logic circuit group 3 have low threshold voltage MOSFETs M11 and M1.
Since it is composed of two components, etc., high-speed operation can be realized even with a low power supply voltage. Further, by providing a high threshold voltage p-channel type MOSFET M13 and a high threshold voltage n-channel type MOSFET M14 in the path for supplying current to the low threshold voltage CMOS logic circuit group 3. , C during standby (when the sleep signal SL is at “H” level)
The leakage current of the MOS logic circuit group 3 is reduced to save power. Note that * SL is an inverted signal of the sleep signal SL.

Further, the circuit proposed in Japanese Patent Application No. 6-334640 is an improvement of the circuit shown in FIG. 1 described above, and as shown in FIG. 2, it has a high potential side and a low potential side. MOSFET M1 that constitutes power supply control circuits 4 and 5
3, the back gate electrode (substrate) terminal of M14 is connected to the gate terminal.

A MOSFET having a variable threshold voltage is realized by connecting the back gate terminal to the gate terminal. This is due to the back gate effect (a phenomenon in which the threshold voltage changes when a voltage is applied to the back gate in the MOSFET), and the MOSFET M1 during operation is
This is because the threshold voltage of M3 and M14 becomes small. Therefore, in the circuit shown in FIG. 2, the power supply voltage can be further reduced.

In these circuits, low threshold CMOS
For the logic circuit group 3, pseudo power supply lines 41 and 51 and high threshold voltage MOSFETs M13 and M14 are provided on both the high potential power supply side and the low potential power supply side. A pseudo power supply line or a MOSFET having a high threshold voltage is provided on only one of the low voltage power supply side.

[0008]

By the way, the same integrated circuit may be used in a wide range of power supply voltages as well as a low voltage power supply. For example, the low voltage of 1 V or less to 3 V to 5 V may be used.

Consider the high threshold voltage n-channel MOSFET M14 for control of the circuit shown in FIG. The following description also applies to the other MOSFET M13. n-channel type MOSFET M1
4, since the back gate region (substrate or well in the bulk MOS structure) portion is a p-type semiconductor, the parasitic diode D3 is formed between the back gate region and the source S, and the MOSFET M14 shown in FIG.
The equivalent circuit of (FIG. 3 (A)) becomes a circuit as shown in FIG. 3 (B).

Here, the gate-source voltage Vgs of the MOSFET M14 increases, and the voltage Vgs increases.
Exceeds the forward voltage Vf of the parasitic diode D3 (a voltage at which a current flows out when the voltage is applied in the forward direction and is increased, which is about 0.8 V), the parasitic diode D3 becomes conductive. Therefore, a path of gate terminal → back gate terminal → parasitic diode D3 is formed, and the gate current is significantly increased.

Therefore, the control MOSFET of FIG.
・ When M14 is on, * SL = Vgs = VDD
Since it is (power supply voltage), this circuit cannot supply current to the low threshold CMOS logic circuit group 3 when VDD ≧ Vf.

On the other hand, FIG. 4 shows an example of a CMOS circuit which can be operated at a high speed with a power supply voltage of 1 V or less, which is close to the threshold voltage of the MOSFET. This is T. Andoh, et.
al., “Design Methodology for Low-Voltage MOSFET
s ”, IEDM Technical Digest, pp.79-82, 1994.

The circuit of FIG. 4 is a p-channel MOSFET M
CMO composed of 3 and n-channel MOSFET M4
It is an S inverter, but each MOSFET / M
The gate terminals and back gate terminals of M3 and M4 are commonly connected. Reference numeral 14 is a signal input terminal, and 15 is a signal output terminal.

Regarding the p-channel MOSFET M3, when the gate terminal connected to the signal input terminal 14 has a low level voltage (equal to the ground voltage), the voltage of the back gate terminal connected to the gate terminal also drops. ,
A forward bias is applied between the back gate region (n-type semiconductor) and the source region (p-type semiconductor).

Regarding the n-channel MOSFET M4, when the gate terminal connected to the signal input terminal 4 has a high level voltage (equal to the power supply voltage VDD), the voltage of the back gate terminal connected to the gate terminal is also Ascending, the back gate region (p-type semiconductor) and the source region (n
Type semiconductor) is forward biased.

In the MOSFET, whether the p-channel type or the n-channel type, when the back gate region and the source region are forward biased, the depletion layer width of the back gate region becomes small. The threshold voltage of the MOSFET is determined by the ratio of the gate capacitance C _OX and the charge density Q _{B of the} depletion layer,
As the width of the depletion layer becomes smaller, Q _B becomes smaller, so that the threshold voltage becomes smaller. In the p-channel, the absolute value of the threshold voltage becomes small.

Therefore, in the CMOS inverter shown in FIG. 4, when the signal input terminal 14 becomes a high level voltage, that is, when the n-channel MOSFET M4 is turned on, only the n-channel transistor M4 is turned on. When the threshold voltage decreases to a low level voltage, that is, when the p-channel MOSFET M3 is in the ON state, the threshold voltage of only the p-channel MOSFET M3 decreases. When the threshold voltage decreases,
Since the current drivability is further increased, high speed operation can be performed even with a power supply voltage of 1 V or less, which is close to the original threshold voltage.

However, the circuit shown in FIG.
There are the following problems. 3 CMOS inverter of FIG.
Consider the circuit shown in FIG. 5 in a stage chain connection. Assuming that the low level voltage (L) and the high level voltage (H) are in the state shown in FIG. 5, the input terminal of the inverter # 3 is at the low level, and the p-channel MOSFET For M33, the gate terminal is equal to ground potential and the source terminal is equal to power supply voltage VDD.

Therefore, the p-channel MOSFET
A forward parasitic diode having a source terminal (p-type semiconductor) as an anode and a back gate terminal (n-type semiconductor) as a cathode is generated in M33. On the other hand, since the gate voltage of the n-channel MOSFET M42 of the inverter # 2 in the preceding stage is the power supply voltage VDD, it is in the ON state.

Therefore, as indicated by the broken line in FIG. 5, the power supply terminal → the source of the p-channel MOSFET M33 which is turned on (p-type semiconductor) → the back gate terminal (n-type semiconductor) of the transistor M33 → the n-channel MOSF which is turned on.
A short-circuit current from the power supply terminal to the ground terminal is generated in the path of the drain of the ET • M42 → the source of the transistor M42 → ground.

Similarly, the power supply terminal → the source of the p-channel MOSFET M31 which is turned on → the same transistor M3
1 drain → n-channel MOSFET M4 turned on
A short-circuit current is generated in the path of the back gate terminal (p-type semiconductor) of 2 → the source of the transistor M42 (n-type semiconductor) → ground.

Since the forward current of the pn junction diode exponentially increases according to the applied voltage, the forward current rapidly increases with respect to the power supply voltage Vf (for example, 0.8 V) or more. In the CMOS circuit having the configuration shown in FIG. 5, a significant leak current is generated and the circuit does not operate. Therefore, the circuit shown in FIG. 5 has a problem that the value of the power supply voltage used is limited to the forward voltage Vf or less.

The present invention has been made in view of the above points, and an object thereof is to make the power supply voltage of a circuit equal to or lower than the forward voltage of a parasitic diode parasitic between a source region and a back gate region. Even with the above, a large current does not flow in the parasitic diode, and the MOSF has solved the above problems.
It is to provide an ET circuit.

Another object of the present invention is to provide a CMOS circuit which realizes high speed operation and low power consumption in a wide power supply voltage range.

[0025]

According to the present invention, there is provided a first MOSFET having a first threshold voltage and a second MOSFET having a second threshold voltage equal to or lower than the first threshold voltage. MO
A second SFET having a gate electrode and a first main current electrode connected to a back gate electrode of the first MOSFET and a second main current electrode connected to an externally supplied signal. And a MOSFET.

In the above MOSFET circuit, the first
The main current electrode is a source electrode, and the second main current electrode is a drain electrode.

In the above MOSFET circuit, the first
Gate electrode of the second MOSFET and the second MOSFE
It is characterized in that it is connected to the second main current electrode of T.

In the above MOSFET circuit, the second
Threshold voltage is lower than the first threshold voltage.

In the above MOSFET circuit, the second
The threshold voltage of 1 is equal to the first threshold voltage.

According to the present invention, in a CMOS logic circuit having a load transistor and a drive transistor connected in series, one of the drive transistor and the load transistor includes a first MOSFET circuit, and the first MOSFET circuit is provided.
Is a first MOSFET having a first threshold voltage, the first MOSFET being connected in series with the other of the drive transistor and the load transistor, and the first threshold voltage. Lower second
Has a threshold voltage of, a gate electrode and a first main current electrode are connected to a back gate electrode of the first MOSFET, and a second main current electrode is the first MOSF.
And a second MOSFET connected to the gate electrode of ET.

In the above logic circuit, the other one of the drive transistor and the load transistor is a MOSFET, and the CMOS logic circuit is a CMOS inverter.

In the above CMOS logic circuit, the load transistor has M (M is an integer larger than 1) MOSFETs connected in series, and the driving transistor has M first MOSFET circuits connected in parallel. And the CMOS logic circuit is a NOR circuit.

In the above CMOS logic circuit, the load transistor has M (M is an integer greater than 1) MOSFETs connected in parallel, and the drive transistor has M first first elements connected in series. It has a MOSFET circuit, and the CMOS logic circuit is a NAND circuit.

In the above CMOS logic circuit, the other one of the drive transistor and the load transistor is the second MO.
An SFET circuit, the second MOSFET circuit is a third MOSFET having a third threshold voltage, and is a third MOSFET connected in series with the first MOSFET circuit.
And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the MOSFET being the back of the third MOSFET. Second, connected to the gate electrode
And a fourth MOSFET connected to the gate electrode of the third MOSFET.

The CMOS logic circuit is characterized by being a CMOS inverter.

In the above CMOS logic circuit, the drive transistor includes M MOSFET circuits (M is an integer greater than 1) connected in parallel, and the load transistor is M connected in series with the second MOSFET. MOSF
An ET circuit is included, and the CMOS logic circuit is a NOR circuit.

In the above CMOS logic circuit, the drive transistor includes M (M is an integer larger than 1) first MOSFET circuits connected in series, and the load transistor is connected in parallel to the M first MOSFET circuits. 2 MOSFE
A CMOS logic circuit including a T circuit, wherein the CMOS logic circuit is a NAND circuit.

According to the present invention, the first Cs are connected in cascade.
In a buffer circuit having a MOS inverter and a second CMOS inverter, the load transistor of the first CMOS inverter is a first MOSFET having a first threshold voltage, and the load transistor of the first CMOS inverter is A first MO connected in series with the drive transistor
An SFET and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first main current electrode of which are the first M
A second MOSFET connected to the back gate of the OSFET and having a second main current electrode connected to the gate electrode of the first MOSFET, wherein the drive transistor of the second CMOS inverter has a third A third MOSFET having a threshold voltage, the second CMO
Third connected in series with load transistor of S inverter
And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the third MOSFET of Second, connected to the back gate electrode
And a fourth MOSFET connected to the gate electrode of the third MOSFET.

The present invention is a low threshold CM including a MOSFET having a threshold voltage lower than a first threshold voltage.
In a CMOS logic circuit having an OS logic circuit and at least one switch circuit connected between a power supply terminal and a power supply of the low threshold CMOS logic circuit, the switch circuit is the first threshold. First with a value voltage
Of the MOSFET, the power supply and the low threshold C
A first MOSFET connected between a power supply terminal of a MOS logic circuit and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate of which is An electrode and a first main current electrode are connected to the back gate electrode of the first MOSFET,
The main current electrode of the second MOSFET is connected to the gate electrode of the first MOSFET.

In the above CMOS logic circuit, the switch circuit includes a high potential terminal of the power source and the low threshold value C.
It is characterized in that it is connected to the high potential power supply end of the MOS logic circuit.

In the above CMOS logic circuit, the switch circuit includes a low potential terminal of the power source and the low threshold value C.
It is characterized in that it is connected to the low potential power supply end of the MOS logic circuit.

In the above CMOS logic circuit, the switch circuit is further connected between a low potential terminal of the power supply and a low potential power supply terminal of the low threshold CMOS logic circuit. Logic circuit.

According to the present invention, a CMOS logic circuit is a CMOS logic circuit which is switched to a sleep state or an operating state by a sleep signal from the outside, and has a first buffer connected to its non-inverted sleep signal input terminal. , A second buffer connected to the inverted sleep signal input terminal, wherein the first buffer is alternately cascaded with the first CMOS inverter and the second CM.
An OS inverter, wherein the load transistor of the first CMOS inverter is a first MOSFET having the first threshold voltage, and the load transistor is the first CMOS.
A first MOSFET connected in series with a drive transistor of an inverter; and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first MOSFET A main current electrode is connected to the back gate electrode of the first MOSFET,
A second MOSFET whose main current electrode is connected to the gate electrode of the first MOSFET, and the drive transistor of the second CMOS inverter is a third MOSFET having a third threshold voltage. And a third MOSFET connected in series with the load transistor of the second CMOS inverter, and a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage.
T, the gate electrode and the first main current electrode of which are connected to the back gate electrode of the third MOSFET, and the second main current electrode of which is connected to the gate electrode of the third MOSFET. With 4 MOSFETs,
The second buffers are the second buffers that are alternately connected in cascade.
3. A CMOS logic circuit comprising: the CMOS inverter and the first CMOS inverter.

According to the present invention, the CMOS logic circuit is a CMOS logic circuit which is switched to a sleep state or an operating state by a sleep signal from the outside, and further comprises a buffer connected to the non-inverted sleep signal input terminal. However, the buffers are first cascaded alternately.
And a second CMOS inverter, wherein the load transistor of the first CMOS inverter has a first MOSF having the first threshold voltage.
A first MOSFET connected in series with the driving transistor of the first CMOS inverter, and a second MOSFET having a second threshold voltage lower than the first threshold voltage. And a gate electrode and a first main current electrode connected to a back gate electrode of the first MOSFET, and a second main current electrode connected to a gate electrode of the first MOSFET. MO
SFET, and the drive transistor of the second CMOS inverter has a third threshold voltage.
A third MOSF connected in series with the load transistor of the second CMOS inverter.
ET and a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the fourth MOSFET being the third MOS transistor.
A fourth MOSFET connected to the back gate electrode of the FET and having a second main current electrode connected to the gate electrode of the third MOSFET.

According to the present invention, a CMOS logic circuit is a CMOS logic circuit which is switched to a sleep state or an operating state by a sleep signal from the outside, and further comprises a buffer connected to its inverted sleep signal input terminal. The buffer has a first CMOS inverter and a second CMOS inverter that are alternately connected in cascade, and a drive transistor of the first CMOS inverter has a first threshold voltage having a first threshold voltage. A first MOSFET connected in series with a load transistor of the first CMOS inverter;
A second MOSFET having a second threshold voltage lower than the threshold voltage of, the gate electrode and the first main current electrode being connected to the back gate electrode of the first MOSFET, The second main current electrode is the first M
Second MOSFET connected to the gate electrode of the OSFET
T, and the load transistor of the second CMOS inverter has a third MO with a third threshold voltage.
SFET, which is a third MOSFET connected in series with the drive transistor of the second CMOS inverter
And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the fourth MOSFET being the third MOSFET.
A fourth main current electrode connected to the back gate electrode of T and a second main current electrode connected to the gate electrode of the third MOSFET;
And MOSFET.

The present invention includes an internal C which includes M (M is an integer of 1 or more) sets of drive transistors and load transistors and switches the operating state in response to a control signal from the outside.
A first MOSFET that is commonly connected to a MOS logic circuit and a first MOSFET circuit that constitutes one of the drive transistor and the load transistor, wherein a gate electrode and a first main current electrode are the first MOSFET. MOSFET
Said first MOSFET connected to a back gate electrode of a circuit and having a second main current electrode connected to said control signal
A CMOS logic circuit comprising a first MOSFET of the same channel type as the circuit.

The CMOS logic circuit is a second MOSFET that is commonly connected to a second MOSFET circuit that constitutes the other of the drive transistor and the load transistor, and has a gate electrode and a first main current electrode. Are connected to the back gate electrode of the second MOSFET circuit, and the second main current electrode is connected to the inverted signal of the control signal, and are the same channel type second MOSFET as the second MOSFET circuit. A CMOS logic circuit characterized by comprising:

In the above CMOS logic circuit, the first
And the threshold voltage of the second MOSFET is smaller than the threshold voltage of the MOSFET included in the internal CMOS logic circuit.

The internal CMOS logic circuit is characterized by including one or more CMOS inverters.

The internal CMOS logic circuit is characterized by including a transfer gate.

The internal CMOS logic circuit includes a memory cell, and the control signal is a word line signal.

In the above CMOS logic circuit, the control signal is a sleep signal for switching the internal CMOS logic circuit to a sleep state or an operating state.

Each MOSFET of the CMOS logic circuit
Is an SOIFET formed on an SOI (Semiconductor On Insulator) substrate.

In the above CMOS logic circuit, the impurity concentration of the body portion of the low-threshold MOSFET is adjusted so that the body portion is completely depleted. In the above CMOS logic circuit, a high threshold MO
It is characterized in that the impurity concentration of the body portion of the SFET is adjusted so that the body portion is partially depleted.

According to the present invention, the second MOSFET connected between the gate terminal and the back gate terminal of the first MOSFET functions as a reverse diode, and the current flowing from the gate terminal toward the back gate terminal is increased. Is blocked. As a result, even if the power supply voltage exceeds the forward voltage Vf of the parasitic diode parasitic between the source terminal and the back gate terminal of the first MOSFET, a large current is not passed through the parasitic diode and a high power supply voltage is used. it can. In addition, the first MOSFET has a variable threshold voltage, and the threshold voltage in the ON state becomes low, which enables high-speed operation. From the above, high-speed MOSFE with a wide power supply voltage range
T can be provided.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIGS. 6A and 6B show a MOSFET circuit according to a first embodiment of the present invention. First, FIG. 6A shows an n-channel type MOS with a high threshold voltage.
A low threshold voltage n-channel MOSFET M2 in which a drain terminal D is connected to a gate terminal G of the MOSFET M1 and a source terminal S and a gate terminal G are connected to a back gate terminal (substrate) of the FET M1. Composed of n
The channel type MOSFET circuit 112.

FIG. 6B shows a high threshold voltage p-channel MOSFET M3 and its MOSFET M.
3, a drain terminal D is connected to the gate terminal G, and a back gate terminal is connected to the source terminal S and the gate terminal G to form a p-channel MOSFET circuit 111 having a low threshold voltage p-channel MOSFET M4. .

The above-mentioned low threshold voltage MOSFET
The channel width of M2 and M4 may be about 1/100 of the channel width of the high threshold voltage MOSFETs M1 and M3. This is because it merely needs to function as a diode, as described below. Further, since the area is extremely small, the increase of the chip area by adding the MOSFETs M2 and M4 is extremely small.

The n-channel type MOSF shown in FIG.
In the ET circuit 112, when the power supply voltage VDD is applied to the drain terminal D, the input voltage Vin is applied to the gate terminal G, and the source terminal S is grounded, as shown in FIG. The equivalent circuit shown in FIG.

As described above, in the enhancement n-channel type MOSFET, since the back gate region of the enhancement type n-channel MOSFET is a p-type semiconductor, a parasitic between the back gate terminal and the source terminal S of the high threshold voltage transistor M1. The diode D3 is configured. Further, the low threshold voltage transistor M2 functions as a diode D1 that functions as a drain D (or source S) and the gate terminal G side as an anode and a source terminal S (or drain terminal D) side as a cathode.

The forward voltage Vf of the diode D3 is about 0.
It is 8V, and Vf of the diode D1 formed by the MOSFET M2 having a low threshold voltage is the threshold voltage of the transistor M2 (about 0.2V).

Next, the operation of the MOSFET circuit 112 will be described.

(1) Input voltage Vin (Vgs) = VDD
At this time, the circuit 112 is turned on. In this case, FIG.
The circuit is as shown in (C), and the forward current i3 of the diode D3 is regulated by the leak current of the diode D1. That is, as shown in FIG.
The anode potential Vb of 3 is limited by the dark current of the diode D1 and cannot rise above 0.8V. That is, although the voltage Vb of the back gate terminal is positive, it is clamped by the dark current of the diode D1 and therefore does not exceed Vf of the diode D3, and 0 <Vb ≦
It is 0.8V. Thus, the voltage V of the back gate terminal
Since b is positive, a high threshold voltage MOSFET M
The back gate effect works so that the threshold voltage of 1 becomes small. Therefore, the on-resistance decreases.

Further, the current from the gate terminal to the back gate terminal is blocked by the diode D1 connected in the reverse direction. Therefore, when VDD> 0.8V, the gate of the MOSFET M1 is turned on by turning on the diode D3. A large current flowing through the path of terminal G → back gate terminal → source terminal 3 is not generated.

(2) When the input voltage Vin (Vgs) = 0, the circuit 112 is turned off. At this time, the circuit equivalently becomes as shown in FIG. 7D, both the diode D1 and the diode D2 are turned off, and the voltage Vb of the back gate terminal becomes Vb = 0. Therefore, since the back gate effect does not occur in the MOSFET M1 having a high threshold voltage, the threshold voltage becomes high.

From the above, even if the power supply voltage VDD> 0.8V, the MOSFET M1 is made into a variable bias, that is, when the input voltage Vin = 0, the high threshold voltage, Vin =
It is possible to realize a variable threshold value that is a low threshold voltage when VDD.

FIGS. 9A and 9B are views showing an embodiment in which the n-channel MOSFET circuit 112 shown in FIG. 6A is formed on the SOI type integrated circuit. This figure 9
9A is a plan view, and FIG. 9B is a sectional view taken along line AA of FIG. High threshold voltage n-channel MOSFET M1
21 is drain, 22 is source, 23 is gate, 24
Is a body portion below the gate 23, and 25 is a back gate terminal. The body portion is a p-type region (in the case of an n-channel MOSFET) or an n-type region (in the case of a p-channel MOSFET) in the SOI structure MOSFET, and corresponds to the back gate region in the bulk structure. Low threshold voltage n-channel MOSFET
M26 is a source, 27 is a drain, 28 is a gate, and 29 is a body portion below the gate 28. 30 is wiring, 31 is a silicon substrate, 32 is a buried oxide film, 33
Is a contact hole.

The body portion 24 of the high threshold voltage MOSFET M1 is connected from the back gate terminal 25 to the gate 28 and the source 26 of the low threshold voltage MOSFET M2 by the wiring 30. Voltage MOSFET
The body portion 29 of M2 is floating and is not connected to the back gate terminal. The SOI-type MOSFET is different from the bulk-type MOSFET in that the body portion can be floated without providing a well for each MOSFET independently.

When the body portion is floated in this manner, the potential of the body portion rises and the threshold voltage drops. Therefore, MOSFET of SOI type structure
Then, a high threshold MOSFET and a low threshold MOSFET can be realized depending on the presence / absence of a bias to the body portion without using a special threshold adjustment mask in the process.

Independently of this, if the impurity concentration of the body portion is adjusted, the threshold voltage of the FET can be adjusted with high accuracy. FIG. 10 shows this relationship. That is, when the impurity concentration is reduced, the depletion layer width W increases, the voltage required to form a channel decreases, and the threshold voltage decreases.

In FIG. 11A, the impurity concentration is reduced to
A state in which the depletion layer width W is widened and the body portion 24A is a complete depletion layer is shown. In this state, the threshold voltage becomes low.
On the other hand, FIG. 11B shows a state in which the impurity concentration is increased, the depletion layer width W is reduced, and the body portion 24B is a partial depletion layer. In this state, the threshold voltage becomes high.

Therefore, a low threshold voltage MOSFET
The body portion 29 of M2 is in the fully depleted state shown in FIG. 11A, and the body portion 24 of the high threshold voltage MOSFET M1 is in the partially depleted state shown in FIG. 11B. By making the low threshold voltage MOSFET M2 fully depleted, the mutual inductance increases or the gate capacitance decreases, so that the speed performance is drastically improved.

FIG. 12 shows a bulk structure of the n-channel MOSFET shown in FIG. 6A. In the bulk MOSFET, an n ⁺ buried layer and a p well are formed in a p type silicon substrate, and an MO is formed in the p well.
The back gate regions of the SFETs M1 and M2 are formed.

FIGS. 13A to 13D are graphs showing the experimental results of this embodiment, and FIGS. 13A and 13B show the structure of a conventional MOSFET and its current characteristics, respectively. 13C and 13D respectively show the configuration of the MOSFET according to the present invention and its current characteristic.

As shown in FIGS. 13A and 13B,
Conventional n in which the gate terminal and the back gate terminal are directly connected
In the channel MOSFET Ma, the back gate potential rises in proportion to the rise of the power supply voltage VDD, and the leak current Ileak exponentially increases. On the other hand, FIG.
As shown in (C) and (D), n-channel MOSF
In the circuit of the present invention in which the gate terminal and the back gate terminal of ET · Ma are connected via the low threshold n-channel MOSFET · Mb for rectification in which the gate and source are commonly connected, the rectification MOSFET · Mb is used. Is reverse-biased, so that an increase in current can be prevented and an increase in leak current can be suppressed. When the power supply voltage is 1 V, the circuit configuration of the present invention can reduce this leakage current by four digits or more as compared with the conventional circuit configuration.

FIGS. 14A and 14B are circuit diagrams showing a modification of this embodiment. MOS of FIG. 14 (A)
The FET has a control terminal in addition to the gate terminal of the MOSFET of FIG. 6A, the gate electrode of the MOSFET M1 is connected to the gate terminal, and the gate of the MOSFET M2 is connected to the control terminal. By thus separating the gate terminal and the control terminal, the operating state of the MOSFET M1 can be controlled by a control signal from the outside. An example will be described later.

(Second Embodiment) FIGS. 15A and 15B are circuit diagrams of CMOS inverter circuits 122 and 121 showing a second embodiment of the present invention. FIG.
(A) is a p-channel type low threshold voltage MOSFET
・ M5 is a load transistor, and n shown in FIG.
A CMOS inverter circuit 122 using the channel type MOSFET circuit 112 as a driving transistor is shown. Further, FIG. 15B shows a CMOS inverter circuit 121 in which the p-channel MOSFET circuit 111 shown in FIG. 6B is used as a load transistor and the n-channel MOSFET M6 having a constant threshold voltage is used as a drive transistor. Is shown.

FIGS. 16A and 16B show an example of development of the second embodiment. FIG. 16A shows a 2-input NOR circuit 123 and FIG. 16B shows a 2-input NAND circuit. 3 shows a circuit 124. FIG. 16A shows a low threshold voltage p-channel MOSFET M7 and M.
8 is connected in series as a load transistor,
The n-channel MOSFET circuit 112 shown in FIG.
2-input NO as a drive transistor by connecting two in parallel
The R circuit 123 is shown. In addition, in FIG. 16B, low threshold voltage p-channel MOSFETs M9 and M10 are connected in parallel to form a load transistor.
The n-channel MOSFET circuit 112 shown in FIG.
Two-input NA with two drive transistors connected in series
The ND circuit 124 is shown.

In the second embodiment described above, FIG. 6 (A)
N-channel MOSFET circuit 112 shown in FIG. 6 and p-channel MOSFET circuit 111 shown in FIG.
Since a power supply of VDD> 0.8V is used,
The OSFETs M1 and M2 can be variably biased to realize a variable threshold voltage, and low power consumption can be realized even in a high power supply voltage region.

Note that, in FIGS. 15A to 16B, the low threshold voltage MOSFETs M5 to M10 are used.
Can be replaced with a high threshold voltage MOSFET.

(Third Embodiment) FIGS. 17 and 18
FIGS. 6A and 6B are diagrams showing a circuit of a third embodiment according to the present invention configured by using only the MOSFET circuits 111 and 112 shown in FIGS. 6A and 6B. FIG. 17 shows an n-channel MOSFET circuit 112.
Is a drive transistor and the p-channel MOSFET circuit 111 is a load transistor. FIG. 18A shows a p-channel type MOS.
Two-input NOR circuit 13 in which two FET circuits 111 are connected in series as load transistors and two n-channel MOSFET circuits 112 are connected in parallel as drive transistors
2 is shown. In addition, FIG. 18B shows a p-channel type MOS.
Two-input NAND circuit 1 in which two FET circuits 111 are connected in parallel as load transistors and two n-channel MOSFET circuits 112 are connected in series as drive transistors
33 is shown. These 2-input NOR circuits 132 and N
The AND circuit 133 has the same structure as that shown in FIGS.
MOS of NOR circuit 123 and NAND circuit 124
The FETs M7 and M8 and M9 and M10 are replaced with a p-channel type MOS circuit 111.

Also in the third embodiment, as in the second embodiment, even if the power source VDD> 0.8V, the MOSF is used.
A variable threshold voltage can be realized by changing ET to a variable bias, and low power consumption can be realized even in a high power supply voltage region. As described above, in the configurations of FIGS. 15A to 18B, a high-speed and low-power-consumption CMOS is used over a wide power supply voltage range.
A logic circuit can be realized.

(Fourth Embodiment) FIGS. 19A and 19B are views showing a fourth embodiment of the present invention, which are the CMOS inverter circuit 122 shown in FIG. The CMOS inverter circuits 121 shown in FIG. 15B are alternately connected in four stages to form buffer circuits 141 and 142. The difference between FIGS. 19A and 19B is that
The difference is whether the final stage is the CMOS inverter circuit 121 or 122.

The above-mentioned inverter circuit 1 of FIG. 15 (A)
22, the input voltage Vin is at the “H” level and the output voltage V
MOS with low threshold voltage when out is at “L” level
The FET M5 is off, the inverter circuit 1 of FIG.
21, the input voltage Vin is at the “L” level and the output voltage V
MOS with low threshold voltage when out is at "H" level
FET M6 is turned off. These low threshold voltages M
When the OSFETs M5 and M6 are turned off, the resistance value is not sufficiently high, and the leak current increases.

On the other hand, in the CMOS inverter circuit 122 shown in FIG. 15A, when the input voltage Vin is at the "L" level and the output voltage Vout is at the "H" level, the n-channel MOSFET circuit 112 is turned off. In the CMO inverter circuit 111 shown in (B), the p-channel MOSFET circuit 111 is turned off when the input voltage Vin is at “H” level and the output voltage Vout is at “L” level.
Since the off resistance values of these circuits 112 and 111 are sufficiently large, the leak current becomes small.

From the above, in the buffer circuit 141 of FIG. 19A, the leak currents of all the gate circuits are small when the input / output terminals are at the "H" level, and at this time the quiescent current is small as a whole. In the case of "L" level, on the contrary, the quiescent current increases. Conversely, FIG. 19 (B)
In the buffer circuit 142, the leakage currents of all the gate circuits are small when the input / output terminals are at the “L” level, and at this time, the quiescent current becomes small as a whole, and the “H” level is obtained.
At the level, the opposite causes the quiescent current to increase.

Thus, the buffer circuits 141 and 1
In 42, the current during sleep due to the leak current of the device can be reduced in a specific logic state of the two values. The above is an example of a simple circuit, and there can be many variations. For example, a buffer circuit in which the circuits 121 and 122 illustrated in FIGS. 15A and 15B are alternately connected in four or more even stages, an inverter circuit in which odd circuits are connected, and the like are given.

(Fifth Embodiment) FIGS. 20 and 21.
(A) And (B) is a circuit diagram which shows 5th Embodiment. First, FIG. 20 illustrates the low potential side power supply control circuit 5 by replacing the high potential side power supply control circuit 4 of the CMOS logic circuit described in FIG. 2 with the p-channel type MOSFET circuit 111 shown in FIG. 6B. N-channel MOS shown in 6 (A)
The CMOS logic circuit 151 is replaced with the FET circuit 112.

In this CMOS logic circuit 151, the same operation as in FIG. 2 is performed until the power supply voltage VDD is 0.8 V (more precisely, the forward voltage Vf of the diode D3). Power supply voltage V
When DD exceeds 0.8 V, the MOSFET circuit 112,
High threshold voltage MOSFETs M1, M3 in 111
MOSFET whose back gate voltage is low threshold voltage
Since it is clamped by M2 and M4, the gate current does not increase, and the threshold voltage during operation is lowered to achieve low impedance, which does not hinder high-speed operation. That is, the merit of the circuit shown in FIG. 2 can be received over a wide power supply voltage range.

In the CMOS logic circuit 151 shown in FIG. 20, the power supply control circuits on both the high potential side and the low potential side are shown in FIG.
(A) and (B) MOSFET circuits 112, 111
However, as shown in the CMOS logic circuit 152 of FIG. 21A, the p-channel MOSFET is provided only on the high potential side.
The circuit 111 is connected, and as shown in the CMOS logic circuit 153 in FIG. 21B, the n-channel MOSFET circuit 112 is connected only to the low potential side and the power supply terminal on the side not connected to the power supply control circuit is the power supply VDD. Alternatively, it is obvious that substantially the same operational effect can be obtained even if the structure is connected to the ground.

(Sixth Embodiment) FIG. 22A to FIG.
(C) is a circuit showing a sixth embodiment of the present invention.
22A shows the CMOS logic circuit 15 shown in FIG.
The buffer circuit 141 shown in FIG. 19A is connected to the input terminal of the SL signal of No. 1 and the input terminal of the * SL signal is shown in FIG.
The buffer circuit 142 shown in (B) is connected. 22B, the buffer circuit 141 shown in FIG. 19A is connected to the SL signal input terminal of the CMOS logic circuit 152 shown in FIG. 21A, and FIG.
The buffer circuit 142 shown in FIG. 19B is connected to the * SL signal input terminal of the CMOS logic circuit 153 shown in FIG.

In the circuits of FIGS. 22A to 22C, S
When the L signal is at the “H” level and the * SL signal is at the “L” level, that is, when the low threshold voltage CMOS logic circuit group 3 is in the standby (sleep) state, the quiescent current of the buffer circuits 141 and 142 becomes small.

As described above, when the CMOS logic circuit group 3 having a low threshold voltage is in a standby state, the quiescent current of these circuits is small, which is effective in reducing power consumption. Especially,
When the ratio of the standby time to the operation time is large, it is effective in reducing the power consumption of the entire circuit.
The circuits shown in FIGS. 22 (A) to 22 (C) have a great advantage that a high speed operation and low power consumption at the same time can be satisfied with a wide range of power supply voltage from 1 V or less to 3 to 5 V. is there.

With the configurations shown in FIGS. 20 to 22C, a multi-threshold CMOS logic circuit of high speed and low power consumption can be realized over a wide power supply voltage range. Especially in FIG.
With the configurations (A) to (C), the leakage current in the standby state is small, so the power consumption in the standby state is reduced, and it is useful when the standby state is longer than the operating state.

20, FIG. 21 (A), (B) and FIG.
It is also possible to configure the circuits (A) to (C) with SOI type MOSFETs and make the body portions of a large number of low threshold MOSFETs constituting the CMOS logic circuit 3 in a floating state. This eliminates the need for back gate terminals. In the SOI structure MOSFET, the back gate terminal must be taken out for each MOSFET, and the back gate terminal requires a certain area as shown in FIG. 9, so that the chip area required for the back gate terminal as a whole circuit. Cannot be ignored. For this reason, when the back gate terminal is not required, the chip area can be greatly reduced and high integration can be achieved. NMOSFET (PMOSFET) with body part floating
Then, holes (electrons) flow from the drain to the body portion, and the potential of the body portion rises (decreases). Therefore, the threshold voltage is lowered, and the MOSFET of the CMOS logic circuit is
It is possible to reduce the voltage.

(Seventh Embodiment) FIG. 23 is a circuit diagram of a MOSFET circuit according to a seventh embodiment of the present invention. Reference numeral 201 is a first control input terminal to which the control signal C is input, 202 is a second control input terminal to which a control signal * C which is complementary to the control signal C is input, and 203 is a CMOS
Reference numeral 204 denotes a signal input terminal and 205 denotes a signal output terminal.

Here, the p-channel MOSFET M3 that constitutes the load transistor of the internal CMOS circuit 203 is used.
All back gate terminals 1 to M3n are connected to a first control input terminal 201 via a p-channel MOSFET M1 (first rectifying element) in which a gate and a source are commonly connected.
Connected to Similarly, the CMOS inverter group 203
N-channel MOSFET forming a drive transistor
・ N-channel MOSFET with all gate terminals of M41 to M4n commonly connected to the gate and source
2 (second rectifying element) through the second control terminal 20
Connected to 2.

In the p-channel MOSFET M1 in which the gate and the source are commonly connected, a forward current flows in the direction of drain → gate / source, so that the drain terminal functions as an anode and the gate / source terminal functions as a cathode. . The forward voltage Vf of this diode is the threshold voltage of the MOSFET M1.

In the n-channel MOSFET M2 in which the gate and the source are commonly connected, a forward current flows in the direction of gate-source → drain, so that the gate-source terminal functions as an anode and the drain terminal functions as a diode. . The forward voltage Vf of this diode is the threshold voltage of the MOSFET M2.

Next, the operation will be described. First, when the control signal C applied to the first control input terminal 201 is a low level voltage, a p-channel MOSFET M as a rectifying element is used.
Although 1 is reverse-biased, its leakage current acts as a kind of constant voltage diode, and the internal CMOS circuit 20
Since the back gate voltage of the p-channel MOSFETs M31 to M3n of No. 3 decreases, those transistors M3
The threshold voltage of 1 to M3n becomes small.

At this time, the second control input terminal 202
Since the control signal * C applied to is a high level voltage,
The n-channel MOSFET M2 as the rectifying element is also reverse-biased, but the leak current thereof functions as a kind of constant voltage diode, and the back gate voltage of the n-channel MOSFETs M41 to M4n forming the internal CMOS circuit 203 rises. And those transistors M41-
The threshold voltage of M4n also becomes smaller.

When the threshold voltage becomes small as described above, it becomes possible to operate at high speed even with a constant power supply voltage near the original threshold voltage of the MOSFET.

At this time, in each transistor, the back gate terminal and the source terminal are forward biased to generate a short-circuit current path.
Since 1 and M2 are reverse biased, it is the leakage current that flows and the short circuit current is blocked. In particular, compared with the conventional example, the current is remarkably reduced for a power supply voltage of Vf (0.8 V) or more of the diode D3.

Since the leak current flowing through the rectifying transistors M1 and M2 is small, the p-channel MO
A large decrease in the back gate potential of the SFETs M31 to M3n and a large increase in the back gate potential of the n-channel MOSFETs M41 to M4n are prevented.

Next, when the control signal C at the control input terminal 201 is a high level voltage and the control signal * C at the control input terminal 202 is a low level voltage, the rectifying MOSFET M1, M1.
M2 is forward biased and p-channel MOSFET
The back gate terminals of M31 to M3n are at high potential, and the back gate terminals of the n-channel MOSFETs M41 to M4n are at low potential. However, those MOSFET M3
The sources of 1 to M3n and M41 to M4n and the back gate have the same potential, so that the threshold voltage does not decrease and the short circuit current does not occur.

From the above, as shown in FIG. 24, when the control signal C is set to the low level voltage and the control signal * C is set to the high level voltage, the threshold voltage of each transistor changes to the low threshold voltage. Therefore, when this mode is set as an operation mode, a low power supply voltage can be used, and at the same time, high speed operation is possible. Conversely, when the control signal C is set to a high level voltage and the control signal * C is set to a low level voltage, each transistor becomes the original high threshold voltage. In this mode, the leak current flowing between the source and drain of each transistor is reduced, and low power consumption can be achieved.

In the MOSFET circuit of FIG. 23, the rectifying p-channel MOSFET M1 is an internal CM.
P channel MOSFETs M31 to M of the OS circuit 203
Commonly used for 3n and n-channel MOSF for rectification
ET · M2 is an n-channel MO of the internal CMOS circuit 203
Although it is commonly used for the SFETs M41 to M4n, even if a rectifying MOSFET is connected to each MOSFET of the internal CMOS circuit 203, the internal CMOS circuit 2 is also used.
Rectifying MOSFET for each of the plurality of 03
May be connected.

In the MOSFET circuit of FIG. 23, the p-channel MOSFET.
M31 to M3n and n-channel MOSFET M41 to M
The rectifying MOSFETs are connected to the back gate terminals of the MOSFETs of both 4n channels, but the rectifying MOSFETs are connected only to the back gate terminals of the MOSFETs of one channel, and the MOSFETs of the other channel are connected.
A fixed voltage may be applied to the back gate terminal of T (a ground potential is applied to the back gate terminal of the p-channel MOSFET and a power supply voltage is applied to the back gate terminal of the n-channel MOSFET) or it may be floating. In these cases, complementary signals are not required as control signals.

Further, in the MOSFET circuit of FIG.
The internal CMOS circuit 203 is constituted by connecting CMOS inverters in a chain of n stages.
03 is not limited to a circuit configured only with such a CMOS inverter.

(Eighth Embodiment) FIG. 25 is a circuit diagram of a MOSFET circuit showing an eighth embodiment of the present invention. Here, the MO that constitutes the internal CMOS circuit 203.
P of threshold voltage (low threshold voltage) smaller than the threshold voltage of SFET M31 to M3n, M41 to M4n
Channel MOSFET / M5, n-channel MOSFET
-M6 is used as a rectifying transistor, and its gate and source are connected together. For example, the internal CMOS circuit 2
03-M31-M3n, M41
-When the threshold voltage of M4n is set to 0.6V, the threshold voltage of the rectifying MOSFETs M5 and M6 is set to 0.2V.
And

As described above, the rectification MOSFET M
Use of low threshold voltage transistors as M5 and M6 has an advantage that a desired leak current can be realized in a small area. This is because the low threshold voltage MOSFET originally has a large leak current.

(Ninth Embodiment) FIG. 26 is a circuit diagram of a MOSFET circuit according to a ninth embodiment of the present invention. This is because the internal CMOS circuit 203 is connected to the p-channel M
OSFET M31, M32, n-channel MOSFET
-A two-stage inverter composed of M41 and M42, p-channel MOSFET-M33, n-channel MO
A latch circuit 206 is formed by loop-connecting a transfer gate composed of SFET M43. Then, the p-channel MOSFET of this latch circuit 206
・ MOS for rectifying the back gate terminals of M31 to M33
Connect to the first control terminal 201 via FET M5,
The back gate terminals of the n-channel MOSFETs M41 to M43 are connected to the second control terminal 202 via the rectifying MOSFET M6.

In the MOSFET circuit shown in FIG. 26,
P-channel MOSFET forming a transfer gate
Since the threshold voltage of M33 and n-channel MOSFET M43 when conducting is smaller than that when shutting off, the on-resistance of the transfer gate can be reduced, so that a low power supply near the original threshold voltage. A reliable memory operation can be performed even with a voltage.

(Tenth Embodiment) FIG. 27 is a circuit diagram of a MOSFET circuit showing a tenth embodiment of the present invention. This is because the internal CMOS circuit 203 has p-channel MOSFETs M71 and M72 and n-channel MOSFE.
The memory cell 207 is composed of T.M81 and M82 and n-channel MOSFETs M91 and M92 as transfer gates. Then, among them, n-channel MOSFETs M81, M82, M91, M92
The back gate terminal of the control word line 209 is connected to the control word line 209,
It is connected to the word line 208 via the TM10. 210 is a bit line and 211 is an inverted bit line.

Due to this structure, the n-channel MOSFET of the memory cell 207 selected by the word line 208 is selected.
, The equivalent resistance of the MOSFET can be reduced, and the read operation and the write operation of the memory cell 207 can be reliably performed even at a low power supply voltage at which the on-resistance of the MOSFET rises. .

In the structure of FIG. 27, the memory cell 20
N-channel MOSFET M for the transfer gate of 7
Although 91 and M92 are used, when a p-channel MOSFET is used for the transfer gate, word line 2
08 and the back gate terminal of the p-channel MOSFET may be connected via a rectifying MOSFET. It is also possible to use complementary control word lines, in which case the contents are similar to those shown in FIGS. 23 and 25.

FIG. 28 shows a leak current Ile flowing between the back gate and the source of the MOSFET when a forward bias is applied between the back gate terminal and the source terminal of the MOSFET.
It is a figure showing the reduction effect of ak. As is clear from the figure, in the present invention, the leak current Ileak is significantly improved.

The circuit configuration described above is effective when formed on an SOI (Silicon On Insulator) type substrate as described above. Since the back gate region of the MOSFET formed on the SOI type substrate is independent, the potential of the back gate terminal can be freely set, which is effective.

[0119]

As described above, according to the present invention,
Since the back gate terminal of the MOSFET in the internal CMOS circuit is connected to the control terminal via the second MOSFET (rectifying element), the back gate region and the source region of the transistor are controlled by the control signal applied to the control terminal. When and are forward biased, the rectifying element is reverse biased.

Therefore, when the rectifying element is reverse biased by the control signal applied to the back gate terminal, the leakage current flowing therethrough forward biases the MOSFET to reduce its threshold voltage and drive it. Since the capability is improved, a low power supply voltage can be used and a high speed operation is possible, and this state is suitable as an operation mode. At this time, since the current flowing through the back gate is limited by the rectifying element, the current does not increase sharply even if the power supply voltage becomes higher than the forward voltage Vf of the back gate region and the source region.

On the contrary, when the rectifying element is forward biased by the control signal applied to the back gate terminal,
The threshold voltage does not decrease because the current flowing therethrough reverse biases the MOSFET.
The leakage current can be reduced and the power consumption can be reduced. This state is suitable for the sleep mode.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a conventional CMOS logic circuit.

2 is a development of the CMOS logic circuit shown in FIG.
It is a circuit diagram which shows the structural example of the conventional CMOS logic circuit.

3A and 3B are circuit diagrams illustrating the operation of the n-channel MOSFET M14 shown in FIG. 2, and FIG. 3A is a single circuit diagram of the MOSFET M14;
(B) is an equivalent circuit diagram.

FIG. 4 is a circuit diagram of a conventional CMOS inverter.

5 is a circuit diagram showing a configuration in which the inverters of FIG. 4 are cascade-connected in three stages.

6 (A) and (B) are MOSFs according to the invention.
FIG. 1 is a circuit diagram showing a first embodiment of ET, (A) is an n-channel type MOSFET, and (B) is a p-channel type MOSFET.
T is shown.

7A to 7D are operation explanatory diagrams of the n-channel MOSFET 112 shown in FIG. 6A.

FIG. 8 is a graph for explaining a back gate voltage clamping operation in the n-channel MOSFET 112.

9A and 9B are diagrams showing a structure of a p-channel MOSFET 111 having an SOI structure, and FIG.
9B is a top view, and FIG. 9B is a sectional view taken along the line AA of FIG. 9A.

FIG. 10 is a graph showing the relationship between the carrier density of the body of the n-channel MOSFET 112 and the threshold voltage.

FIG. 11A is a low threshold voltage SOI of Example 1;
A schematic cross-sectional view for explaining the depletion layer width W of the body portion of the MOSFET, (B) is a high threshold voltage S of the first embodiment.
FIG. 6 is a schematic cross-sectional view for explaining a depletion layer width W of a body portion of an OI MOSFET.

12A and 12B are diagrams showing a structure of a p-channel MOSFET 111 having a bulk structure,
(A) is a top view and (B) is a sectional view taken along the line AA of (A).

13A to 13D are MOSFETs of the first embodiment.
6 is a circuit diagram and a graph showing the characteristics of FIG.

14A and 14B are circuit diagrams showing a modification of the first embodiment.

15A and 15B are circuit diagrams showing a CMOS inverter according to a second embodiment of the present invention, FIG.
Shows an inverter using the MOSFET of the first embodiment as a drive transistor, and (B) shows M of the first embodiment.
An inverter using an OSFET as a load transistor is shown.

16A and 16B are block diagrams showing a modification of the second embodiment of the present invention, where FIG. 16A shows a NOR circuit and FIG. 16B shows a NAND circuit.

FIG. 17 is a circuit diagram showing a CMOS inverter according to a third embodiment of the present invention.

18A and 18B are block diagrams showing a CMOS logic circuit according to a third embodiment of the present invention,
(A) shows a NOR circuit and (B) shows a NAND circuit.

19A and 19B are circuit diagrams showing a buffer circuit according to a fourth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a CMOS logic circuit according to a fifth embodiment of the present invention.

21A and 21B are circuit diagrams showing a configuration of a modified example of the fifth embodiment.

22A to 22C are block diagrams showing a CMOS logic circuit according to a sixth embodiment of the present invention.

FIG. 23 is a circuit diagram showing a CMOS logic circuit according to a seventh embodiment of the present invention.

FIG. 24 is an explanatory diagram of operation modes of the CMOS logic circuit according to the seventh embodiment.

FIG. 25 is a circuit diagram of a CMOS logic circuit according to an eighth embodiment of the present invention.

FIG. 26 is a circuit diagram of a CMOS logic circuit according to a ninth embodiment of the present invention.

FIG. 27 is a circuit diagram of a CMOS logic circuit according to a tenth embodiment of the present invention.

FIG. 28 is a graph showing a leakage current reduction effect in the tenth embodiment.

[Explanation of symbols]

 1 High-potential power supply line 2 Low-potential power supply line 3 CMOS logic circuit 4 High-potential-side power supply control circuit 5 Low-potential-side power supply control circuit 21 Drain 22 Source 23 Gate 24 Body part 25 Back gate terminal 26 Source 27 Drain 28 Gate 29 Body part 30 wiring 31 silicon substrate 32 buried oxide film 33 contact hole 41 high potential pseudo power supply line 51 low potential pseudo power supply line 111 p-channel MOSFET circuit 112 n-channel MOSFET circuit 121 CMOS inverter 122 CMOS inverter 123 NOR circuit 124 NAND circuit 131 CMOS Inverter 132 NOR circuit 133 NAND circuit 141 Buffer circuit 142 Buffer circuit 151 CMOS logic circuit 152 CMOS logic circuit 153 CMOS logic circuit 201 Control Input terminal 202 Control input terminal 203 Internal CMOS circuit 204 Signal input terminal 205 Signal output terminal 206 Latch circuit 207 Memory cell 208 Word line 209 Control word 210 Bit line 211 Inverted bit line M1 to M4 MOSFET M11 to M14 MOSFET M31 to M33 MOSFET M41 ~ M43 MOSFET

Claims (31)

[Claims] 1. A first MO having a first threshold voltage.
An SFET and a second MOSFET having a second threshold voltage equal to or lower than the first threshold voltage, the gate electrode and the first main current electrode of which are the back gate of the first MOSFET. A second MOSFET connected to the electrode and having a second main current electrode connected to a signal supplied from the outside. 2. The MOSFET circuit according to claim 1, wherein the first main current electrode is a source electrode, and the second main current electrode is a drain electrode. 3. The MOSFET circuit according to claim 1, wherein a gate electrode of the first MOSFET and a second main current electrode of the second MOSFET are connected to each other. 4. The MOSFET circuit according to claim 1, wherein the second threshold voltage is lower than the first threshold voltage. 5. The MOSFET circuit according to claim 1, wherein the second threshold voltage is equal to the first threshold voltage. 6. In a CMOS logic circuit having a load transistor and a drive transistor connected in series,
One of the drive transistor and the load transistor includes a first MOSFET circuit,
The FET circuit is a first MOSFET having a first threshold voltage, the first MOSFET being connected in series with the other one of the drive transistor and the load transistor, and the first threshold voltage. A low second threshold voltage, the gate electrode and the first main current electrode of which are connected to the back gate electrode of the first MOSFET, and the second main current electrode of the first MOSFET. And a second MOSFET connected to the gate electrode. 7. The CMOS logic circuit according to claim 6, wherein the other one of the drive transistor and the load transistor is a MOSFET, and the CMOS logic circuit is C.
A CMOS logic circuit characterized by being a MOS inverter. 8. The CMOS logic circuit according to claim 6, wherein the load transistors are M in series (M
Is an integer greater than 1), and the drive transistor is connected in parallel to the M first MOSs.
A CMOS logic circuit having an FET circuit, wherein the CMOS logic circuit is a NOR circuit. 9. The CMOS logic circuit according to claim 6, wherein the load transistor has M (M is an integer larger than 1) MOSFETs connected in parallel, and the drive transistor is connected in series. The CMOS logic circuit has M first MOSFET circuits, and
A CMOS logic circuit characterized by being an AND circuit. 10. The CMOS logic circuit according to claim 6, wherein the other one of the drive transistor and the load transistor has a second MOSFET circuit.
The ET circuit is a third MOSFET having a third threshold voltage, and a third MOSFET connected in series with the first MOSFET circuit.
And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the MOSFET being the back of the third MOSFET. A fourth MO connected to the gate electrode and a second main current electrode connected to the gate electrode of the third MOSFET.
A CMOS logic circuit comprising an SFET. 11. The C logic circuit according to claim 10 is a CMOS inverter.
MOS logic circuit. 12. The CMOS logic circuit according to claim 10, wherein the drive transistors are M connected in parallel.
Wherein the load transistor includes M second MOSFET circuits connected in series, and the CMOS logic circuit is a NOR circuit. CMOS logic circuit. 13. The CMOS logic circuit according to claim 10, wherein the drive transistors are connected in series.
Characterized in that the load transistor includes M second MOSFET circuits connected in parallel, and the CMOS logic circuit is a NAND circuit. And a CMOS logic circuit. 14. First CMOSs alternately connected in cascade
In a buffer circuit having an inverter and a second CMOS inverter, the load transistor of the first CMOS inverter is a first MOSFET having a first threshold voltage and drives the first CMOS inverter. A first MOSFET connected in series with the transistor, and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first main current electrode Is connected to the back gate electrode of the first MOSFET, and the second main current electrode is connected to the gate electrode of the first MOSFET.
An OSFET, the drive transistor of the second CMOS inverter is a third MOSFET having a third threshold voltage, and the drive transistor of the third CMOS inverter is connected in series with the load transistor of the second CMOS inverter. And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the third MOSFET of A fourth M connected to the back gate electrode and a second main current electrode connected to the gate electrode of the third MOSFET.
A buffer circuit comprising an OSFET. 15. A low threshold CMOS logic circuit including a MOSFET having a threshold voltage lower than a first threshold voltage, and a power supply terminal and a power supply of the low threshold CMOS logic circuit. A CMOS logic circuit having at least one switch circuit connected thereto, wherein the switch circuit is a first MOSFET having the first threshold voltage, the power supply and the low threshold CMOS logic circuit. A first MOSFET connected to the power supply end of the second MOSFET and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the second MOSFET having a second threshold voltage lower than the first threshold voltage. One main current electrode is connected to the back gate electrode of the first MOSFET, and a second main current electrode is connected to the gate electrode of the first MOSFET.
A CMOS logic circuit comprising an OSFET. 16. The CMOS logic circuit according to claim 15, wherein the switch circuit is connected between a high potential terminal of the power supply and a high potential power supply terminal of the low threshold CMOS logic circuit. CMOS logic circuit characterized by: 17. The CMOS logic circuit according to claim 15, wherein the switch circuit is connected between a low potential terminal of the power supply and a low potential power supply terminal of the low threshold CMOS logic circuit. CMOS logic circuit characterized by: 18. The CMOS logic circuit according to claim 16, wherein the switch circuit is further connected between a low potential terminal of the power supply and a low potential power supply terminal of the low threshold CMOS logic circuit. CMOS characterized by
Logic circuit. 19. The CMOS logic circuit according to claim 15, wherein the CMOS logic circuit is switched to a sleep state or an operating state by a sleep signal from the outside, and is connected to a non-inverting sleep signal input terminal of the CMOS logic circuit. 1
And a second buffer connected to the inverted sleep signal input terminal, wherein the first buffers are alternately cascaded first C's.
A load transistor of the first CMOS inverter is a first MOSFET having the first threshold voltage, and a load transistor of the first CMOS inverter; A first MOSFET connected in series with the transistor, and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first main current electrode Is connected to the back gate electrode of the first MOSFET, and the second main current electrode is connected to the gate electrode of the first MOSFET.
An OSFET, the drive transistor of the second CMOS inverter is a third MOSFET having a third threshold voltage, and the drive transistor of the third CMOS inverter is connected in series with the load transistor of the second CMOS inverter. And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the third MOSFET being the back of the third MOSFET. A fourth MO connected to the gate electrode and a second main current electrode connected to the gate electrode of the third MOSFET.
SFET and the second buffer are alternately connected in cascade.
3. A CMOS logic circuit comprising: the CMOS inverter and the first CMOS inverter. 20. The CMOS logic circuit according to claim 15, wherein the CMOS logic circuit is switched to a sleep state or an operating state in response to a sleep signal from the outside, and a buffer connected to a non-inverting sleep signal input terminal thereof. Further comprising: the buffers are first CMOSs that are alternately connected in cascade.
An inverter and a second CMOS inverter, wherein the load transistor of the first CMOS inverter is a first MOSFET having the first threshold voltage and is a drive transistor of the first CMOS inverter. A first MOSFET connected in series with a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first main current electrode of which are , A second M connected to the back gate electrode of the first MOSFET and a second main current electrode connected to the gate electrode of the first MOSFET.
An OSFET, the drive transistor of the second CMOS inverter is a third MOSFET having a third threshold voltage, and the drive transistor of the third CMOS inverter is connected in series with the load transistor of the second CMOS inverter. And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the third MOSFET of A fourth M connected to the back gate electrode and a second main current electrode connected to the gate electrode of the third MOSFET.
A CMOS logic circuit comprising an OSFET. 21. The CMOS logic circuit according to claim 15, wherein the CMOS logic circuit is switched to a sleep state or an operation state by a sleep signal from the outside, and a buffer connected to an inverted sleep signal input terminal of the CMOS logic circuit. Further comprising: the buffers are first CMOSs that are alternately connected in cascade.
An inverter and a second CMOS inverter, wherein the drive transistor of the first CMOS inverter is a first MOSFET having a first threshold voltage and the load transistor of the first CMOS inverter. A first MOSFET connected in series and a second MOSFET having a second threshold voltage lower than the first threshold voltage, the gate electrode and the first main current electrode of which are A second M connected to the back gate electrode of the first MOSFET and a second main current electrode connected to the gate electrode of the first MOSFET.
OSFET, the load transistor of the second CMOS inverter is a third MOSFET having a third threshold voltage, and the load transistor of the third CMOS inverter is connected in series with the drive transistor of the second CMOS inverter. And a fourth MOSFET having a fourth threshold voltage lower than the third threshold voltage, the gate electrode and the first main current electrode of the third MOSFET of A fourth M connected to the back gate electrode and a second main current electrode connected to the gate electrode of the third MOSFET.
A CMOS logic circuit comprising an OSFET. 22. An internal CMOS including M (M is an integer of 1 or more) sets of drive transistors and load transistors, and switching the operating state in response to a control signal from the outside.
A first MOSFET commonly connected to a logic circuit and a first MOSFET circuit forming one of the drive transistor and the load transistor, wherein a gate electrode and a first main current electrode are the first MOSFET. CMOS logic, comprising: a first MOSFET of the same channel type as the first MOSFET circuit, connected to a back gate electrode of the circuit, and a second main current electrode connected to the control signal. circuit. 23. The CMOS logic circuit according to claim 22, further comprising a second MOSFET that is commonly connected to a second MOSFET circuit that constitutes the other of the drive transistor and the load transistor, and has a gate electrode. And a first main current electrode connected to the back gate electrode of the second MOSFET circuit, and a second main current electrode connected to the inverted signal of the control signal.
A CMOS logic circuit comprising a second MOSFET of the same channel type as the ET circuit. 24. The CMOS logic circuit according to claim 23, wherein the threshold voltages of the first and second MOSFETs are included in the internal CMOS logic circuit.
C characterized by being smaller than the threshold voltage of the FET
MOS logic circuit. 25. The internal CMOS of claim 22.
A CMOS logic circuit, wherein the logic circuit includes one or more CMOS inverters. 26. The internal CMOS of claim 22.
The logic circuit is a CMOS logic circuit including a transfer gate. 27. The internal CMOS of claim 22.
A logic circuit includes a memory cell, and the control signal is a word line signal. A CMOS logic circuit. 28. The CMOS logic circuit according to claim 22, wherein the control signal is a sleep signal for switching the internal CMOS logic circuit to a sleep state or an operating state. 29. Each MOSFET of the CMOS logic circuit according to any one of claims 1 to 28 is an SOI (Sem
(iconductor on insulator) formed on the substrate
A CMOS logic circuit characterized by being T. 30. The CMOS logic circuit according to claim 29, wherein the impurity concentration of the body of the low threshold MOSFET is adjusted so that the body of the low threshold MOSFET is completely depleted. . 31. The CMOS logic circuit according to claim 29, wherein the impurity concentration of the body of the high threshold MOSFET is adjusted so that the body of the high threshold MOSFET is partially depleted. .