JP2013080878A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of adjusting the voltage of a back gate when a MOS transistor connected as a power switch between a power line and a functional circuit is turned on with a simple structure is provided.
And A pair of power supply lines 2 and 3, the function circuit _4a 0 to 4A _n and a switching circuit 6a which is connected between at least one and the functional circuit _4a 0 to 4A _n of a pair of power supply lines 2 and 3 _{0 ~6a n,} and a _7a 0 _{~7a n,} the switching circuit _{6a 0 ~6a n, 7a 0 ~7a} n is one of the source / drain is connected to the functional circuit _4a 0 to 4A _n, the other is the A first MOS transistor 11 connected to one of the pair of power supply lines 2 and 3, resistance elements 12 and 21 connecting the gate and back gate of the first MOS transistor 11, and the gate of the first MOS transistor 11 And a gate voltage control circuit 13 connected to.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device.

  In a semiconductor device, a functional block or a functional circuit including a logic circuit is connected to a pair of power supply lines for supplying power. Further, a structure is known in which the source and drain of a PMOS transistor are connected as a power switch between the power line and the functional circuit. The power switch has a function of interrupting the electrical connection between the power line and the functional circuit and stopping the power supply to the functional circuit in the standby mode. In this case, it is known that the gate and back gate of the PMOS transistor are controlled by a common control circuit.

  As a power switch, a circuit in which a plurality of MOS transistors are connected in parallel is known. In this case, by selecting a plurality of MOS transistors, at least one of the electrical resistances between the power supply line and the functional circuit and between the ground line and the functional circuit is changed during operation of the functional circuit. Thereby, the value of the voltage applied to the functional circuit can be adjusted.

JP 2008-85571 A JP 2010-80807 A

  As described above, the MOS transistor connected between the functional circuit and the power supply line or between the functional circuit and the ground line has a complicated structure because the gate and the back gate are controlled by a common control circuit. Further, according to the structure in which a plurality of MOS transistors are connected in parallel between the functional circuit and the power supply line, the resistance between the source and the drain of the MOS transistor is reduced, so that the leakage current at the time of off tends to increase.

  An object of the present invention is to provide a semiconductor device capable of adjusting a back gate voltage when a MOS transistor connected as a power switch between a power line and a functional circuit is turned on with a simple structure.

According to one aspect of the present embodiment, the power supply circuit includes a pair of power supply lines, a functional circuit, and a switching circuit connected between at least one of the pair of power supply lines and the functional circuit. A first MOS transistor in which one of the source / drain is connected to the functional circuit and the other is connected to one of the power supply lines, and a resistance element connecting the gate and the back gate of the first MOS transistor, And a gate voltage control circuit connected to the gate of the first MOS transistor.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

According to this embodiment, in the MOS transistor in which the source / drain is connected between the functional circuit and the power supply line, the resistance element is connected between the gate and the back gate. Therefore, M
When the OS transistor is turned on, the threshold voltage can be optimized by adjusting the back gate voltage using a resistance element. In addition, when the transistor is turned off, the leak current can be reduced by lowering the back gate potential of the MOS transistor.

FIG. 1 is a circuit diagram illustrating a semiconductor device according to the embodiment. FIG. 2 is a circuit diagram illustrating a switching circuit connected between the functional circuit and the power supply line in the semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram illustrating a switching circuit connected between the functional circuit and the power supply line in the semiconductor device according to the second embodiment. FIG. 4 is a circuit diagram illustrating a switching circuit connected between the functional circuit and the power supply line in the semiconductor device according to the third embodiment. FIG. 5 is a circuit diagram illustrating a switching circuit connected between the functional circuit and the power supply line in the semiconductor device according to the fourth embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
FIG. 1 is a circuit diagram illustrating a part of a semiconductor device according to the embodiment. FIG. 2 is a circuit diagram illustrating a switching circuit connected between a functional circuit and a power supply line in the semiconductor device.
In Figure 1, the semiconductor device 1 includes a high voltage line 2 to high-level voltage V _DD of the power supply voltage is supplied, and a low voltage line 3 a low-level voltage V _SS of the power supply voltage is supplied . The high voltage line 2 and the voltage line 3 are a pair of power supply lines. The low level voltage includes, for example, a ground potential.

A plurality of functional circuits 4 a _{0 to} 4 a _n (n = 0, 1, 2,...), For example, logic circuits, are electrically connected between the high voltage line 2 and the low voltage line 3. Between the functional circuit _4a 1 to 4A respective high voltage supply ports 5a and the high-voltage line of the _n 2 the high voltage side switching circuit _6a 0 _{~6a n} are electrically connected. Further, between the functional circuit _4a 0 to 4A _n low voltage supply ports 5b and the low-voltage line 3 of the low voltage side switching circuit _7a 0 _{~7a n} are electrically connected.

High voltage side switching circuit _6a 0 _{~6a n,} the low voltage side switching circuit _7a 0 _{~7a n} is a power supply domain 8 illustrated in FIG. 2, respectively a control signal generating circuit 9. Power supply domain 8 has a plurality of units _8a 0 _{~8a n.}

Here, p-type MOS transistor is formed as a MOS transistor in the power supply domain 8 in the high voltage side switching circuit _6a 0 _{~6a n.} Further, n-type MOS transistor is formed as a MOS transistor in the power supply domain 8 in the low voltage side switching circuit _7a 0 _{~7a n.} In the following description, it is described as an example low voltage side switching circuit 7a ₀ ~7a _n in the power supply domain 8 and the control signal generating circuit 9.

A plurality of units _8a 0 _{~8a n} is the same structure in the power supply domain 8 have respective control MOS transistor 11. The gate of the control MOS transistor 11 is connected to its own back gate via a back gate (BG) control MOS transistor 12 used as a variable resistance element. The gate of the control MOS transistor 11 is also connected to the output terminal of the gate voltage control circuit 13. The gate voltage control circuit 13 is formed from, for example, a CMOS that connects the drains of a p-type MOS transistor and an n-type MOS transistor.

  One of the source / drain of the BG control MOS transistor 12 is connected to the gate of the control MOS transistor 11, and the other is connected to the back gate of the control MOS transistor 11. Further, the gate of the BG control MOS transistor 12 is connected to the first voltage output terminal 9 a of the control signal generation circuit 9.

If control MOS transistor 11 is an n-type MOS transistor, its source electrode connected to the low voltage line 3 and the drain electrode is connected to the low voltage supply ports 5b of the functional circuit _4a 0 to 4A _n.

  The control signal generation circuit 9 has an encoder 14 and a voltage generator 15. The encoder 14 monitors a chip state in a certain period based on outputs from the temperature monitor circuit 16 and the frequency monitor circuit 17, encodes a state identification signal that is an output thereof, and outputs the encoded signal to the voltage generator 15. The output of the encoder 14 is a signal for controlling the output signal AEN0 of the potential generation circuit 15.

  The encoder 14 is connected to a first control line PGEN for transmitting a control signal from a power supply control circuit (not shown). When a high (H) level signal is input from the first control line PGEN, the encoder 14 outputs an analog signal according to the data signal output from the temperature monitor circuit 16 and the frequency monitor circuit 17. Further, when a low (L) level signal is input from the first control line PGEN, the encoder 14 outputs an L level signal regardless of the outputs of the temperature monitor circuit 16 and the frequency monitor circuit 17.

  A second control line AEN from a power supply control circuit (not shown) is connected to the voltage generation circuit 15, and the second control line AEN outputs a predetermined signal from the voltage generation circuit 15 regardless of the output from the encoder 14. .

For example, a diode thermometer is used as the temperature monitor circuit 16. Further, a circuit having a voltage controlled oscillator VCO and a resistor V _osc is used as the frequency monitor circuit 17, and for example, a frequency position indicating whether the frequency of the oscillation clock is within a predetermined frequency range or higher or lower is output as a data signal.

  Based on the data signal input from the encoder 14, the voltage generator 15 outputs an analog output signal AEN0 to the gate of the GB control MOS transistor 12 via the first output port 9a, and further outputs the second output port 9b. The control signal ENn (n = 0, 1, 2,...) Is output to the gate voltage control circuit 13 through the gate voltage control circuit 13. For example, a charge pump circuit is used as the potential generating circuit 15.

As described above, the functional circuit _4a 0 to 4A _n and the power supply voltage applied to the functional circuit _4a 0 to 4A _n by the low-pressure side operation of the switching circuit _7a 0 _{~7a n} interposed between the low-voltage line 3 Table 1 It is controlled as shown in the truth table.

  In Table 1, PG indicates control of the power supply domain 8 based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17.

  PG off means that the power supply domain 8 is controlled without depending on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, the first control line PGEN is forcibly set to the L level to hold the output of the encoder 14 at the L level, and the second control line AEN is set to the L level to supply the first output port from the voltage generator 15. The output voltage to 9a and the second output port 9b is set to H level.

Accordingly, the voltage output from all of the voltage selection circuit 13 controlled by a signal from the second output port 9b becomes H level, the plurality of units 8a ₀ ~8a _n control MOS transistor in the power supply domain 8 11 is turned on. At the same time, the signal voltage of the H level is applied has been turned on to the gates of all the units _8a 0 BG controlling MOS transistor 12 in ~8a _n.

Thus, the functional circuit 4a ₀ to 4A _n and the low voltage line 3 are electrically connected via a control MOS transistor 11, the voltage applied to the back gate of the control MOS transistor 11 is out of the setting range The maximum value of. In this case, the threshold voltage of the control MOS transistor 11 is lowered and the resistance between the source and the drain is lowered as compared with the case where an H level voltage is not applied to the back gate.

  In addition, as a case where the output of the encoder 14 is forcibly set to the L level by the signal voltage transmitted from the first control line PGEN, for example, there is a failure in the temperature monitor circuit 16 and the frequency monitor circuit 17. The failure is judged by another test circuit, and a signal voltage corresponding to the failure is transmitted to the first control line PGEN.

  In Table 1, PG-on means that the power supply domain 8 can be controlled based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, the signal voltage transmitted through the first control line PGEN is set to H level, and the output of the encoder 14 variably controls the output signal AEN0 of the voltage generation circuit 15 according to the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. It can be so. In this case, whether or not the output of the voltage generation circuit 15 is controlled by the output from the encoder 14 further depends on a signal transmitted through the second control line AEN.

When the second control line AEN is at the L level, the output of the voltage generation circuit 15 is not controlled by the signal from the encoder 14. On this case, by setting the output from the voltage generating circuit 15 to the first output port 9a H level voltage and without, the gate of the BG controlling MOS transistor 12 of all units _8a 0 _{~8a n} to H level State.

At the same time, the second output port 9b a voltage selection circuit 13 in the unit 8a ₀ ~8a _n through, voltage is applied that is set in advance. For example, based on the table stored in the voltage generating circuit 15 transmits an H level signal to the voltage selection circuit 13 of the specified unit of the units 8a ₀ ~8a _n, other the voltage selection circuit 13 An L level signal is transmitted.

As a result, the control MOS transistor 11 to which the on-voltage is applied from the voltage selection circuit 13 by the H level signal is turned on. Thus, the unit _8a 0 _{~8a n} having control MOS transistor 11 in the ON state, a function circuit _4a 0 to 4A _n and the low voltage line 3 via the control MOS transistor 11 are electrically connected. Only the H level signal is transmitted from the voltage selection circuit 13 via the BG control MOS transistor 12 to the back gate of the control MOS transistor 11 which is turned on, and the threshold voltage of the control MOS transistor 11 is set low. .

Further, an off voltage is applied to the gate of the control MOS transistor 11 from the voltage selection circuit 13 to which other L level voltage is applied. In unit _8a 0 _{~8a n} having control MOS transistor 11 is turned off condition, the functional circuit _4a 0 to 4A _n and the low voltage line 3 is electrically disconnected.

On the other hand, when the second control line AEN is at the H level, the voltage output from the voltage generation circuit 15 to the second output port 9b changes in an analog manner according to the signal output from the encoder 14, and BG The voltage is applied to the gate of the control MOS transistor 12. At the same time, sends a signal of H level to the voltage selection circuit 13 in a predetermined unit unit 8a ₀ ~8a _n previously set in the voltage generating circuit 15, the level of the signal to other voltage selection circuits 13 Send.

Thus, in the selected units _8a in 0 ~8a _n control MOS transistor 11 is turned on by the voltage selection circuit 13, thereby the function circuit _4a 0 to 4A _n and the low voltage line 3 is electrically connected. Also, the unit _8a in 1 ~8a _n having control MOS transistor 11 which is turned off to block the function circuit _4a 0 to 4A _n and the low voltage line 3 electrically.

An analog voltage corresponding to the voltage level from the voltage generation circuit 15 applied to the gate of the BG control MOS transistor 12 is applied to the back gate of the control MOS transistor 11 that is turned on. That is, as the voltage level applied from the voltage generation circuit 15 to the gate of the BG control MOS transistor 12 increases, the on-resistance value between the source and the drain decreases, so the voltage of the back gate of the control MOS transistor 11 increases. Thus, the threshold voltage of the control MOS transistor 11 is reduced. When the threshold voltage of the control MOS transistor 11 is decreased, the ON resistance between the source and the drain of controlling MOS transistor 11 decreases, the potential difference between the low voltage dedicated 3 function circuit 4a ₀ to 4A _n decreases.

Meanwhile, as shown in Table 2, in the state of the PG off by the second control line AEN to the H level, the control MOS transistor 11 of the unit _8a in 1 ~8a _n selected by the voltage generating circuit 15 The other control MOS transistor 11 may be turned off.

According to this embodiment as described above, connect one source / drain of controlling MOS transistor 11 to the functional circuit 4a ₀ to 4A _n, it connects the other to the low-voltage line 3. Further, the source / drain of the BG control MOS transistor 12 is connected as a variable resistance element between the gate of the control MOS transistor 11 and its back gate. The voltage applied to the gate of the BG control MOS transistor 12 is set so that it can be adjusted depending on the detected values of the temperature sensor circuit 16 and the frequency sensor circuit 17 via the encoder 14 and the voltage supply circuit 15. .

  For this reason, when the control MOS transistor 11 is turned off (standby), no voltage is applied to the back gate, so that the leakage current is caused by the crystallinity and impurity concentration of the channel region between the source and drain of the control MOS transistor 11. , Distance, conductance, etc.

  As an element structure for reducing the leakage current of the control MOS transistor 11 at the off time, for example, the gate length may be increased by adjusting the gap between the source region and the drain region of the element. Alternatively, a structure may be adopted in which the impurity concentration in the channel region is lowered to enhance the operation more than usual. The same applies to the following embodiments.

When the control MOS transistor 11 is on (during driving), a voltage having the same polarity as that of the gate is applied to the back gate via the BG control MOS transistor 12. As a result, the resistance between the source and drain of the control MOS transistor 11 is lowered, and the threshold voltage is lowered. As a result, the source-drain current of the control MOS transistor 11 is increased, it is possible to reduce the resistance due to the low voltage side switching circuit _7a 0 _{~7a n,} the function circuit _4a 0 to 4A _n and the low voltage line 3 The bias voltage generated between them can be lowered.

Further, the back gate voltage of the control MOS transistor 11 is controlled by adjusting the voltage applied to the gate of the BG control MOS transistor 12, so that the temperature of the semiconductor device 1 and the change in the clock frequency are changed. Adjusted. Thus, to stabilize the change in the internal constant of the semiconductor device 1 by suppressing the change in the voltage between the functional circuit 4a ₀ to 4A _n and the low voltage line 3 during driving, for example, the clock frequency can be stabilized .

Incidentally, a control applied to a plurality of units _8a 0 _{~8a n} of the high-voltage side switching circuit _6a in 1 ~6a _n power supply domain 8 which is interposed between the high voltage line 2 and the functional circuit _4a 1 to 4A _n The MOS transistor 11 and the BG control MOS transistor 12 are p-type MOS transistors. The source of a control MOS transistor 11 p-type MOS transistor is connected to the high voltage line 2, also, the drain is connected to the high voltage supply ports 5a of the functional circuit _4a 1 _{~4a n.} Further, a circuit that generates a back gate voltage using a regulator from an input / output power supply instead of a charge pump is used as the voltage generation circuit 15.

(Second Embodiment)
FIG. 3 is a circuit diagram illustrating a portion where a switching circuit is connected between a functional circuit and a power supply line in the semiconductor device according to the second embodiment. 3, the same reference numerals as those in FIGS. 1 and 2 denote the same elements.

In the present embodiment, as shown in FIG. 1, a plurality of functional circuits 4 a _{0 to} 4 a _n , for example, logic circuits, are electrically connected between the high voltage line 2 and the low voltage line 3. Between the functional circuit _4a 0 to 4A each of the high voltage supply ports 5a and the high-voltage line of the _n 2 the high voltage side switching circuit _6a 0 _{~6a n} are electrically connected. Further, between the functional circuit _4a 0 to 4A _n low voltage supply ports 5b and the low-voltage line 3 of the low voltage side switching circuit _7a 0 _{~7a n} are electrically connected.

High voltage side switching circuit _6a 0 _{~6a n,} the low voltage side switching circuit _7a 0 _{~7a n,} as in the first embodiment, each have a control signal generating circuit 9 and the power supply domain 8. Power supply domain 8 has a plurality of units _8a 0 _{~8a n.}

Unit _8a 0 _{~8a n} is control MOS transistor 11, and a gate voltage control circuit 13 and a variable resistor 21 and resistor selection circuit 22. The gate of the control MOS transistor 11 is connected to the output terminal of the gate voltage control circuit 13 as in the first embodiment. The variable resistor 21 has a structure in which the resistance elements R _{0 to} R _n selected by the resistance selection circuit 22 are connected between the gate and the back gate of the control MOS transistor 11.

  As in the first embodiment, the control signal generation circuit 9 is connected to the temperature sensor circuit 16 and the frequency sensor circuit 17, and these data are input to the encoder 14. The encoder 14 has a structure in which detection data of the temperature sensor circuit 16 and the frequency sensor circuit 17 are encoded and output to the first and second output ports 9a and 9b as voltage signals.

A control signal EN _n having a magnitude corresponding to input signals from the temperature sensor circuit 16 and the frequency sensor circuit 17 is input from the encoder 14 to the first output port 9a, and the output signal EN _n is a unit signal as a control signal. The voltage is applied to the gate voltage control circuit 13 in 8a _{0 to} 8a _n .
The second output port 9b has a selection signal SEL _m (m = 0, 1, 2) determined by a combination of the detection signal from the temperature sensor circuit 16 and the frequency sensor circuit 17 and the voltage of the first control line PGEN. ...) is input from the encoder 14.

One input portion of the gate voltage control circuit 13 is connected to the low voltage line 3, and the other input portion is connected to the high voltage line 2a (V _DD ). In addition, the gate voltage control circuit 13 determines either the voltage V _SS of the low voltage line 3 or the voltage V _DD of the first output port 9a according to the control signals EN _{0 to} EN _n from the second output port 9b. Is applied to the gate of the control MOS transistor 11.

As described above, the functional circuit _4a 0 to 4A _n and the voltage applied to the functional circuit _4a 0 to 4A _n by the low-pressure side operation of the switching circuit _7a 0 _{~7a n} interposed between the low-voltage line 3 in Table 3 It is controlled as in the illustrated truth table.

  In Table 1, PG indicates control of the power supply domain 8 based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17.

PG off means that the power supply domain 8 is controlled without depending on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, by setting the control line PGEN to L level to retain from the encoder 14 to the control signal EN _n to the gate voltage control circuit 13 to the H level. At the same time, the control signal SELm of the resistance selection circuit 22 is set to L level from the encoder 14, and the variable resistance 21 is set to the lowest resistance value _R0 .

As a result, the voltages output from all the voltage selection circuits 13 controlled by the signal from the second output port 9 b become the V _DD on-voltage, and the plurality of units 8 a _{0 to} 8 a in all the power supply domains 8. _{The n} control MOS transistor 11 is turned on.

Accordingly, the functional circuit 4a ₀ to 4A _n and the low voltage line 3 is electrically connected via a control MOS transistor 11, the voltage applied to the back gate of the control MOS transistor 11 is out of the setting range The maximum value of. In this case, the threshold voltage of the control MOS transistor 11 is lowered and the resistance between the source and the drain is lowered as compared with the case where an H level voltage is not applied to the back gate.

In Table 3, “PG ON” means that the power supply domain 8 can be controlled based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, the first control line PGEN is set to the H level, and the output of the encoder 14 can encode the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17 to make the output from the encoder 14 variable. Thus, in each unit _8a 0 _{~8a n,} it is ready to select a resistance value of the resistor selection circuit 22 in accordance with the value of the voltage SEL _m output from the encoder 14. As a result, the back gate voltage of the control MOS transistor 11 varies depending on the resistance value of the resistance selection circuit 22.

Further, the output voltage ENn from the encoder 14, the second output port 9b a voltage selection circuit 13 in the unit _8a 0 _{~8a n} through, voltage is applied that it is set in advance. For example, based on the table stored in the voltage generating circuit 15 transmits an H level signal to the voltage selection circuit 13 of the specified unit of the units 8a ₀ ~8a _n, other the voltage selection circuit 13 An L level signal is transmitted.

As a result, the control MOS transistor 11 to which the H level voltage is applied from the voltage selection circuit 13 is turned on. Thus, the unit _8a 0 _{~8a n} having control MOS transistor 11 in the ON state, a function circuit _4a 0 to 4A _n and the low voltage line 3 via the control MOS transistor 11 are electrically connected. Only the H level signal is transmitted from the voltage generation circuit 15 to the back gate of the control MOS transistor 11 which is turned on, and the threshold voltage is set low.

Further, an off voltage is applied to the gate of the control MOS transistor 11 from the voltage selection circuit 13 to which other L level voltage is applied. In unit _8a 0 _{~8a n} having control MOS transistor 11 is turned off condition, the functional circuit _4a 0 to 4A _n and the low voltage line 3 is electrically disconnected.

Thus, in the selected units _8a in 0 ~8a _n control MOS transistor 11 is turned on by the voltage selection circuit 13, the function circuit _4a 0 to 4A _n and the low voltage line 3 is electrically connected.

  A voltage adjusted according to the resistance value selected by the resistance selection circuit 22 is applied to the back gate of the control MOS transistor 11 that is turned on. When the resistance is high, the back gate voltage is low, and when the resistance is low, the back gate voltage is high. The higher the back gate voltage, the lower the threshold voltage of the control MOS transistor 11 and the lower the source-drain resistance.

According to this embodiment as described above, connect one source / drain of controlling MOS transistor 11 to the functional circuit 4a ₀ to 4A _n, it connects the other to the low voltage line 3. Further, a variable resistor 21 whose resistance can be adjusted by a resistance selection circuit 22 is connected as a variable resistance element between the gate of the control MOS transistor 11 and its back gate.

For this reason, when the control MOS transistor 11 is turned off (standby), no voltage is applied to the back gate, so that the leakage current is caused by the crystallinity and impurity concentration of the channel region between the source and drain of the control MOS transistor 11. , Distance, conductance, etc.

Further, when the control MOS transistor 11 is turned on (during driving), a voltage having the same polarity as that of the gate is applied to the back gate via the variable resistor 21. As a result, the resistance between the source and drain of the control MOS transistor 11 is lowered, and the threshold voltage is lowered. As a result, the source-drain current of the control MOS transistor 11 is increased, it is possible to reduce the resistance due to the low voltage side switching circuit _7a 0 _{~7a n,} the function circuit _4a 0 to 4A _n and the low voltage line 3 The bias voltage generated between them can be lowered.

The back gate voltage of the control MOS transistor 11 is controlled by adjusting the variable resistor 21 by the resistance selection circuit 22 based on a control signal that depends on the outputs of the temperature sensor circuit 16 and the frequency sensor circuit 17. Therefore, in accordance with a change in status of the temperature and the clock frequency of the semiconductor device 1, the internal constants by suppressing the change in the voltage between the functional circuit 4a ₀ to 4A _n and the low voltage line 3 during driving semiconductor device 1 For example, the clock frequency can be stabilized.

Incidentally, a control applied to a plurality of units _8a 0 _{~8a n} of the high-voltage side switching circuit _6a in 1 ~6a _n power supply domain 8 which is interposed between the high voltage line 2 and the functional circuit _4a 1 to 4A _n The MOS transistor 11 is a p-type MOS transistor. As source of the p-type MOS transistor is connected to the high voltage line 2, also, the drain is connected to the high voltage supply ports 5a of the functional circuit _4a 1 _{~4a n.} Further, a circuit that generates a back gate voltage using a regulator from an input / output power supply instead of a charge pump is used as the voltage generation circuit 15.

(Third embodiment)
FIG. 4 is a circuit diagram illustrating a portion where a switching circuit is connected between a functional circuit and a power supply line in the semiconductor device according to the third embodiment. 4, the same reference numerals as those in FIGS. 1 and 2 denote the same elements.

In the present embodiment, as shown in FIG. 1, a plurality of functional circuits 4 a _{0 to} 4 a _n , for example, logic circuits, are electrically connected between the high voltage line 2 and the low voltage line 3. Between the functional circuit _4a 1 to 4A respective high voltage supply ports 5a and the high-voltage line of the _n 2 the high voltage side switching circuit _6a 0 _{~6a n} are electrically connected. Further, between the functional circuit _4a 0 to 4A _n low voltage supply ports 5b and the low-voltage line 3 of the low voltage side switching circuit _7a 0 _{~7a n} are electrically connected.

High voltage side switching circuit _6a 0 _{~6a n,} the low voltage side switching circuit _7a 0 _{~7a n,} as in the first embodiment, each have a control signal generating circuit 9 and the power supply domain 8. Power supply domain 8 has a plurality of units _8a 0 _{~8a n.}

Unit _8a 0 _{~8a n,} as in the first embodiment, controlling MOS transistors 11, BG controlling MOS transistor 12 has a gate voltage control circuit 13. The gate of the control MOS transistor 11 is connected to the output terminal of the gate voltage control circuit 13 as in the first embodiment. One of the two sources / drains of the BG control MOS transistor 12 is connected to the gate of the control MOS transistor 11, and the other is connected to the back gate. The gate of the BG control MOS transistor 12 is connected to the back gate of the control MOS transistor 11 and is substantially a constant resistance element.

The control signal generation circuit 9 includes a temperature sensor circuit 16 and a frequency sensor circuit 17 as in the first embodiment, and these data are output to the input unit of the encoder 14. The voltage generation circuit 15 that receives a signal from the encoder 14 outputs a signal having a magnitude corresponding to the input signal from the encoder 14 to the first output port 9a. Further, the voltage generating circuit 15, by the combination of the output of the second control line AEN and encoder 14, a second output port 9b some predetermined through or all of the units _8a 0 _{~8a n} to H level voltage Or L level signal is output.

Control signal input of the gate voltage control circuit 13 of the unit 8a in _{0 ~8a n} is connected to the second output port 9b, the gate ON voltage of the control MOS transistor 11 by the control signal from the second output port 9b Or off voltage is output. A first input portion of the gate voltage control circuit 13 is connected to the low voltage line 3, and a second input portion is connected to the first output port 9a. The gate voltage control circuit 13 applies either the voltage V _SS of the low voltage line 3 or the voltage SEL _m of the first output port 9 a to the gate of the control MOS transistor 11 in accordance with the control signal EN _n .

As described above, the functional circuit _4a 0 to 4A _n and the voltage applied to the functional circuit _4a 0 to 4A _n by the low-pressure side operation of the switching circuit _7a 0 _{~7a n} interposed between the low-voltage line 3 in Table 1 It is controlled like a truth table similar to the one shown.

  PG off means that the power supply domain 8 is controlled without depending on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, the first control line PGEN is set to the L level to hold the output of the encoder 14 at the L level, and the second control line AEN is set to the L level to connect the first output port 9a to the first output port 9a. 2 Both output voltages to the output port 9b are set to H level.

Thus, the voltage output from all of the voltage selection circuit 13 controlled by a signal from the second output port 9b becomes H level, control of a plurality of units 8a ₀ ~8a _n of all power in the supply domain 8 The MOS transistor 11 is turned on.

Therefore, BG control function circuit _4a 0 to 4A _n and the low voltage line 3 is electrically connected via a control MOS transistor 11, a constant resistance between the gate and the back gate of the control MOS transistor 11 The source / drain of the MOS transistor 12 is connected. In this case, the threshold voltage of the control MOS transistor 11 is lowered and the resistance between the source and the drain is lowered as compared with the case where an H level voltage is not applied to the back gate.

  In Table 1, PG-on means that the power supply domain 8 can be controlled based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. In this case, whether or not the output of the voltage generation circuit 15 is controlled by the output from the encoder 14 further depends on the signal of the second control line AEN.

When the second control line AEN is at the L level, the output from the voltage generation circuit 15 is not controlled by the signal from the encoder 14. In this case, the output from the voltage generating circuit 15 to the first output port 9a becomes highest H-level voltage, the ON voltage of the gate voltage control circuit 13 of all units 8a in _{0 ~8a n} is the highest H level Become.

At the same time, the control voltage set in advance to the gate voltage control circuit 13 of the unit 8a in _{0 ~8a n} via the second output port 9b is applied. For example, based on the table stored in the voltage generating circuit 15, to the unit 8a ₀ ~8a the voltage selection circuit 13 of the specified unit of _n transmits a control signal of H level, other voltage selection circuits 13 Transmits an L level control signal.

As a result, the control MOS transistor 11 to which the on-voltage is applied from the voltage selection circuit 13 by the H level signal is turned on. Thus, the unit _8a 0 _{~8a n} having control MOS transistor 11 in the ON state, a function circuit _4a 0 to 4A _n and the low voltage line 3 via the control MOS transistor 11 are electrically connected. A predetermined voltage is applied to the back gate of the control MOS transistor 11 that is turned on, and the threshold voltage is set lower than when no voltage is applied to the back gate.

Further, an off voltage is applied to the gate of the control MOS transistor 11 from the voltage selection circuit 13 to which other L level voltage is applied. In unit _8a 0 _{~8a n} having control MOS transistor 11 is turned off condition, the functional circuit _4a 0 to 4A _n and the low voltage line 3 is cut off electrically.

On the other hand, when the second control line AEN is at the H level, the voltage output from the voltage generation circuit 15 to the second output port 9 b changes in an analog manner according to the signal output from the encoder 14. Then, it transmits a signal magnitude to the voltage selection circuit 13 in a predetermined unit unit 8a ₀ ~8a _n previously set in the voltage generating circuit 15 varies. Further, an L level signal is transmitted to the other voltage selection circuit 13.

Thus, in the selected units _8a in 0 ~8a _n control MOS transistor 11 is turned on by the voltage selection circuit 13, thereby the function circuit _4a 0 to 4A _n and the low voltage line 3 is electrically connected. In this case, the current between the source and the drain of the control MOS transistor 11 changes according to the magnitude of the gate voltage, that is, the analog voltage input from the first output port 9a. For example, since the voltage inputted to the gate of the control MOS transistor 11 becomes larger source-drain current in the case of the maximum in the control range, the resistance between the functional circuit 4a ₀ to 4A _n and the low voltage line 3 The lowest.
In the unit _8a in 1 ~8a _n having control MOS transistor 11 which is turned off to block the function circuit _4a 0 to 4A _n and the low voltage line 3 electrically.

According to this embodiment as described above, connect one source / drain of controlling MOS transistor 11 to the functional circuit 4a ₀ to 4A _n, it connects the other to the low-voltage line 3. Further, the source / drain of the BG control MOS transistor 12 is connected as a constant resistance element between the gate of the control MOS transistor 11 and its back gate. The voltage applied to the gate of the BG control MOS transistor 12 is set so that it can be adjusted depending on the detected values of the temperature sensor circuit 16 and the frequency sensor circuit 17 via the encoder 14 and the voltage supply circuit 15. .

  For this reason, when the control MOS transistor 11 is turned off (standby), no voltage is applied to the back gate, so that the leakage current is caused by the crystallinity and impurity concentration of the channel region between the source and drain of the control MOS transistor 11. , Distance, conductance, etc.

When the control MOS transistor 11 is on (during driving), a voltage having the same polarity as that of the gate is applied to the back gate via the BG control MOS transistor 12. As a result, the resistance between the source and the drain of the control MOS transistor 11 becomes lower and the threshold voltage becomes lower than when a back gate voltage having the same polarity as the gate voltage is not applied. As a result, the source-drain current of the control MOS transistor 11 is increased, it is possible to reduce the resistance due to the low voltage side switching circuit _7a 0 _{~7a n,} the function circuit _4a 0 to 4A _n and the low voltage line 3 The bias voltage generated between them can be lowered.

Further, since the gate voltage of the control MOS transistor 11 is controlled by adjusting the output voltage of the voltage supply circuit 15, it is adjusted according to changes in the temperature of the semiconductor device 1 and the state of the clock frequency. Thus, to stabilize the change in the internal constant of the semiconductor device 1 by suppressing the change in the voltage between the functional circuit 4a ₀ to 4A _n and the low voltage line 3 during driving, for example, the clock frequency can be stabilized .

Incidentally, a control applied to a plurality of units _8a 0 _{~8a n} of the high-voltage side switching circuit _6a in 1 ~6a _n power supply domain 8 which is interposed between the high voltage line 2 and the functional circuit _4a 1 to 4A _n The MOS transistor 11 is a p-type MOS transistor. As source of the p-type MOS transistor is connected to the high voltage line 2, also, the drain is connected to the high voltage supply ports 5a of the functional circuit _4a 1 _{~4a n.} Further, a circuit that generates a back gate voltage using a regulator from an input / output power supply instead of a charge pump is used as the voltage generation circuit 15. Note that the gate voltage of the p-type MOS transistor is, for example, −V _DD .

(Fourth embodiment)
FIG. 5 is a circuit diagram illustrating a portion where a switching circuit is connected between a functional circuit and a power supply line in the semiconductor device according to the fourth embodiment. 5, the same reference numerals as those in FIGS. 1 and 2 indicate the same elements.

In the present embodiment, as shown in FIG. 1, a plurality of functional circuits 4 a _{0 to} 4 a _n , for example, logic circuits, are electrically connected between the high voltage line 2 and the low voltage line 3. Between the functional circuit _4a 1 to 4A respective high voltage supply ports 5a and the high-voltage line of the _n 2 the high voltage side switching circuit _6a 0 _{~6a n} are electrically connected. Further, between the functional circuit _4a 0 to 4A _n low voltage supply ports 5b and the low-voltage line 3 of the low voltage side switching circuit _7a 0 _{~7a n} are electrically connected.

High voltage side switching circuit _6a 0 _{~6a n,} the low voltage side switching circuit _7a 0 _{~7a n,} as in the first embodiment, each have a control signal generating circuit 9 and the power supply domain 8. Power supply domain 8 has a plurality of units _8a 0 _{~8a n.}

Unit _8a 0 _{~8a n,} as in the first embodiment, controlling MOS transistors 11, BG controlling MOS transistor 12 has a gate voltage control circuit 13. The gate of the control MOS transistor 11 is connected to the output part of the gate voltage control circuit 13 as in the first embodiment. Further, the two sources / drains of the BG control MOS transistor 12 are connected to the gate and back gate of the control MOS transistor 11 as in the first embodiment. The gate of the BG control MOS transistor 12 is connected to the source / drain on the side connected to the back gate, and has a substantially constant resistance.

The control signal generation circuit 9 includes a temperature sensor circuit 16 and a frequency sensor circuit 17 as in the first embodiment, and these data are output to the input unit of the encoder 14. Unlike the first and third embodiments, the encoder 14 outputs an H level voltage and an L level voltage to the output port 9 b without outputting an analog voltage from the encoder 14.
The encoder 14 selects the H-level voltage or L level signal is output to the predetermined part or all of the units _8a 0 _{~8a n} by the voltage of the first control line PGEN.

Control signal input of the gate voltage control circuit 13 of the unit 8a in _{0 ~8a n} is connected to the output port 9b, a second gate ON voltage or OFF voltage of the control MOS transistor 11 by the control signal from the output port 9b One of the following is output. A first input portion of the gate voltage control circuit 13 is connected to the low voltage line 3, and a second input portion is connected to the high voltage line 2. Accordingly, either the voltage of the low voltage line 3 or the voltage V _DD is applied to the gate of the control MOS transistor 11 by the control signal input to the gate voltage control circuit 13.

As described above, the functional circuit _4a 0 to 4A _n and the voltage applied to the functional circuit _4a 0 to 4A _n by the low-pressure side operation of the switching circuit _7a 0 _{~7a n} interposed between the low-voltage line 3 and Table 4 It is controlled as shown in the truth table.

  PG off means that the power supply domain 8 is controlled without depending on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. That is, the signal voltage transmitted through the first control line PGEN is set to L level, and the output of the encoder 14 is held at L level.

Thus, the voltage output from all of the voltage selection circuit 13 controlled by a signal from the output port 9b becomes the threshold voltage or more H-level, the plurality of units 8a ₀ ~8a _n of all power in the supply domain 8 The control MOS transistor 11 is turned on.

Therefore, BG control function circuit _4a 0 to 4A _n and the low voltage line 3 is electrically connected via a control MOS transistor 11, a constant resistance between the gate and the back gate of the control MOS transistor 11 The source / drain of the MOS transistor 12 is connected. In this case, the threshold voltage of the control MOS transistor 11 is lowered and the resistance between the source and the drain is lowered as compared with the case where the H level voltage is not applied to the back gate.

In Table 4, “PG ON” means that the power supply domain 8 can be controlled based on the data output of the temperature monitor circuit 16 and the frequency monitor circuit 17. In this case, by controlling the gate voltage control circuit 13 by the output from the encoder 14, in a predetermined condition, and turns on or off the control MOS transistor 11 in the unit _8a 0 _{~8a n.}

Thus, the unit _8a 0 _{~8a n} having control MOS transistor 11 is turned on a voltage is applied to electrically connect the functional circuit _4a 0 to 4A _n and the low voltage line 3 via a control MOS transistor 11 . A predetermined voltage is applied to the back gate of the control MOS transistor 11 that is turned on, and the threshold voltage is set lower than when no voltage is applied to the back gate.

Also, the unit _8a 0 _{~8a n} having control MOS transistor 11 OFF voltage is applied, the functional circuit _4a 0 to 4A _n and the low voltage line 3 is cut off electrically.

According to this embodiment as described above, connect one source / drain of controlling MOS transistor 11 to the functional circuit 4a ₀ to 4A _n, it connects the other to the low voltage line 3. Further, the source / drain of the BG control MOS transistor 12 is connected as a constant resistance element between the gate of the control MOS transistor 11 and its back gate. The voltage applied to the gate of the BG control MOS transistor 12 is set so that it can be adjusted depending on the detected values of the temperature sensor circuit 16 and the frequency sensor circuit 17 via the encoder 14 and the voltage supply circuit 15. .

  Since no voltage is applied to the back gate when the control MOS transistor 11 is off (standby), the leakage current is caused by the crystallinity, impurity concentration, distance of the channel region between the source and drain of the control MOS transistor 11, Depends on conductance etc.

When the control MOS transistor 11 is on (during driving), a voltage having the same polarity as that of the gate is applied to the back gate via the BG control MOS transistor 12. As a result, the resistance between the source and the drain of the control MOS transistor 11 becomes lower and the threshold voltage becomes lower than when a back gate voltage having the same polarity as the gate voltage is not applied. As a result, the source-drain current of the control MOS transistor 11 is increased, it is possible to reduce the resistance due to the low voltage side switching circuit _7a 0 _{~7a n,} the function circuit _4a 0 to 4A _n and the low voltage line 3 The bias voltage generated between them can be lowered.

Incidentally, a control applied to a plurality of units _8a 0 _{~8a n} of the high-voltage side switching circuit _6a in 1 ~6a _n power supply domain 8 which is interposed between the high voltage line 2 and the functional circuit _4a 1 to 4A _n The MOS transistor 11 is a p-type MOS transistor. As source of the p-type MOS transistor is connected to the high voltage line 2, also, the drain is connected to the high voltage supply ports 5a of the functional circuit _4a 1 _{~4a n.} Further, a circuit that generates a back gate voltage using a regulator from an input / output power supply instead of a charge pump is used as the voltage generation circuit 15. Note that the gate voltage of the p-type MOS transistor is, for example, −V _DD .

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary Note 1) A pair of power supply lines, a functional circuit, and a switching circuit connected between at least one of the pair of power supply lines and the functional circuit, wherein one of the source / drain is A first MOS transistor connected to the functional circuit and the other connected to one of the power supply lines; a resistance element connecting a gate and a back gate of the first MOS transistor; and And a gate voltage control circuit connected to the gate.
(Supplementary Note 2) The resistance element is a second MOS transistor in which one of source / drain is connected to the gate of the first MOS transistor and the other is connected to the back gate of the first MOS transistor. 2. The semiconductor device according to appendix 1, wherein there is a semiconductor device. (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the gate of the second MOS transistor is connected to an output terminal of a voltage generating circuit whose output voltage is variable.
(Supplementary note 4) The semiconductor device according to supplementary note 2, wherein a gate of the second MOS transistor is connected to a back gate of the first MOS transistor.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the gate of the first MOS transistor is connected to an output terminal of a voltage generation circuit whose output voltage is variable. .
(Supplementary note 6) The semiconductor device according to Supplementary note 1, wherein the resistance element is a variable resistor electrically connected between the gate and the back gate of the first MOS transistor.
(Additional remark 7) It has a resistance selection circuit which selects the resistance value of the said variable resistance, The semiconductor device of Additional remark 6 characterized by the above-mentioned.
(Additional remark 8) The said resistance selection circuit is connected to the output terminal of the control circuit which outputs the control signal which changes the resistance value of the said variable resistance based on the detection data by a sensor, The additional description 7 characterized by the above-mentioned. Semiconductor device.
Body equipment.
(Supplementary note 9) A plurality of the first MOS transistors are formed, and either a turn-on voltage or a turn-off voltage is applied from the voltage control circuit to each gate of the first MOS transistor. A semiconductor device according to 1.

1 semiconductor device 2 high-voltage line 3 the low-voltage line _4a 0 to 4A _n functional circuit 5a High Voltage supply ports 5b low voltage supply port _{6a 0 ~6a n, 7a 0 ~7a} n switching circuit 8 power supply domains _8a 0 _{~8a n} Unit 9 Control signal generation circuit 11 Control MOS transistor 12 Back gate control MOS transistor 13 Gate voltage control circuit 14 Encoder 15 Voltage generator 16 Temperature sensor circuit 17 Frequency sensor circuit 21 Variable resistor 22 Resistance selection circuit

Claims (5)

A pair of power wires;
A functional circuit;
A switching circuit connected between at least one of the pair of power supply lines and the functional circuit;
The switching circuit is
A first MOS transistor having one source / drain connected to the functional circuit and the other connected to one of the power supply lines;
A resistance element connecting a gate and a back gate of the first MOS transistor;
A gate voltage control circuit connected to the gate of the first MOS transistor;
A semiconductor device.   The resistance element is a second MOS transistor in which one of source / drain is connected to the gate of the first MOS transistor and the other is connected to the back gate of the first MOS transistor. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 2, wherein the gate of the second MOS transistor is connected to an output terminal of a voltage generating circuit whose output voltage is variable.   The semiconductor device according to claim 2, wherein a gate of the second MOS transistor is connected to a back gate of the first MOS transistor.   The semiconductor device according to claim 1, wherein the resistance element is a variable resistance electrically connected between the gate and the back gate of the first MOS transistor.

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