JPH09120770A - Electric field emission cold cathode and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cold cathode of electric field emission type which has a high reliability and can operate with a low power by suppressing a discharge destruction without provision of any high resistance layer in the emitter. SOLUTION: A silicon base board 1 is connected with a cathode electrode, wherein no resistance layer is provided between the cathode electrode and an emitter in conical shape having a sharp tip connected with the base board 1, and therefore, a large potential drop will not occur between the emitter and cathode electrode even at the time of large current flowing, which favors a low power operation. A high resistance layer 4 is formed between a gate electrode film 6 and the board 1, which results in existence of the high resistance layer 4 on the current path in the initial period of discharging between the emitter and gate electrode film 6, i.e., the path the electric charges between the gate and cathode electrode flow to the emitter, and it is possible to suppress the amperage at the time of discharging. This prevents a current as large as causing shortcircuit between the emitter and gate from flowing at the time of discharging.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type cold cathode and a method for manufacturing the same, and more particularly to a field emission type cold cathode having an emitter whose tip is sharpened and connected to a cathode electrode, and a gate electrode surrounding the emitter, and the same. The present invention relates to a manufacturing method.

[0002]

2. Description of the Related Art A conventional field emission type cold cathode of this type is shown in FIG.
The structure shown in FIG. 1 or the structure shown in FIG. FIG.
FIG. 1 is a sectional view of a first conventional example in which a high resistance layer is provided between an emitter and a cathode electrode.
No. 6,086,045. FIG. 12 is a schematic view of JP-A-6-205.
FIG. 9 is a sectional view of a second conventional example in which a high resistance layer is provided on an emitter as disclosed in Japanese Patent Laid-Open No. 92 or Japanese Patent Laid-Open No. 5-36345. In the conventional example of FIG. 11, 1 is a silicon substrate to be a cathode electrode, 4 is a high resistance layer such as a low-concentration epitaxial growth layer, 3 and 5 are oxide films, 6 is a gate electrode film, and 9 is a sharpened emitter. Is a low resistance region.

The conventional example shown in FIG. 12 has a structure in which a high resistance layer 4 is formed under a sharpened convex portion which becomes an emitter, and a low resistance region 9 is formed over the projection.

As in the conventional example shown above, by applying a voltage between the cathode electrode having a sharp emitter and the gate electrode surrounding the emitter, a strong electric field is generated at the tip of the emitter and electrons are emitted from the tip of the emitter by field emission. Is released. Here, the high resistance layer 4 is provided to control the value of the emission current flowing by the emission of electrons from the emitter.

[0005]

All of the conventional field emission cold cathodes have a structure in which a high resistance layer is provided on a sharp cone-shaped emitter. This structure has the advantages of controlling the current and suppressing the generation of excess current during discharge. However, since the current value control is performed by utilizing the potential difference generated in the high resistance layer of the emitter section, when the current exceeding a certain level is required, the gate voltage is reduced by the amount of the voltage drop in the high resistance layer.
It was necessary to make a large potential difference between the emitter electrodes. This leads to an increase in the power of the device, which is an obstacle to lowering the power. Further, in order to control the current value flowing through the emitter with the high resistance layer, a highly accurate high resistance layer forming technique has been required. In order to avoid this increase in power, it is possible to adopt a structure in which the high resistance layer is not provided in the emitter section. However, in a structure without a resistance layer, an excessive current is generated due to discharge more than the control of the current value, which causes a phenomenon that the emitter or the gate portion is destroyed. As a result of research, it has been found that this phenomenon is triggered by the electric charge accumulated between the gate and the cathode electrode being instantaneously discharged between the emitter and the gate. In a structure without a high resistance layer, it is difficult to suppress the current value of this instantaneous discharge, so that an excessive current easily flows and breaks down in the emitter. As described above, it is difficult for the conventional structure to achieve both low power consumption and prevention of discharge breakdown.

An object of the present invention is to provide a field emission type cold cathode having high reliability and low power operation, which suppresses discharge breakdown without providing a high resistance layer on the emitter, and a manufacturing method thereof.

[0007]

The present invention employs the following means to solve the above-mentioned problems.

(1) In the field emission type cold cathode having an emitter having a sharpened tip connected to the cathode electrode and a gate electrode formed with an insulating film on the cathode electrode except the periphery of the emitter, A field emission cold cathode having a high resistance layer between a cathode electrode and a gate electrode.

(2) The field emission cold cathode according to (1), wherein the emitter is connected to the cathode electrode without the resistance layer.

(3) The field emission cold cathode according to (2), wherein the resistance layer is formed between the insulating film and the cathode electrode.

(4) The field emission cold cathode according to (2), wherein the resistance layer is formed between the insulating film and the gate electrode.

(5) The field emission cold cathode according to (2), wherein a constant current source is connected to the cathode electrode.

(6) At least a region of the cathode electrode connected to the emitter is a silicon substrate containing silicon as a main component and doped with n-type impurity atoms, and the resistance layer is formed in the silicon substrate. (3) The field emission cold cathode as described above.

(7) In the above (6), the resistance layer is n-type.
The field emission cold cathode as described.

(8) In the above (6), the resistance layer is p-type.
The field emission cold cathode as described.

(9) The field emission cold cathode according to (6), wherein the resistance layer is formed at least directly under the insulating film.

(10) The field emission cold cathode according to the above (9), wherein the resistance layer is formed at least in a region except the sharpened region of the emitter.

(11) A method of manufacturing a field emission cold cathode having an emitter connected to a cathode electrode and having a sharpened tip, and a gate electrode formed through an insulating film on the cathode electrode except at least the periphery of the emitter. At
A method of manufacturing a field emission cold cathode, comprising the step of forming a high resistance layer between the cathode electrode and a gate electrode other than a region directly under the tip of the emitter.

(12) The method for manufacturing a field emission cold cathode according to the above (11), wherein the resistance layer is formed by a vapor deposition method.

(13) The method for manufacturing a field emission cold cathode according to the above (11), wherein the resistance layer is formed by an epitaxial growth method.

(14) The method for manufacturing a field emission cold cathode according to the above (11), wherein the resistance layer is formed by an ion implantation method.

(15) The method for manufacturing a field emission cold cathode according to the above (11), wherein the resistance layer is formed by diffusing from an oxide film containing impurity atoms.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of the first embodiment of the present invention. Reference numeral 1 is a silicon substrate connected to the cathode electrode, 3 and 5 are oxide films, 4 is a high resistance layer formed on the silicon substrate, and 6 is a gate electrode film made of a metal film. Since there is no resistance layer between the conical emitter and the cathode electrode having a sharp tip connected to the silicon substrate 1 as described above, a large potential drop does not occur between the emitter and the cathode electrode even at a high current, It is advantageous for low power operation. Further, the gate electrode film 6 and the silicon substrate 1
By forming a high resistance layer 4 between the
Current path in the initial stage of discharge between the gate electrode films 6, that is, gate
Since the high resistance layer 4 exists on the path through which the charge between the cathode electrodes flows to the emitter, the current value during discharge can be suppressed. As a result, it is possible to prevent a large current from flowing into the emitter, which would cause a short circuit between the emitter and the gate during discharge.

2A to 2C and 3A and 3B.
FIG. 4A is a cross-sectional view in order of the steps of the first embodiment of the present invention.
First, as shown in FIG. 2A, for example, an oxide film 2 is formed on the surface of an n-type silicon substrate 1 having a concentration of about 10 ¹⁵ cm ⁻³ or more to a thickness of about 200 nm by a thermal oxidation method or a CVD method. To do. Next, as shown in FIG. 2B, after patterning a resist or the like (not shown) to form a mask of the oxide film 2, the oxide film 2 is patterned by an anisotropic etching method, and then the resist is removed. The silicon substrate 1 is isotropically etched using the oxide film 2 as a mask to form a convex shape as shown in the figure. Then, as shown in FIG.
Thermal oxidation is applied to oxidize the convex recon substrate 1 to sharpen the convex tip to form an emitter and an oxide film 3. When the oxide film thickness at this time is about 100 nm,
The tip width of the convex silicon substrate 1 shown in (b) is about 90 n.
It should be a value of m or less and a value that sharpens during this oxidation. Then, using the oxide film 2 as a mask, p-type impurity atoms such as boron are added to the silicon substrate 1 at a concentration not higher than the n-type impurity concentration by ion implantation. By subjecting this to heat treatment and activation, the resistance value of this p-type impurity-added region can be set higher than that of the region immediately below the emitter, and high resistance layer 4 is formed. Next, by the vapor deposition method, 40
An oxide film 5 of about 0 nm and a gate electrode film 6 of a metal film such as Mo of about 200 nm are sequentially deposited. After that, as shown in FIG. 3B, the oxide film 2 and the oxide film 3 are etched in a solution of hydrofluoric acid or the like, the laminated film deposited on the emitter is lifted off, and the gate electrode film 6 is patterned. To form a field emission cold cathode.

As described above, in the field emission type cold cathode shown in this embodiment, the impurity atom adding step for forming the high resistance layer is performed by ion implantation, and the oxide film used for forming the emitter is used as a mask at that time. ing. Therefore, it is possible to form a high resistance layer in a desired region in a self-aligned manner without the need for a step of newly forming a mask at the time of ion implantation.

In this embodiment, the method of forming the emitter by forming the silicon substrate by etching and oxidation is described, but the method is not limited to this method.
Alternatively, the silicon substrate may be sharpened by oxidation to form an emitter, or the emitter may be formed of another material.

Next, a second embodiment of the present invention will be described. 4A to 4D are sectional views in order of the processes, according to the second embodiment of the present invention. In the second embodiment, the steps up to FIG. 2B are the same as those in the first embodiment. After that, as shown in FIG. 4A, a BSG film 7 (boron silicate glass film) is deposited to a thickness of about 50 nm by a vapor deposition method or a CVD method, and heat treatment is performed so that boron atoms are deposited from the BSG film 7 into the silicon substrate 1. The high resistance layer 4 is formed by diffusion. Then, the oxide film 5 and the gate electrode film 6 are sequentially deposited by the vapor deposition method in the same process as in the first embodiment. Next, as shown in FIG. 4B, the oxide film 2, the BSG film 7, the oxide film 5 and the gate electrode film 6 on the emitter are lifted off and removed, and the gate electrode film 6 is patterned to perform field emission cooling. Form the cathode. In the second method, the high resistance layer 4 is formed in a self-aligned manner by boron diffusion from the BSG film instead of ion implantation. As a result, the formation region of the high resistance layer 4 can be formed in a self-aligned manner not only under the oxide film 5 under the gate but also around the emitter portion, so that the charge accumulated under the gate electrode film 6 can be formed in the emitter. The resistance when flowing increases.

FIG. 5 shows a plan view of this embodiment. The high resistance layer formation region is formed on the entire surface of the region other than the emitter section 10, and has a structure in which the high resistance layer 4 is arranged in the current path of the charges accumulated under the gate electrode film 6 to the emitter.

The method of forming the high resistance layer by boron diffusion from the BSG film shown in the second embodiment is not limited to the method of forming the emitter with silicon, but is also described in Journal of Applied Physics, 1976, Volume 47,
It is effective in a method of forming a metal emitter by a vapor deposition method as disclosed in page 5248. That is, by using the BSG film as the insulating film under the gate electrode film, the high resistance layer can be easily formed around the emitter in a self-aligned manner.

Next, a third embodiment of the present invention will be described. 6A to 6C and 7A to 7C are cross-sectional views in order of the processes of the third embodiment. As shown in FIG. 6A, an epi layer 8 having a concentration of about 10 ¹⁴ cm ^{-3 is formed} on the n-type silicon substrate 1 having a concentration of 10 ¹⁵ cm ^-3 or more by an epitaxial growth method to a thickness of about 4 μm. And about 20
The oxide film 2 having a thickness of 0 nm is formed by the thermal oxidation method or the CVD method. Next, as shown in FIG. 6B, after the oxide film 2 is patterned, it is etched to a depth of about 300 nm to 1000 nm by an isotropic etching method so that the epi layer 2 has a convex shape. Thereafter, as shown in FIG. 6C, the epi layer 8 is oxidized by thermal oxidation to a thickness of about 10 to 40 nm.
To form an emitter. Next, FIG. 7 (a)
As shown in FIG. 5, the oxide film 5 and the gate electrode film 6 are formed by the vapor deposition method in the same manner as in the first and second embodiments described above. Next, as shown in FIG. 7B, the laminated film on the emitter is removed by the lift method and the gate electrode film 6 is patterned. Then, as shown in FIG. 7C, about 10 ¹⁵ n-type impurity atoms are introduced into the opening of the oxide film 5 by the ion implantation method.
It is added so as to have a concentration of cm ⁻³ or more, and a low resistance region 9 which penetrates the epi layer 8 and reaches the silicon substrate 1 is formed to form a field emission cold cathode. In this method, as shown in FIG. 7C, the low concentration epi layer 8 acts as a high resistance region under the gate electrode film 6. In this embodiment, since the high resistance layer is formed of the epi layer, there is an advantage that the crystallinity of the oxide film / epi layer interface is good. Further, since the emitter section can be controlled to be a high-concentration n-type, it is possible to suppress the potential drop in the emitter section and improve the emission efficiency.

FIG. 8 shows a fourth embodiment. In this embodiment, after manufacturing in the same process as that of the third embodiment up to FIG. 7B, a mask such as a resist that exposes the vicinity of the center of the emitter is formed, and then an n-type impurity is formed by an ion implantation method. Atoms are added and activated to form a low resistance region 9 as shown. In this embodiment, the low resistance region 9 is formed immediately below the tip of the emitter, and since it becomes a high resistance layer, the epi layer 8 is formed in a region wider than immediately below the gate electrode film 6, so that the high resistance layer is introduced. The structure has a higher effect.

In the embodiments of the invention described so far,
Although the n-type low-concentration region is formed as the high-resistance layer in the description, this is not limited to the n-type region, and a p-type region can be formed in the high-resistance layer. The p-type layer can be formed by adding a p-type impurity at a concentration higher than the n-type concentration of the silicon substrate when forming the high-resistance layer by ion implantation, and a method of forming a high resistance at the epi layer. Then, it is possible by performing p-type epitaxial growth. In the case of the p-type, this region can be reduced not only as a high resistance layer but also by reducing the capacitance value between the gate electrode film and the silicon substrate (cathode electrode) by the extent of the depletion layer. This has the effect of limiting the amount of current to the emitter.

Next, a fifth embodiment of the present invention will be described. 9A to 9C and FIGS. 10A and 10B are cross-sectional views in order of the steps of the fifth embodiment of the present invention. FIG.
9A shows the oxide film 2 formed on the silicon substrate 1, and FIG. 9B shows the silicon substrate 1 etched in a convex shape after the oxide film 2 is patterned. The steps are the same as those of the embodiment described above (for example, the first embodiment). Then Figure 9
As shown in (c), 50 nm to 100 n by thermal oxidation
Oxidation of about m is performed to form the oxide film 3 while sharpening the convex shape of the silicon substrate 1. By anisotropic etching, the oxide film 2 and the oxide film 3 immediately below remain, and the other oxide film 3 is removed. The oxide film is etched as described above. next,
As shown in FIG. 10 (a), a silicon film is deposited to a thickness of, for example, about 200 nm by an evaporation method, and an n-type silicon film having a concentration of about 10 ¹⁴ cm ⁻³ to 10 ¹⁶ cm ⁻³ is formed by a method such as ion implantation. Impurity atoms are added and activated by heat treatment, and the vapor-deposited silicon film is polycrystallized to form the high resistance layer 4
To form After that, the oxide film 5 and the gate electrode film 6 are formed by the vapor deposition method. Next, as shown in FIG. 10B, the oxide film 2, the high resistance layer 4, the oxide film 5, and the gate electrode film 6 on the emitter are lifted off and removed by oxide film etching, and the oxide film 3 is removed. The gate electrode film 6 is patterned to form a field emission cold cathode.

In this embodiment, the silicon film to be the high resistance layer is formed by the vapor deposition method. However, the present invention is not limited to this method, and after the oxide film 3 is removed by the selective epitaxial growth method, the exposed silicon substrate 1 is exposed. Alternatively, a method of growing a silicon film may be used. In the selective epitaxial growth method,
Since the silicon film grows only on the silicon substrate and does not grow on the oxide film 2, there is an advantage that lift-off in a later process becomes easier.

In the present invention, the high resistance layer has a structure formed between the oxide film under the gate electrode film and the silicon substrate, but the present invention is not limited to this, and the high resistance layer is not limited to this. It is effective if it is formed between them, or if it is formed in the oxide film.

In the device of the present invention, the stability of the cathode current value, which is possible when the high resistance layer is introduced into the conventional emitter, cannot be controlled. However, this is because the active device such as a transistor is connected to the cathode electrode. This is possible by using this as a constant current source. Even in this case, since the present invention has a structure in which there is no high resistance layer between the emitter and cathode electrodes, there is no voltage drop due to the current value between the emitter and cathode, which is advantageous for the circuit design of the constant current source. There are advantages.

[0038]

As described above, the present invention has a structure in which there is no high resistance layer between the emitter and the silicon substrate which becomes the cathode electrode, and the high resistance is provided between the gate electrode film and the silicon substrate. It has a structure in which layers are formed. As a result, the structure is such that no potential drop occurs between the emitter and the silicon substrate (cathode electrode), which is advantageous for low power operation. In addition to this, a high resistance layer is formed immediately below the gate electrode film, and the high resistance layer is effectively provided between the capacitance between the gate electrode film and the silicon substrate (cathode electrode) and the emitter. As a result, when a discharge is generated between the emitter and the gate electrode, it is possible to prevent the electric charge accumulated in the capacitor serving as a current source in the initial stage of discharge from being rapidly discharged.

Further, when a p-type region is formed on the n-type silicon substrate as the high resistance layer, the depletion layer expands by this region, effectively reducing the capacitance value accumulated between the gate electrode film and the cathode electrode. However, it becomes possible to suppress the current value flowing through the emitter during discharge between the emitter and the gate electrode.

Due to the effects of the present invention as described above, when comparing the conventional element having the high resistance layer formed on the emitter with the element of the present invention, it is possible to prevent the destruction of the element due to discharge in the same manner and to obtain the threshold voltage of the conventional element. From 40V, the device of the present invention can reduce the voltage to 30V.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

2A to 2C are cross-sectional views in order of the processes, according to the first embodiment of the present invention.

3A to 3D are sectional views in order of the processes, according to the first embodiment of the present invention.

4A to 4C are cross-sectional views in order of the steps of a second embodiment of the present invention.

FIG. 5 is a plan view of the second embodiment of the present invention.

6A to 6C are sectional views in order of the processes, according to a third embodiment of the present invention.

7A to 7D are sectional views in order of the processes, according to a third embodiment of the present invention.

8A to 8D are sectional views in order of the processes, according to a fourth embodiment of the present invention.

9A to 9D are sectional views in order of the processes, according to a fifth embodiment of the present invention.

FIG. 10 is a process order cross-sectional view of a fifth embodiment of the present invention.

FIG. 11 is a sectional view of a first conventional example.

FIG. 12 is a sectional view of a second conventional example.

[Explanation of symbols]

 1 Silicon substrate 2, 3, 5 Oxide film 4 High resistance layer 6 Gate electrode film 7 BSG film 8 Epi layer 9 Low resistance region 10 Emitter part

Claims (15)

[Claims] 1. A field emission type cold cathode having an emitter having a sharpened tip connected to a cathode electrode and a gate electrode formed via an insulating film on the cathode electrode except the periphery of the emitter, wherein the cathode is a cathode. A field emission cold cathode comprising a high resistance layer between an electrode and a gate electrode. 2. The field emission cold cathode according to claim 1, wherein the emitter is connected to the cathode electrode not through the resistance layer. 3. The field emission cold cathode according to claim 2, wherein the resistance layer is formed between the insulating film and the cathode electrode. 4. The field emission cold cathode according to claim 2, wherein the resistance layer is formed between the insulating film and the gate electrode. 5. The field emission cold cathode according to claim 2, wherein a constant current source is connected to the cathode electrode. 6. At least a region of the cathode electrode connected to the emitter is a silicon substrate containing silicon as a main component and doped with n-type impurity atoms, and the resistance layer is formed in the silicon substrate. The field emission cold cathode according to claim 3. 7. The field emission cold cathode according to claim 6, wherein the resistance layer is n-type. 8. The field emission cold cathode according to claim 6, wherein the resistance layer is p-type. 9. The field emission cold cathode according to claim 6, wherein the resistance layer is formed at least directly under the insulating film. 10. The field emission cold cathode according to claim 9, wherein the resistance layer is formed at least in a region except a region near the sharpened region of the emitter. 11. A method of manufacturing a field emission cold cathode, comprising: an emitter connected to a cathode electrode and having a sharpened tip; and a gate electrode formed on at least the cathode electrode except the periphery of the emitter via an insulating film. A method of manufacturing a field emission cold cathode, comprising: forming a high resistance layer between the cathode electrode and a gate electrode other than a region immediately below the tip of the emitter. 12. The method of manufacturing a field emission type cold cathode according to claim 11, wherein the resistance layer is formed by a vapor deposition method. 13. The method of manufacturing a field emission cold cathode according to claim 11, wherein the resistance layer is formed by an epitaxial growth method. 14. The method for manufacturing a field emission cold cathode according to claim 11, wherein the resistance layer is formed by an ion implantation method. 15. The method of manufacturing a field emission cold cathode according to claim 11, wherein the resistance layer is formed by being diffused from an oxide film containing impurity atoms.