JPH09115935A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH09115935A
JPH09115935A JP7273811A JP27381195A JPH09115935A JP H09115935 A JPH09115935 A JP H09115935A JP 7273811 A JP7273811 A JP 7273811A JP 27381195 A JP27381195 A JP 27381195A JP H09115935 A JPH09115935 A JP H09115935A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
package
molding
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7273811A
Other languages
Japanese (ja)
Inventor
Yoshihiko Shimanuki
好彦 嶋貫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP7273811A priority Critical patent/JPH09115935A/en
Publication of JPH09115935A publication Critical patent/JPH09115935A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the move of a tab at the time of molding by covering the outer surface of a semiconductor chip and an electrical connection part, forming an inner fixing part for fixing these, and forming a resin package using a molding device with the inner fixing part outside. SOLUTION: An inner fixing part 15 is formed by silicone, the outer surface of a semiconductor chip 12 and a wire 14 are covered, at the same time the wire 14 and the tip portion of a lead 13 and then the tip of the lead 13 and a tab are mutually fixed. While a lower mold 31 and an upper mold 32 of a molding device 30 are subjected to mold registration, a molten resin is filled into a mold cavity 33, thus forming a package made of resin corresponding to the shape of the mold cavity 33. The wire 14 is fixed, thus preventing the wire 14 and a tab 11 from being deformed owing to the flow of resin filled into the mold cavity 33, thus manufacturing a reliable semiconductor device with improved yield.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に薄型の半導体装置の製造に適用して好適
な半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for manufacturing a thin semiconductor device.

【０００２】[0002]

【従来の技術】ＩＣやＬＳＩなどの半導体装置は、半導
体集積回路が形成された半導体ペレットつまり半導体チ
ップと、これに設けられた電極に電気的に接続される複
数本のリードと、半導体チップをリードのインナー部と
ともに封止するパッケージとを有している。2. Description of the Related Art A semiconductor device such as an IC or an LSI includes a semiconductor pellet on which a semiconductor integrated circuit is formed, that is, a semiconductor chip, a plurality of leads electrically connected to electrodes provided on the semiconductor pellet, and a semiconductor chip. And a package for sealing together with the inner portion of the lead.

【０００３】このような半導体装置を製造する際には、
複数本のリードが設けられたリードフレームのタブつま
りアイランドに半導体チップを接合し、半導体チップに
設けられた電極とリードとをワイヤにより電気的に接続
した後に、モールド装置によって樹脂製のパッケージを
成形し、パッケージによって半導体チップを封止するよ
うにしている。When manufacturing such a semiconductor device,
A semiconductor chip is joined to a tab or island of a lead frame provided with a plurality of leads, and the electrodes provided on the semiconductor chip and the leads are electrically connected by wires, and then a resin package is molded by a molding device. Then, the semiconductor chip is sealed by the package.

【０００４】モールド装置としては、たとえば、日経Ｂ
Ｐ社、１９９３年５月３１日発行の「ＶＬＳＩパッケー
ジング技術（下）」Ｐ３４〜Ｐ４０に記載されるような
トランスファーモールド装置が使用されている。As a molding device, for example, Nikkei B
A transfer mold apparatus as described in "VLSI Packaging Technology (Lower)" P34 to P40, published by Company P, May 31, 1993, is used.

【０００５】[0005]

【発明が解決しようとする課題】近年の半導体装置は、
半導体チップのみならず、パッケージ自体を薄くする要
請が強く、モールド装置を用いて厚さの薄いパッケージ
を成形すると、モールド成形時における樹脂の流れや熱
応力によってタブが変動して、ワイヤやタブが樹脂パッ
ケージの表面に露出したり、モールド用の樹脂つまりレ
ジンの未充填が発生することがある。Recently, semiconductor devices have been
There is a strong demand not only for the semiconductor chip but also for the package itself. When a thin package is molded using a molding machine, the tabs change due to the flow of resin and thermal stress during molding, and the wires and tabs It may be exposed on the surface of the resin package or may not be filled with the molding resin, that is, the resin.

【０００６】また、薄型の半導体装置を製造するため
に、半導体チップの厚みを薄くしたり、ボンディングワ
イヤのワイヤアーチの高さを低くすると、半導体チップ
を形成するための半導体ウエハの厚みを薄くすべく追加
工が発生したり、ワイヤボンディングを低いアーチで行
わなければならず、モールド時にタブが変動して製造安
定性や製品歩留りが良好とならないという問題点が発生
するおそれがある。Further, if the thickness of the semiconductor chip is reduced or the height of the wire arch of the bonding wire is reduced in order to manufacture a thin semiconductor device, the thickness of the semiconductor wafer for forming the semiconductor chip is reduced. As a result, additional machining may occur, and wire bonding may have to be performed with a low arch, and the tab may fluctuate during molding, resulting in a problem that manufacturing stability and product yield are not good.

【０００７】本発明の目的は、薄型の半導体装置であっ
ても歩留り良く製造し得るようにすることである。An object of the present invention is to enable a thin semiconductor device to be manufactured with high yield.

【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【０００９】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１０】すなわち、本発明の半導体装置の製造方法
は、半導体チップに設けられた電極に電気的接続部を介
して接続される複数のリードを有するリードフレームに
前記半導体チップを接合する接合工程と、前記半導体チ
ップの外面と前記電気的接続部とを覆いかつこれらを固
定する内側固定部を形成する固定部形成工程と、前記内
側固定部の外側にモールド装置を用いて樹脂パッケージ
を成形するモールド工程とを有することを特徴とする。That is, the method of manufacturing a semiconductor device according to the present invention comprises a joining step of joining the semiconductor chip to a lead frame having a plurality of leads connected to electrodes provided on the semiconductor chip via electrical connecting portions. A fixing part forming step of forming an inner fixing part that covers the outer surface of the semiconductor chip and the electrical connection part and fixes them, and a mold for molding a resin package on the outside of the inner fixing part using a molding device. And a process.

【００１１】本発明の半導体装置の製造方法にあって
は、樹脂製のパッケージの成形時には、ワイヤ相互など
が固定されているので、レジンの流れによってワイヤや
タブが変形することが防止される。また、パッケージを
成形する際におけるレジンの熱によって内側固定部に熱
応力が作用しても、熱応力に起因するタブの変動などの
影響を抑制することができる。また、内側固定部が設け
られた状態の多数のリードフレームストックしておくこ
とができ、需要に応じて相互にサイズの相違した半導体
装置を能率良く製造することができ、半導体装置の製造
能率が向上する。In the method of manufacturing a semiconductor device of the present invention, since the wires are fixed to each other when the resin package is molded, the wires and tabs are prevented from being deformed by the flow of the resin. Further, even if thermal stress acts on the inner fixed portion due to the heat of the resin when the package is molded, it is possible to suppress the influence such as the tab change caused by the thermal stress. Further, a large number of lead frame stocks with the inner fixing portion provided can be stocked, so that semiconductor devices of different sizes can be efficiently manufactured according to demand, and the manufacturing efficiency of the semiconductor device is improved. improves.

【００１２】[0012]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００１３】図１は本発明の半導体装置の製造方法によ
り製造された半導体装置を示す図であり、この半導体装
置はＱＦＰ(Quad Flat Package) タイプであり、アイラ
ンドとも言われるタブ１１の上には半導体ペレットつま
り半導体チップ１２が接合されており、半導体チップ１
２の４つの外周辺に向けて延びたリード１３の先端部と
半導体チップ１２に設けられた図示しない電極との間に
はワイヤ１４が接続されており、このワイヤ１４が電極
とリード１３とを電気的に接続する電気的接続部となっ
ている。FIG. 1 is a diagram showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention. This semiconductor device is of a QFP (Quad Flat Package) type, and on a tab 11 which is also called an island. The semiconductor pellet, that is, the semiconductor chip 12 is bonded to the semiconductor chip 1.
Wires 14 are connected between the tips of the leads 13 extending toward the four outer peripheries 2 and the electrodes (not shown) provided on the semiconductor chip 12. The wires 14 connect the electrodes and the leads 13. It is an electrical connection part that electrically connects.

【００１４】ワイヤ１４および半導体チップ１２の外面
は内側固定部１５により覆われるとともに、この内側固
定部１５によってワイヤ１４の相互間が埋め込まれると
ともに、リード１３の先端部とタブ１１とも相互に固定
される。この内側固定部１５の素材としては、図示する
場合にはシリコーンゴムが使用されている。The outer surfaces of the wire 14 and the semiconductor chip 12 are covered with an inner fixing portion 15, and the inner fixing portion 15 fills the space between the wires 14 with each other, and the tip portions of the leads 13 and the tab 11 are fixed to each other. It Silicon rubber is used as the material of the inner fixing portion 15 in the illustrated case.

【００１５】この内側固定部１５の外側には樹脂製のパ
ッケージ１６が成形されており、このパッケージ用の樹
脂としては、エポキシ樹脂、硬化剤、硬化促進剤および
溶融シリカなどのフィラーなどからなる熱硬化型の樹脂
が使用される。それぞれのリード１３のうち、パッケー
ジ１６により封止される部分がインナー部となり、パッ
ケージ１６から突出した部分がアウター部となる。A resin package 16 is formed on the outside of the inner fixing portion 15. The resin for this package is a heat composed of an epoxy resin, a curing agent, a curing accelerator and a filler such as fused silica. A curable resin is used. A portion of each lead 13 sealed by the package 16 serves as an inner portion, and a portion protruding from the package 16 serves as an outer portion.

【００１６】図２は図１に示す半導体装置を製造する手
順を示す図であり、図２（ａ）はリードフレーム２０の
タブ１１上に半導体チップ１２をダイボンディング工程
で接合し、さらにワイヤボンディング工程で半導体チッ
プ１２に設けられた電極とリード１３の先端部とをワイ
ヤ１４により、ループ状に電気的に接続した状態を示
す。FIG. 2 is a diagram showing a procedure for manufacturing the semiconductor device shown in FIG. 1. FIG. 2 (a) shows that the semiconductor chip 12 is bonded onto the tab 11 of the lead frame 20 by a die bonding process, and then wire bonding. In the process, the electrodes provided on the semiconductor chip 12 and the tips of the leads 13 are electrically connected in a loop by the wires 14.

【００１７】図２（ｂ）は同図（ａ）に示す接合工程が
終了した後における固定部形成工程を示す。この工程で
は、シリコーンによって内側固定部１５が形成され、半
導体チップ１２の外面とワイヤ１４が覆われるとともに
ワイヤ１４相互とリード１３の先端部相互ならびにリー
ド１３の先端とタブ１１とが相互に固定されることにな
る。シリコーンは、シロキサン結合の繰り返しを主鎖と
し、側基としてアルキル、アリール基などをもつ重合体
であって、耐熱性、撥水性、電気絶縁性、耐薬品性など
に優れている。重合度、側基の種類、橋かけの程度によ
って液状、グリース状、ゴム状、そして樹脂状のものが
あるが、図示する場合にはゴム状のものつまり弾性を有
するものが使用されている。FIG. 2B shows a fixing portion forming step after the joining step shown in FIG. In this step, the inner fixing portion 15 is formed of silicone, the outer surface of the semiconductor chip 12 and the wire 14 are covered, and the wires 14 and the tips of the leads 13 and the tips of the leads 13 and the tabs 11 are fixed to each other. Will be. Silicone is a polymer having a repeating siloxane bond as a main chain and having an alkyl or aryl group as a side group, and is excellent in heat resistance, water repellency, electric insulation, chemical resistance and the like. Depending on the degree of polymerization, the type of side groups, and the degree of cross-linking, there are liquid, grease-like, rubber-like, and resin-like ones. In the illustrated case, a rubber-like one, that is, one having elasticity is used.

【００１８】シリコーンゴムによって内側固定部１５を
形成するには、素材を流動状態として半導体チップ１２
の上側から滴下する。これにより、滴下された素材はワ
イヤ１４の相互間における隙間やリード１３の先端部相
互間に入り込み、これらが固定される。内側固定部１５
が硬化したならば、図２（ｃ）に示すモールド装置に搬
送される。In order to form the inner fixing portion 15 with silicone rubber, the material is made to flow and the semiconductor chip 12 is
Dripping from above. As a result, the dropped material enters the gaps between the wires 14 and the tip portions of the leads 13 and fixes them. Inner fixed part 15
When the resin is cured, it is transferred to the molding apparatus shown in FIG.

【００１９】モールド装置３０は下金型３１と上金型３
２とを有し、これらを型合わせすることにより、両方の
金型３１，３２に形成されている凹部によってモールド
キャビティ３３が形成される。型合わせした状態でこの
モールドキャビティ３３内に溶融状態のレジンを充填す
ることにより、モールドキャビティ３３の形状に対応し
た樹脂製のパッケージ１６が成形される。The molding device 30 includes a lower mold 31 and an upper mold 3.
2 and the mold cavity 33 is formed by the concave portions formed in both the molds 31 and 32 by mating them. By filling the molten resin into the mold cavity 33 in a state where the molds are matched with each other, the resin package 16 corresponding to the shape of the mold cavity 33 is molded.

【００２０】この成形時には、固定部形成工程において
ワイヤ１４相互などが固定されているので、モールドキ
ャビティ３３内に充填されるレジンの流れよって、ワイ
ヤ１４やタブ１１が変形することが防止される。また、
パッケージ１６を成形する際におけるレジンの熱によっ
て内側固定部１５に熱応力が作用しても、内側固定部１
５が弾性変形し得る素材により形成されているので、熱
応力に起因するタブの変動などの影響を抑制することが
できる。At the time of this molding, the wires 14 and the like are fixed in the fixing portion forming step, so that the wires 14 and the tabs 11 are prevented from being deformed by the flow of the resin filled in the mold cavity 33. Also,
Even if thermal stress acts on the inner fixing portion 15 by the heat of the resin when molding the package 16, the inner fixing portion 1
Since 5 is made of a material that is elastically deformable, it is possible to suppress the influence of fluctuations in tabs and the like due to thermal stress.

【００２１】図３はこのようにしてパッケージ１６が成
形された後のリードフレーム２０の全体を示す平面図で
あり、図３に示す部分が複数個一体となった状態でパッ
ケージ１６の成形が終了する。リードフレーム２０は、
トリミング工程とフォーミング工程とを経て、図１に示
す半導体装置が得られる。トリミング工程は、パッケー
ジ１６をリードフレーム２０の外枠２１，２２、内枠２
３およびダム片２４から切り離してリード１３のアウタ
ー部を独立させる工程であり、フォーミング工程はリー
ド１３のアウター部を所定の形状に折り曲げる工程であ
る。FIG. 3 is a plan view showing the entire lead frame 20 after the package 16 has been molded in this way, and the molding of the package 16 is completed with the plurality of parts shown in FIG. 3 being integrated. To do. The lead frame 20 is
The semiconductor device shown in FIG. 1 is obtained through the trimming process and the forming process. In the trimming process, the package 16 is divided into the outer frames 21, 22 and the inner frame 2 of the lead frame 20.
3 and the dam piece 24 to separate the outer portion of the lead 13 from each other, and the forming step is a step of bending the outer portion of the lead 13 into a predetermined shape.

【００２２】図２（ｂ）で示すように内側固定部１５が
形成された状態では、ワイヤ１４や半導体チップ１２の
表面などが覆われて保護されているので、ワイヤ１４な
どに付着するゴムなどの影響を考慮する必要がなくな
り、多数のリードフレーム２０を内側固定部１５が形成
された状態でストックつまり貯留しておくことができ
る。したがって、ストックされていたリードフレーム２
０を用いて、モールドキャビティ３３の形状や寸法が相
違したモールド装置でパッケージ１６を成形することに
よって、最終的なパッケージ１６の形状に応じてサイズ
変更を容易に行うことができる。As shown in FIG. 2B, when the inner fixing portion 15 is formed, the surfaces of the wires 14 and the semiconductor chip 12 are covered and protected, so that the rubber or the like attached to the wires 14 or the like is covered. It is no longer necessary to consider the influence of the above, and a large number of lead frames 20 can be stocked or stored with the inner fixing portion 15 formed. Therefore, the stock lead frame 2
By using 0 to mold the package 16 with a molding device in which the shape and dimensions of the mold cavity 33 are different, the size can be easily changed according to the final shape of the package 16.

【００２３】さらに、パッケージ１６を成形する際にお
けるワイヤ１４の変形などを考慮する必要がなくなるの
で、パッケージ１６の厚みを薄くした薄型半導体装置を
製造する場合でも、半導体チップ１２の厚みを厚くした
り、ワイヤループの高さを高く設定することがで、厚み
の厚い半導体装置を製造するためのものと同一のワイヤ
ボンディング装置を用いて薄型の半導体装置のワイヤボ
ンディングを行うことができる。Further, since it is not necessary to consider the deformation of the wire 14 when molding the package 16, the thickness of the semiconductor chip 12 may be increased even when a thin semiconductor device in which the thickness of the package 16 is thin is manufactured. By setting the height of the wire loop to be high, it is possible to perform wire bonding of a thin semiconductor device by using the same wire bonding device for manufacturing a thick semiconductor device.

【００２４】また、半導体チップ１２を二層構造で封止
するようにしたことから、外側のパッケージ１６にクラ
ックが発生しても、そのクラックが内側固定部１５にま
で伝播されることが防止される。同様に、内側固定部１
５にクラックが発生しても、そのクラックが外側のパッ
ケージ１６にまで伝播されることはない。Further, since the semiconductor chip 12 is sealed with the two-layer structure, even if a crack is generated in the outer package 16, the crack is prevented from propagating to the inner fixing portion 15. It Similarly, the inner fixing portion 1
Even if a crack occurs in No. 5, the crack does not propagate to the outer package 16.

【００２５】内側固定部１５を形成する手段としては、
パッケージ１６を成形するためのモールド装置を用いる
ようにしても良く、さらには、接着剤を塗布して内側固
定部１５を形成するようにしても良い。また、図１に示
す半導体装置にあっては、半導体チップ１２の封止が内
側固定部１５と樹脂製のパッケージ１６とによりなされ
ているが、内側固定部１５とパッケージ１６との間に、
耐熱性や耐湿性に優れた中間層を形成するようにしても
良い。この中間層の形成は、たとえば、樹脂などを内側
固定部１５の表面に噴霧して塗布したり、どぶ付けする
ことによりなされる。As a means for forming the inner fixing portion 15,
A molding device for molding the package 16 may be used, and further, an adhesive may be applied to form the inner fixing portion 15. Further, in the semiconductor device shown in FIG. 1, the semiconductor chip 12 is sealed by the inner fixing portion 15 and the resin package 16. However, between the inner fixing portion 15 and the package 16,
You may make it form the intermediate | middle layer excellent in heat resistance and moisture resistance. The intermediate layer is formed, for example, by spraying a resin or the like on the surface of the inner fixing portion 15 to apply it, or by applying a drip.

【００２６】前記した半導体装置は、タブ１１を有する
タイプのものであるが、タブ１１を使用しないタイプの
半導体装置を製造することもできる。図４（ａ）はタブ
１１を用いないタイプであって、リード１３の先端部に
半導体チップ１２が積層され、半導体チップ１２のうち
回路が形成されていない面がリード１３と対向し、リー
ド１３と電極とがワイヤ１４を介して接続されたＣＯＬ
タイプの半導体装置を示す。図４（ｂ）は同様にタブ１
１を用いないタイプであって、リード１３の先端部に半
導体チップ１２が積層され、半導体チップ１２のうち回
路が形成された面に設けられた電極がリード１３に直接
接続されたＬＯＣタイプの半導体装置を示す。図４
（ｂ）に示す場合には、はんだバンプ１７の部分が電気
的接続部となる。The above-mentioned semiconductor device is of a type having the tab 11, but it is also possible to manufacture a semiconductor device of the type not using the tab 11. FIG. 4A shows a type in which the tab 11 is not used, in which the semiconductor chip 12 is laminated on the tip of the lead 13, and the surface of the semiconductor chip 12 on which the circuit is not formed faces the lead 13. COL in which the electrode and the electrode are connected via the wire 14.
1 illustrates a type of semiconductor device. Similarly, FIG. 4B shows tab 1
1 is a type that does not use 1 and is a LOC type semiconductor in which the semiconductor chip 12 is laminated on the tip of the lead 13 and the electrode provided on the surface of the semiconductor chip 12 on which the circuit is formed is directly connected to the lead 13. Shows the device. FIG.
In the case shown in (b), the portion of the solder bump 17 serves as an electrical connection portion.

【００２７】以上、本発明者によってなされた発明を実
施の形態に基づき具体的に説明したが、本発明は前記実
施の形態に限定されるものではなく、その要旨を逸脱し
ない範囲で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

【００２８】たとえば、図示する半導体装置はＱＦＰタ
イプのものを示すが、ＳＯＰ(SmallOutline Package)
タイプ、ＱＦＪ(Quad Flat J-leaded Package)タイプな
どの面実装タイプの半導体装置やＤＩＰ(Dual in-line
Package)タイプなどのピン挿入タイプの半導体装置に対
しても適用することができる。For example, the semiconductor device shown is of the QFP type, but SOP (Small Outline Package)
Type, surface mount type semiconductor devices such as QFJ (Quad Flat J-leaded Package) type and DIP (Dual in-line)
It can also be applied to pin insertion type semiconductor devices such as Package) type.

【００２９】[0029]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【００３０】(1).ワイヤや半導体チップを内側固定部に
よって覆った後にパッケージを成形するようにしたの
で、モールドレジンの熱による影響を防止し、信頼性の
高い半導体装置を歩留り良く製造することができる。(1). Since the package is molded after the wires and the semiconductor chips are covered with the inner fixing portion, the influence of heat of the mold resin can be prevented, and a highly reliable semiconductor device can be manufactured with high yield. You can

【００３１】(2).内側固定部を形成した後のリードフレ
ームを多量にストックすることができ、最終的な半導体
装置の外径寸法の需要に応じて任意のサイズのものを自
由に設定することができる。(2) It is possible to stock a large amount of lead frames after forming the inner fixing portion, and freely set any size according to the demand for the outer diameter dimension of the final semiconductor device. be able to.

【００３２】(3).これにより、生産能率を大幅に向上す
ることができる。(3) As a result, the production efficiency can be greatly improved.

【００３３】(4).半導体チップを封止する部分が多層構
造となるので、外側の部分にラクックが発生しても、内
側の部分にまでクラックが入り込むことを防止すること
ができる。(4) Since the portion for encapsulating the semiconductor chip has a multi-layer structure, even if a crack occurs in the outer portion, it is possible to prevent cracks from reaching the inner portion.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の製造方法によって製造さ
れた半導体装置の一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to the present invention.

【図２】半導体装置の製造工程を示す工程図である。FIG. 2 is a process drawing showing a manufacturing process of a semiconductor device.

【図３】パッケージを成形した後のリードフレームの一
部を示す平面図である。FIG. 3 is a plan view showing a part of the lead frame after molding the package.

【図４】（ａ）および（ｂ）はそれぞれ他のタイプの半
導体装置を示す断面図である。4A and 4B are cross-sectional views showing other types of semiconductor devices, respectively.

【符号の説明】[Explanation of symbols]

１１ タブ １２ 半導体チップ １３ リード １４ ワイヤ １５ 内側固定部 １６ パッケージ １７ はんだバンプ ２０ リードフレーム ２１，２２ 外枠 ２３ 内枠 ２４ ダム片 ３０ モールド装置 ３１ 下金型 ３２ 上金型 ３３ モールドキャビティ 11 tabs 12 semiconductor chips 13 leads 14 wires 15 inner fixing parts 16 packages 17 solder bumps 20 lead frames 21, 22 outer frames 23 inner frames 24 dam pieces 30 molding equipment 31 lower molds 32 upper molds 33 mold cavities

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップに設けられた電極に電気的
接続部を介して接続される複数のリードを有するリード
フレームに前記半導体チップを接合する接合工程と、 前記半導体チップの外面と前記電気的接続部とを覆いか
つこれらを固定する内側固定部を形成する固定部形成工
程と、 前記内側固定部の外側にモールド装置を用いて樹脂パッ
ケージを成形するモールド工程とを有することを特徴と
する半導体装置の製造方法。1. A bonding step of bonding the semiconductor chip to a lead frame having a plurality of leads connected to an electrode provided on the semiconductor chip via an electrical connection portion, and an outer surface of the semiconductor chip and the electrical connection. A semiconductor comprising: a fixing part forming step of forming an inner fixing part for covering the connection part and fixing them; and a molding step of molding a resin package on the outside of the inner fixing part using a molding device. Device manufacturing method. 【請求項２】 請求項１記載の半導体装置の製造方法で
あって、前記固定部形成工程は、前記樹脂パッケージの
素材よりも硬度が低いゴムなどの軟質材料を流動状態と
して前記半導体チップの上方から滴下するようにしたこ
とを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the fixing portion forming step, a soft material such as rubber having a hardness lower than that of the material of the resin package is made to flow above the semiconductor chip. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is dropped. 【請求項３】 請求項１または２記載の半導体装置の製
造方法であって、前記固定部形成工程と前記モールド工
程との間に、前記内側固定部と前記樹脂パッケージとの
間に設けられる少なくとも一層の中間層を形成する工程
を有することを特徴とする半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein at least the inner fixing portion and the resin package are provided between the fixing portion forming step and the molding step. A method of manufacturing a semiconductor device, comprising the step of forming a single intermediate layer.
JP7273811A 1995-10-23 1995-10-23 Manufacture of semiconductor device Pending JPH09115935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7273811A JPH09115935A (en) 1995-10-23 1995-10-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7273811A JPH09115935A (en) 1995-10-23 1995-10-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH09115935A true JPH09115935A (en) 1997-05-02

Family

ID=17532897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7273811A Pending JPH09115935A (en) 1995-10-23 1995-10-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH09115935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008504717A (en) * 2004-06-25 2008-02-14 コンティ テミック マイクロエレクトロニック ゲゼルシャフト ミット ベシュレンクテル ハフツング Electrical equipment with protective coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008504717A (en) * 2004-06-25 2008-02-14 コンティ テミック マイクロエレクトロニック ゲゼルシャフト ミット ベシュレンクテル ハフツング Electrical equipment with protective coating

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