JPH09114422A - Driving circuit of display device, desplay device, and driving method for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit of display device to realize a display device capable of performing a proper display even to various display systems. SOLUTION: This circuit drives a display device so as to perform a display after the enable IE indicating a data display position is supplied from the information device main body being a signal source. In this case, the circuit is provided with an enable input period detecting circuit 1 detecting the period of the input enable IE and a display control circuit part 20 controlling the device so as to continuously perform the display by a display control signal to be generated inside the circuit even after the input period of the input enable IE is finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving technique, and more particularly to a drive circuit for a display device such as an active matrix liquid crystal display device. In recent years, with the diversification of information, display displays that visually give information have become important. By the way, display devices often use enable signals for designating display positions in order to diversify information devices and improve compatibility between devices. Since this enable signal is output to the data display position, if the display data is less than the number of display lines of the display device, the remaining display lines cannot be displayed. Therefore, there is a demand for a display device driving technique capable of performing an appropriate display for various information devices.

[0002]

2. Description of the Related Art Conventionally, there has been provided an active matrix type liquid crystal display device using a thin film transistor (TFT) in order to improve the image quality of liquid crystal. 11 is a block diagram showing an example of an active matrix liquid crystal display device, FIG. 12 is a diagram for explaining a configuration of each pixel in the liquid crystal display device of FIG. 11, and FIG. 13 is a liquid crystal display of FIG. 6 is a timing chart for explaining the operation of the device.

In FIG. 11, reference numeral 101 is an LCD.
A panel, 102 is a data line drive circuit, 103 is a gate line drive circuit, 106 and 108 are shift registers, 107 is a data hold circuit, and 109 is a gate drive circuit. As shown in FIG.
The active matrix type LCD (liquid crystal display device) is
The LCD panel 101, the data line driving circuit 102, and the gate line driving circuit 103 are provided. The LCD panel 101 includes two glass plates (TFT
The liquid crystal material (105) is sealed in the gap between the substrate and the common substrate, and the pixel electrodes are formed in a matrix on the inner surface of each glass plate.

The data line driving circuit 102 includes a shift register 106 and a data hold circuit 107,
According to the data clock, the input data voltage
The first output is sequentially held, and the data for one line is sequentially supplied to the vertical pixel lines (data lines). The gate line drive circuit 103 includes a shift register circuit 108 and a gate drive circuit 109, and sequentially outputs a gate drive voltage from a first output in accordance with a shift clock so that data is written by selecting each line. Has become.

As shown in FIG. 12, the LCD panel 1
Each pixel in 01 is switching-controlled by a transistor (TFT) 104 whose gate electrode is supplied with the output of the gate line drive circuit 103 and whose drain electrode is supplied with the output of the data line drive circuit 102. That is, the TFT 104 for one line is switched on by the output of the gate line driving circuit 103, and the data for one line from the data line driving circuit 102 is applied to the pixel electrode of each pixel (105),
Data writing is performed.

As shown in FIG. 13, first, a data line driving circuit 102 and a gate line driving circuit 103.
The data line driving circuit 1 after resetting the
The data for one horizontal line (data output No. 1 to No. n) is sent to 02 with the data clock, and when the hold is completed, the gate line drive circuit 103 outputs the first data.
Drive voltage for the second horizontal line (gate drive signal N
o. 1) is output. As a result, each of the TFTs 104 on the first horizontal line becomes conductive, and writing is performed on each pixel. Further, in the next cycle, the data voltage (data output No. 1 to No. n) for the second horizontal line is set to the data line driving circuit 102,
A drive voltage (gate drive No. 2) is output from the gate line drive circuit 103 to the second horizontal line.
When the data writing to the final horizontal line is completed by repeating the above operation in sequence, the operation returns to the first horizontal line, a new data writing operation is started, and a predetermined image is sequentially displayed.

[0007]

A display device such as the above-mentioned active matrix type liquid crystal display device is usually provided with a clock signal synchronized with display data, a horizontal display signal (HSYNC signal) for determining horizontal display timing, Also, although the display is controlled by the vertical display signal (VSYNC signal) that determines the frame display timing when switching screens, there is an enable signal that specifies the display position in order to diversify information devices and improve compatibility between devices. It is becoming more and more used. Since this enable signal is output to the data display position, if the display data is less than the number of display lines of the display device, the remaining display lines cannot be displayed.

Therefore, in the conventional display device, since the display timing is controlled on the side of the information device (information device) which is a signal source, depending on the information device, the enable signal may be continuously output regardless of the display data, Alternatively, it outputs by supplementing the enable signal. However, since the display device side complies with the specifications of the information device, when the information device is changed and the display method and the number of display data are changed, the display may not be possible or the display may be deviated and the display may not be normally performed.

Furthermore, depending on the display device, HSYNC
Some control is performed such that the number of display data is discriminated based on the polarity of the signal and VSYNC signal, the number of pulses, etc., and normally displayed. However, in the multi-display by such a discrimination method, only a limited data system can be displayed. Instead, a huge number of discrimination circuits were needed to meet all the conditions. In reality, many display methods are conceivable due to the diversification of information, and it is not possible to deal with the limited display by the discrimination method.

Specifically, when the enable signal indicating the display position of the display data is output from the information device, when the display data number of the enable signal is smaller than the display data number of the display device, the remaining horizontal display lines are displayed. However, there are inconveniences such as direct current being applied to the liquid crystal and deterioration of the liquid crystal, and normal display being impossible. The present invention has been made in view of the problems of the above-described conventional display device, and an object of the present invention is to provide a display device capable of performing an appropriate display for various display systems.

[0011]

According to a first aspect of the present invention, there is provided a drive circuit for a display device, which is supplied with an input enable indicating a data display position from an information device main body serving as a signal source and performs display. An enable input period detection circuit for detecting the input period of the input enable, and a display control circuit unit for controlling so as to continue display by a display control signal internally generated even after the input period of the input enable ends. A drive circuit for a display device is provided, which comprises:

According to a second aspect of the present invention, there is provided a method of driving a display device, in which an input enable indicating a data display position is supplied from an information device main body serving as a signal source for displaying, and There is provided a method for driving a display device, which is characterized in that the display is continuously performed by a display control signal internally generated even after the output of the input enable input is finished.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION According to the drive circuit of the display device of the present invention, even after the input enable input period is detected by the input period detection circuit and the input enable input period is ended by the display control circuit section, The display control signal created in step 1 is controlled to continue the display.

According to the driving method of the display device of the present invention, even after the output of the input enable input from the information device main body is completed, the display is continued by the display control signal internally generated. As a result, it is possible to perform an appropriate display for various display methods.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of a drive circuit for a display device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a first embodiment of a drive circuit of a display device according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the drive circuit of FIG.

As shown in FIG. 1, the enable input period detection circuit 1 receives the input enable IE and the detection flag DF, and outputs the enable input flag EF. The enable input flag EF is supplied to the internal synchronous display control circuit 21 and the external synchronous display control circuit 22 in the display control circuit unit 20. Here, the input enable IE is also supplied to the external synchronous display control circuit 22, and the outputs of the internal synchronous display control circuit 21 and the external synchronous display control circuit 22 are displayed on the display unit (LCD panel 101).
It is supplied to.

The enable input period detection circuit 1 is a circuit for detecting until the input enable IE supplied from the information device (signal source) exceeds the display data area of the information device and is no longer output, and the display control circuit. Upon detection of the enable input flag EF, the unit 20 switches between the display control by the internal synchronous display control circuit 21 and the display control by the external synchronous display control circuit 22 and continues after the external input is completed. The display is continued by the control signal created internally.

1 and 2, the input enable IE is a signal indicating the display position of the data input from the information device, and the enable input flag EF is the information indicating the input enable IE input from the information device. This is a flag signal that detects the timing at which output is stopped beyond the display data area of the device. Furthermore, supplementary enable SE
Is a display timing of the data generated inside the display device, and is a display control signal for continuing the display control when the input enable IE is no longer output and the enable input flag EF is detected.

According to the first embodiment, the input enable I
While E is being supplied, the input enable IE (output of the external creation display control circuit 21) is output enable OE.
(Output of the display control circuit unit 20), and when the input enable IE is no longer supplied, the supplemental enable SE created by the internal synchronous display control circuit 21 is output as the output enable OE. ing. As a result, regardless of the number of input enable IEs supplied from the information device, even after the display data area of the information device is finished, the display can be continued at the internally generated display timing. Here, the display data when the supplement enable SE is output is, for example, data in which each line of the supplement display data area is displayed in "black" over the entire surface.

In other words, in the first embodiment, even when the number of input enables supplied from the information device (display data area from the information device) is smaller than the number of display data of the display device (display data area of the display device), A control signal (supplemental enable: supplemental display data area) for displaying the insufficient display data area inside the display device is created and displayed. Therefore, according to the first embodiment, even when the number of display data output from the information device is smaller than the display data number of the display device, the display control signal (SE) is continuously internally generated.
Since the display is created and the display is continued, it is possible to prevent the display from being missing or the display on which the direct current is applied, thereby performing the normal display.

FIG. 3 is a block diagram showing a configuration example of the enable input period detection circuit 1 in the drive circuit of FIG.
In FIG. 3, reference numerals 11 to 14 denote D-type flip-flops (DF.F.), and 15 denotes an AND circuit. Further, reference symbol Vcc indicates a high-potential power supply line (high-potential power supply voltage). As shown in FIG. 3, the enable input period detection circuit 1 is configured to include four D-type flip-flops 11 to 14 and an AND circuit 15. The input enable IE is the horizontal cycle (HSYN
C) and the vertical period (VSYNC), the input timing is detected, and the enable input flag EF is further created at the input timing. The enable input flag EF is supplied to the internal synchronous display control circuit 21 and the external synchronous display control circuit 22 in the display control circuit 20, as shown in FIG.

Here, the detection pulse DP (detection flag D
F) is a scan pulse considering the start timing of the input enable IE, and the detected enable input flag EF is the AND of the output flag in the horizontal period (line) and the output flag in the vertical period (frame). It was taken. In the above embodiment, the enable input flag EF is the AND of the outputs of the flip-flops 12 and 14.
It may be limited to either the output flag in the horizontal cycle or the output flag in the vertical cycle. Further, in the circuit shown in FIG. 3, in order to avoid malfunction due to noise, it is configured by two stages of flip-flops 11, 12, 13 and 14, but one stage of flip-flop (11, 13). ) Can also be configured. further,
The D-type flip-flops 11 to 14 can also be configured by circuits such as JK flip-flops and counters.

FIG. 4 is a block diagram showing the basic construction of the second embodiment of the drive circuit for a display device according to the present invention. As shown in FIG. 4, the memory circuit 3 is supplied with the enable input timing ET and stores the input timing of the enable signal (input enable IE) at the time of normal input from the information device. Further, the output of the memory circuit 3 and the enable input flag EF are supplied to the internal synchronous display control circuit 21, and a control signal (supplemental enable SE) internally generated is output from the memory circuit 3 (input timing of the enable signal). ), It is controlled internally.

That is, the enable input timing ET of the input enable IE at the time of normal input from the information device is stored in the storage circuit 3, and the internal synchronous display control circuit 4 displays the display control signal (in accordance with the stored enable input timing). A supplementary enable SE) is created internally and is continuously displayed. FIG. 5 is a block diagram showing a configuration example of the drive circuit of FIG.

As shown in FIG. 5, the input timing detection circuit 32 is supplied with the input enable IE and the inverted enable input flag EF via the inverter 31, whereby the input timing detection circuit (counter circuit) is provided. ) 32 outputs the enable input timing ET. The enable input timing ET is supplied to the memory circuit 33 (3). The output (A) of the memory circuit 33 is supplied to the internal enable creation circuit (counter circuit) 34 together with the enable input flag EF, and the output of the internal enable creation circuit 34 is also displayed together with the enable input flag EF in the internal synchronous display control. Circuit 35
It is supplied to (4).

Here, the enable input flag EF is, for example, the enable input period detection circuit (1) shown in FIG.
Can be created by. FIG. 6 is a block diagram showing the basic configuration of the third embodiment of the drive circuit of the display device according to the present invention. In this embodiment, input enable (IE)
In addition to outputting the supplemental enable (SE) when is not output, the display data is internally created and is not output. That is, the supplement enable SE
Is output and displayed, each line of the supplemental display data area is entirely "white", or a predetermined pattern is displayed.

As shown in FIG. 6, the display control circuit section 5
Is supplied with the enable input flag EF, and the output (display timing DT) of the display control circuit unit 5 is supplied to the display data creation circuit 6. The output of the display data creation circuit 6 is supplied to the display data switching circuit 7. Here, the enable input flag EF is also supplied to the display data switching circuit 7. Further, the enable input flag EF can be created by the enable input period detection circuit (1) shown in FIG. 3, for example.

The display data creating circuit 6 creates a predetermined arbitrary display data (for example, whole surface "white" or a predetermined pattern) according to the display timing DT output from the display control circuit section 5. Then, the display data switching circuit 7 displays the supplemental display data area selected by the enable input flag EF with the display data created internally.

FIG. 7 is a diagram showing an example of the display data switching circuit 7 in the drive circuit of FIG. As shown in FIG. 7, the display data switching circuit 7 is composed of a selector 30, which is supplied with input data and creation data, and is supplied from an information device in response to an enable input flag EF (selection signal). The selected input data and the created data created internally are selected and output. That is, when the enable input flag EF is at the low level “L” and the input enable (IE) from the information device is supplied, the input data (display data DD)
On the contrary, when the enable input flag EF is at the high level “H” and the input enable (IE) from the information device is not supplied, the creation data (output of the display data creation circuit 6) is selected. It is designed to output.

Here, in the above embodiment, the data to be selected is internally created data in advance,
A signal from outside the circuit may be selected and switched and output. Further, although the display is switched by the selector, the output control circuit may be constituted by a logic circuit such as an AND gate and an OR gate.

FIG. 8 is a block diagram showing the basic construction of the fourth embodiment of the drive circuit of the display device according to the present invention, and FIG. 9 is a timing diagram for explaining the operation of the drive circuit of FIG. is there. As shown in FIG. 8, the enable input detection circuit 8 includes an input enable IE and a detection flag DF.
Is input and the enable input rising flag ERF is output. This enable input rising flag ER
F is supplied to the counter circuit 9. And where
The output mask OM is output from the counter circuit 9,
It is supplied to the display controller.

In the fourth embodiment, the enable input detection circuit 8 determines the start position of the display data from the information device (the start position of the data in the horizontal and vertical directions), and the counter circuit 9 determines it for each display device. A mask signal OM corresponding to the number of display data of the display device in use is created. The display control section controls the display area according to the output area of the output mask OM so that the number of display data of the display device is made unique.

That is, as shown in FIG. 9, the output mask OM is a mask signal according to the number of display data of the display device, and the output mask OM causes the number of display data from the information device to be displayed on the display device. When the number of data is less than the number of data, supplementary display is performed by the internally generated control signal (supplement enable SE), and the number of display data from the information device is the same as the number of display data of the display device or when the number of display data is large, To match that of the display device.

Therefore, according to the fourth embodiment, the display control signal can be fixed to the number of display data of the display device and displayed regardless of the number of display data from the information device.
FIG. 10 is a block diagram showing a configuration example of the drive circuit of FIG. As shown in FIG. 8, the drive circuit of the present embodiment is 2
It is configured to include one counter 41 and 42.
That is, the enable input detection circuit 8 and the counter circuit 9 in FIG. 8 can be configured by the counters 41 and 42, respectively. In the present embodiment shown in FIG. 10, the input enable IE is supplied to the clock terminal of the counter 41, and the high potential power supply voltage (V
cc) is applied. The circuit shown in FIG. 10 outputs the output mask OM as shown in FIG. 9 so that the number of display data from the information device matches the number of display data of the display device.

In the above, the display device targeted by the present invention is the active matrix type liquid crystal display device described mainly with reference to FIGS. 11 to 13. However, the application of the present invention is applied to the active matrix type liquid crystal. The present invention is not limited to a display device, but can be widely applied to a display device in which an input enable (IE) indicating a data display position is supplied from an information device main body serving as a signal source for display.

[0036]

As described above in detail, according to the drive circuit of the display device of the present invention, the supplied display data number is displayed regardless of the display data number of the enable signal supplied from the information device. A display device (multi-display display) that can perform an appropriate display for various display methods by supplementing a control signal for displaying the insufficient display data area even when the number of display data items is smaller than that of the device Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a first embodiment of a drive circuit of a display device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the drive circuit of FIG.

3 is a block diagram showing a configuration example of an enable input period detection circuit in the drive circuit of FIG.

FIG. 4 is a block diagram showing a basic configuration of a second embodiment of the drive circuit of the display device according to the present invention.

5 is a block diagram showing a configuration example of a drive circuit in FIG.

FIG. 6 is a block diagram showing a basic configuration of a third embodiment of the drive circuit of the display device according to the present invention.

7 is a diagram showing an example of a display data switching circuit in the drive circuit of FIG.

FIG. 8 is a block diagram showing a basic configuration of a fourth embodiment of the drive circuit of the display device according to the present invention.

9 is a timing chart for explaining the operation of the drive circuit of FIG.

10 is a block diagram showing a configuration example of a drive circuit in FIG.

FIG. 11 is a block diagram showing an example of an active matrix liquid crystal display device.

12 is a diagram for explaining a configuration of each pixel in the liquid crystal display device of FIG.

13 is a timing chart for explaining the operation of the liquid crystal display device of FIG.

[Explanation of symbols]

 1 ... Enable input period detection circuit 3 ... Memory circuit 4 ... Internal synchronous display control circuit 5 ... Display control circuit section 6 ... Display data creation circuit 7 ... Display data switching circuit 8 ... Enable input detection circuit 9 ... Counter circuit 20 ... Display Control circuit unit 21 ... Internal synchronous display control circuit 22 ... External synchronous display control circuit 30 ... Selector 41 ... Counter 42 ... Counter 101 ... Display panel (LCD panel) 102 ... Data line drive circuit 103 ... Gate line drive circuit 104 ... Thin film transistor (TFT) 105 ... Liquid crystal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mikio Oshiro 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takahide Ito 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (9)

[Claims] 1. A drive circuit of a display device for displaying by inputting an input enable (IE) indicating a data display position from an information device main body which is a signal source, and detecting an input period of the input enable (IE). An enable input period detection circuit (1), and a display control circuit section (20) for controlling to continue display by a display control signal internally generated even after the input period of the input enable (IE) is finished. A drive circuit for a display device, comprising: 2. The display control circuit unit (20), an external synchronous display control circuit (22) for outputting the input enable (IE) during an input period of the input enable (IE), and the input enable (IE). 2. The drive circuit for a display device according to claim 1, further comprising an internal synchronous display control circuit (21) for outputting a display control signal internally generated after the input period of (1) is finished. 3. A drive circuit of a display device, which is supplied with an input enable (IE) indicating a data display position from an information device main body serving as a signal source to perform display, and which is an input enable during normal input from the information device. (I
A storage circuit (3) for storing the enable input timing (ET) of E) and a display control signal internally generated according to the stored enable input timing even after the input period of the input enable (IE) ends. A drive circuit for a display device, comprising: an internal synchronous display control circuit (4) for continuing display. 4. The drive circuit of the display device further includes an input timing detection circuit (32) for generating the enable input timing (ET) from the input enable (IE) and the enable input flag (EF), and the memory. 4. An internal enable generation circuit (34) for generating an internal enable from an enable input timing (ET) stored in the circuit (33: 3) and the enable input flag (EF). Drive circuit of display device. 5. A drive circuit of a display device, which receives an input enable (IE) indicating a data display position from an information device main body serving as a signal source to perform display, and detects a rising timing of the input enable (IE). And a counter circuit (9) for counting the output of the enable input detection circuit (8) and outputting an output mask (OM). A drive circuit for a display device, which is adapted to match the number of displays. 6. An active matrix type liquid crystal display device comprising the drive circuit of the display device according to claim 1. 7. A method for driving a display device, wherein an input enable (IE) indicating a data display position is supplied from an information device main body serving as a signal source to perform display, and the input enable (IE) input from the information device main body is used. I
A method for driving a display device, wherein display is continuously performed by a display control signal internally generated even after the output in E) is completed. 8. A method of driving a display device, wherein an input enable (IE) indicating a data display position is supplied from an information device main body serving as a signal source to perform a display, and the input enable is normally input from the information device. (I
The enable input timing (ET) of E) is stored, and the display is continuously performed by the display control signal internally generated according to the stored enable input timing even after the input period of the input enable (IE) ends. A method for driving a display device characterized by the above. 9. A method of driving a display device, wherein an input enable (IE) indicating a data display position is supplied from an information device main body serving as a signal source to perform display, and a rising timing of the input enable (IE) is detected. And an output mask (OM) for counting the outputs of the enable input detection circuit (8) and the output of the enable input detection circuit (8) so that the display number of data matches the display number of the display device. A drive circuit for a display device characterized by the above.