JP2002244610A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a display device capable of executing an adjusting operation without displaying a disturbed video on a screen while holding the video in a frame unit without using a frame memory. SOLUTION: In the case where a non-display control signal OE is at an H level, in the frame, even though a gate-driver shift clock CLKV is raised when a vertical start pulse STV is at the H level, row selection signals X1 to XN are always held at L levels by control of a control circuit 32. Since ON voltages are not applied to gates of TFTs(thin film transistors) of respective liquid crystal pixels when the row selection signals X1 to XN are in states of L levels, even when a signal voltage Vout is outputted from a source driver 2, the voltage is not applied to the liquid crystal pixels and the rewriting of a video is not performed. At this time, since liquid crystal holds electric charges in the immediately preceding frame, the video in the immediately preceding frame is displayed on a liquid crystal panel 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to an active matrix drive type liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. H11-15428 has been known as a liquid crystal display device which can hold an image on a frame basis and display an image of a previous frame on a screen. This liquid crystal display device uses a frame memory capable of storing video in units of one frame. When changing the frequency division value of the PLL or adjusting the clock phase, the frame memory is used immediately before the adjustment operation. By stopping the writing of the video signal to the LCD and repeatedly reading the same video signal from the frame memory during the adjustment period and displaying it on the screen, the disturbed video accompanying the adjustment is not displayed on the screen. is there.

[0003]

However, such a conventional display device has a problem that a frame memory is required, which leads to an increase in circuit scale and cost. In particular, as the resolution increases, a large-capacity frame memory is required, so that the effect is great.

The present invention has been made in order to solve such a problem, and holds an image in units of frames without using a frame memory, does not display a disturbed image on a screen, and reduces the frequency division value of a PLL. It is an object of the present invention to obtain a display device capable of executing an adjustment operation such as a change.

[0005]

Means for Solving the Problems Claim 1 of the present invention
The display device according to (1) provides a switching element for each pixel defined at the intersection of the plurality of scanning electrodes and the plurality of signal electrodes, and performs a scanning operation of selecting the scanning electrodes line-sequentially by the first driving circuit. A display device for supplying a video signal from a second driving circuit to a pixel corresponding to a selected scanning electrode via a signal electrode via a switching element, wherein the scanning operation is stopped for a specific frame period. Thus, during the suspension period, the video of the frame before the suspension is displayed.

According to a second aspect of the present invention, there is provided the display device according to the first aspect, wherein the first drive circuit is based on a start pulse and a transition of a shift clock. A scanning operation is started, and in a specific frame period, a non-display control signal for stopping the start of the scanning operation regardless of the start pulse is input to the first driving circuit.

According to a third aspect of the present invention, there is provided the display device according to the first aspect, wherein the first drive circuit is based on a start pulse and a transition of a shift clock. The scan operation is started, and a start pulse is not input to the first drive circuit in a specific frame period.

A display device according to a fourth aspect of the present invention is the display device according to any one of the first to third aspects, wherein the display device is a liquid crystal display device and a specific frame. In a case where the periods are continuous, an inversion operation of inverting the polarity of the voltage applied to the pixel is performed in the middle of a continuous specific frame period.

According to a fifth aspect of the present invention, there is provided the display device according to the fourth aspect, wherein the polarity of the voltage applied to each pixel is alternately inverted in a frame. In this manner, the inversion operation is realized by stopping the scanning operation for an even number of frame periods and then restarting the scanning operation in the next one frame period.

A display device according to a sixth aspect of the present invention is the display device according to any one of the first to fifth aspects, wherein the control for variably setting a parameter relating to the stop of the scanning operation. It is characterized in that means are further provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below by taking an active matrix drive type liquid crystal display device as an example. As is well known, an active matrix driving type liquid crystal display device includes a switching element (TFT) for each liquid crystal pixel defined at an intersection of a plurality of scanning electrodes extending in a row direction and a plurality of signal electrodes extending in a column direction. Provided,
While performing a scanning operation to select scanning electrodes line-sequentially by a gate driver connected to the gate of the TFT,
The TFTs are applied to the liquid crystal pixels corresponding to the selected scanning electrodes from the source driver connected to the source through the signal electrodes.
Is a display device that supplies a video signal through the display.

Embodiment 1 FIG. 1 is a block diagram schematically showing a configuration of an active matrix drive type liquid crystal display device according to Embodiment 1 of the present invention. As shown in FIG. 1, the liquid crystal display device according to the first embodiment includes a liquid crystal panel 1, a source driver 2, a gate driver 3, a timing generator 4, and a microcomputer 5. FIG. 2 is a block diagram showing a specific configuration of the timing generator 4. As shown in FIG. 2, the timing generator 4 includes a delay circuit 41, an edge detection circuit 42, counters 43 and 46, a decoder 44,
47 and output control circuits 45 and 48. FIG. 3 is a block diagram showing a specific configuration of the gate driver 3. As shown in FIG.
Includes a shift register 31, an output circuit 33, and a control circuit 32 inserted between the shift register 31 and the output circuit 33. FIG. 4 is a timing chart showing transition of each signal in the liquid crystal display device according to the first embodiment.

The operation of the liquid crystal display according to the first embodiment will be described below with reference to FIGS. The timing generator 4 starts operation when the power is turned on, and is controlled by a control signal S1 input from the microcomputer 5.
An externally input synchronization signal SYNC (horizontal synchronization signal H
SYNC and the vertical synchronization signal VSYNC), the horizontal start pulse STH, the vertical start pulse STV,
A source driver shift clock CLKH, a gate driver shift clock CLKV, a latch pulse LP, and a video signal polarity inversion signal POL are generated.

More specifically, referring to FIG. 2, an edge detecting circuit 42 detects an edge of the synchronization signal SYNC, and the counter 43 and the decoder 44 use the horizontal start pulse STH, the source driver shift clock CLKH, a latch pulse LP, and a video signal polarity inversion signal POL are generated. The counter 46 and the decoder 47 generate the vertical start pulse STV and the gate driver shift clock CLKV. Decoder 44,
The control signal S1 from the microcomputer 5 is input to 47 so that the timing and the pulse width can be set.

The horizontal start pulse STH, the source driver shift clock CLKH, the latch pulse LP, and the video signal polarity inversion signal POL are output through the output control circuit 45, and the vertical start pulse STV and the gate driver shift clock CLKV are output. It is output via the control circuit 48. The control signal S1 from the microcomputer 5 is input to the output control circuits 45 and 48, and the H level and the L level of each output pulse can be controlled.

The timing generator 4 outputs a video signal DATA input from the outside with a delay of a predetermined time by a delay circuit 41.

The microcomputer 5 outputs the control signal S2 in frame units in synchronization with the vertical synchronization signal VSYNC when changing the frequency division value of the PLL or adjusting the clock phase. The control signal S2 is input to the timing generator 4, and the decoder 47 and the output control circuit 48 included in the timing generator 4 control the non-display control signal OE based on the control signal S2 input from the microcomputer 5.
Generate The non-display control signal OE is output from the output control circuit 48.
Is output via.

Referring to FIG. 1, source driver 2 operates in response to horizontal start pulse STH input from timing generator 4, and distributes signal voltage Vout obtained from video signal DATA to each column of liquid crystal panel 1. Then, the signal voltage Vout is applied to the liquid crystal pixels in the row selected by the gate driver 3 at that time. Specifically, the contents of the data register are transferred to the latch circuit at the rising edge of the latch pulse LP, and the video signal Vout is supplied to the liquid crystal pixels at the falling edge. At this time, the polarity of the signal voltage Vout applied to the liquid crystal pixels is controlled by the video signal polarity inversion signal POL, and AC driving is realized.

The gate driver 3 operates according to the vertical start pulse STV input from the timing generator 4, supplies row selection signals X1 to XN to the liquid crystal panel 1, and sequentially selects each row. Specifically, referring to FIGS. 3 and 4, when non-display control signal OE is at L level, gate driver 3 shift register 31 when gate driver shift clock CLKV rises when vertical start pulse STV is at H level. The scanning operation is started. That is, the row selection signal X1 output from the output circuit 33 in synchronization with the gate driver shift clock CLKV
To XN are sequentially set to the H level.

On the other hand, when the non-display control signal OE is at the H level, the vertical start pulse ST
When V is at H level, the gate driver shift clock CL
Even if KV rises, under the control of the control circuit 32,
Row select signals X1 to XN are always kept at L level. When the row selection signals X1 to XN are at the L level, no on-voltage is applied to the gate of the TFT of each liquid crystal pixel. Therefore, even if the signal voltage Vout is output from the source driver 2, no voltage is applied to the liquid crystal pixels. The video is not rewritten. At this time, since the liquid crystal holds the electric charge in the immediately preceding frame, the liquid crystal panel 1 displays an image in the immediately preceding frame.

As described above, according to the liquid crystal display device of the first embodiment, the scanning operation by the gate driver 3 is stopped by stopping the scanning operation for a specific frame period designated by the control signal S2 from the microcomputer 5, thereby stopping the scanning operation. In the period, the video of the frame before the stop is displayed on the liquid crystal panel 1. Therefore, even if the frequency division value of the PLL is changed or the clock phase is adjusted using the stop period, the image of the frame before the stop is displayed on the liquid crystal panel 1 during the stop period, so that the distorted image is displayed. It can be prevented from being displayed.

Further, since the scanning operation by the gate driver 3 is stopped so that the image of the frame before the stop is displayed on the liquid crystal panel 1, there is no need to provide a frame memory as in the conventional liquid crystal display device. In addition, the circuit scale and cost can be reduced.

Further, since the stop of the scanning operation is controlled by using the microcomputer 5, the parameters relating to the stop of the scanning operation, for example, the timing to start the stop of the scanning operation and the stop period can be variably set by computer control. Can be.

Embodiment 2 FIG. In the liquid crystal display device according to the first embodiment, the gate driver 3 is provided with the control circuit 32, the timing generator 4 generates the non-display control signal OE, and the control circuit 32 outputs the non-display control signal input from the timing generator 4. By stopping the scanning operation based on the OE, the writing of the video signal to the liquid crystal panel 1 was stopped in a specific frame period.

As another method for stopping the scanning operation by the gate driver 3, a control signal S2 from the microcomputer 5 is input to an output control circuit 48 of the timing generator 4, and the output control circuit 48 specifies the control signal S2. The output of the vertical start pulse STV may be controlled to be stopped during the specified specific frame period.

FIG. 5 is a timing chart showing transition of each signal in the liquid crystal display device according to the second embodiment. In the right frame period shown in FIG. 5, the output of the vertical start pulse STV is stopped by the above control of the output control circuit 48. As a result, in the frame period, the row selection signals X1 to XN hold L level, and the scanning operation by the gate driver 3 is not performed.

As described above, according to the liquid crystal display device according to the second embodiment, the vertical start pulse STV is not input to the gate driver 3 instead of using the non-display control signal OE, so that the specific frame period , The scanning operation by the gate driver 3 can be stopped. Thereby, the same effect as that of the liquid crystal display device according to the first embodiment can be obtained.

Embodiment 3 In liquid crystal display devices,
In order to prevent the liquid crystal from deteriorating due to polarization, AC driving must be performed. Therefore, as shown in the timing chart of FIG. 4, the video signal polarity inversion signal POL is controlled so that the polarity of the signal voltage Vout applied to each liquid crystal pixel is alternately inverted in frames. FIG.
In the example shown in (1), when the video signal polarity inversion signal POL is at the H level, the polarity of the signal voltage Vout is negative, and when it is at the L level, it is positive.

In the liquid crystal display devices according to the first and second embodiments, when the scanning operation by the gate driver 3 is stopped continuously for a plurality of frame periods, the signal voltage Vout of the same polarity is applied to the liquid crystal pixels during the stopped period. Since the voltage is continuously applied, the liquid crystal may be deteriorated.
In the third embodiment, a liquid crystal display device that can avoid such a problem will be described.

FIG. 6 is a timing chart for explaining the operation of the liquid crystal display device according to the third embodiment.
Here, paying attention to one certain liquid crystal pixel, five consecutive frame periods F5 out of the frame periods F1 to F11.
In F9 to F9, an example in which the scanning operation is to be stopped is shown. In such a case, if the timing generator 4 outputs the non-display control signal OE at the H level in all of the frame periods F5 to F9, the signal voltage V of the positive polarity is applied to the pixel in the frame periods F4 to F10.
Out is continuously applied, which may cause deterioration of the liquid crystal as described above.

Therefore, in the liquid crystal display device according to the third embodiment, an inversion operation of inverting the polarity of the signal voltage Vout applied to the liquid crystal pixels is performed during the continuous frame periods F5 to F9. Specifically, based on the control signal S2 from the microcomputer 5, the timing generator 4
Outputs the H-level non-display control signal OE in the two frame periods F5 and F6, and then outputs the subsequent frame period F
7 outputs an L-level non-display control signal OE. Thus, the scanning operation is stopped in the frame periods F5 and F6, and the scanning operation is restarted in the frame period F7. As a result, in the frame periods F5 and F6, the signal voltage V
While out is applied, a negative signal voltage Vout is applied in the frame period F7.

Similarly, after outputting the non-display control signal OE at the H level in the frame periods F8 and F9,
10 outputs the L-level non-display control signal OE, so that the negative signal voltage V in the frame periods F8 and F9.
While out is applied, a positive signal voltage Vout is applied in the frame period F10. As described above, in the liquid crystal display device according to the third embodiment, after the scanning operation is stopped for an even number of frame periods, the scanning operation is restarted in the next one frame period, thereby realizing the inversion operation. I have. As a result, although the frequency changes, AC driving of the liquid crystal is realized also in the continuous frame periods F5 to F9.

In the above description, the first embodiment is described.
The case where the invention according to the third embodiment is applied based on the liquid crystal display device according to the above has been described. However, the invention according to the third embodiment is applied based on the liquid crystal display device according to the second embodiment. Can also.

As described above, according to the liquid crystal display device of the third embodiment, even when the frame period in which the scanning operation is stopped is continuous, the voltage is applied to the liquid crystal pixels in the middle of the continuous frame period. By inverting the polarity of the signal voltage Vout, it is possible to prevent the liquid crystal from being deteriorated due to the application of the same polarity voltage for a long time.

[0035]

According to the first aspect of the present invention, even if the frequency division value of the PLL is changed or the clock phase is adjusted using the suspension period, the frame before the suspension is stopped during the suspension period. Since the image is displayed on the screen, it is possible to prevent the disturbed image from being displayed. Moreover, since the image of the frame before the stop is displayed by stopping the scanning operation by the first drive circuit, there is no need to provide a frame memory, and the circuit scale and cost can be reduced. it can.

According to the second aspect of the present invention, by inputting the non-display control signal to the first driving circuit, the scanning operation by the first driving circuit in a specific frame period is performed. Can be stopped.

According to the third aspect of the present invention, the scan operation by the first drive circuit is stopped in a specific frame period by not inputting the start pulse to the first drive circuit. be able to.

According to the fourth aspect of the present invention, even when a specific frame period is continuous, the polarity of the voltage applied to the pixel during the continuous specific frame period is changed. The inversion can prevent the liquid crystal from deteriorating due to the application of a voltage of the same polarity for a long time.

According to the fifth aspect of the present invention, after the scanning operation is stopped for an even number of frame periods, the scanning operation is restarted in the next one frame period, so that the voltage applied to the pixels is increased. Voltage can be inverted.

According to the sixth aspect of the present invention, parameters relating to the stop of the scanning operation, such as the timing to start the stop of the scanning operation and the stop period, are variably set by control means such as a computer. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a timing generator.

FIG. 3 is a block diagram showing a specific configuration of a gate driver.

FIG. 4 is a timing chart showing transition of each signal in the liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 5 is a timing chart showing transition of each signal in the liquid crystal display device according to Embodiment 2 of the present invention.

FIG. 6 is a timing chart for explaining an operation of the liquid crystal display device according to Embodiment 3 of the present invention.

[Explanation of symbols]

1 LCD panel, 2 source driver, 3 gate driver, 4 timing generator, 5 microcomputer, 3
2 control circuit, 46 counter, 47 decoder, 48
Output control circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G02F 1/133 550 G02F 1/133 550 G09G 3/36 G09G 3/36 F-term (Reference) 2H093 NA16 NA33 NA43 NA43 NB16 NC16 NC26 NC29 NC34 NC50 ND34 ND47 ND49 ND54 5C006 AC24 AC25 AC28 AF44 AF51 AF52 AF57 AF71 BC03 BC11 BF49 FA43 FA44 FA52 5C080 AA10 BB05 DD22 FF12 JJ02 JJ04

Claims (6)

[Claims] A switching element provided for each pixel defined at an intersection of a plurality of scanning electrodes and a plurality of signal electrodes;
While performing a scanning operation to select the scanning electrodes line-sequentially by the first driving circuit, the switching element is applied to the pixel corresponding to the selected scanning electrode from the second driving circuit via the signal electrode. A display device for supplying a video signal through the display device, wherein the scanning operation is stopped for a specific frame period, and in the stop period, the image of the frame before the stop is displayed. apparatus. 2. The first driving circuit starts the scanning operation based on a start pulse and a transition of a shift clock. In the specific frame period, the first driving circuit performs the scanning operation regardless of the start pulse. The display device according to claim 1, wherein a non-display control signal for stopping the start is input to the first drive circuit. 3. The first driving circuit starts the scanning operation based on a start pulse and a transition of a shift clock. In the specific frame period, the start pulse is applied to the first driving circuit. The display device according to claim 1, wherein the display device is not inputted. 4. The inverting operation for inverting the polarity of a voltage applied to the pixel during the continuous specific frame period when the specific frame period is continuous, wherein the display device is a liquid crystal display device. Is performed.
The display device according to any one of the above. 5. The display device is controlled so that the polarity of a voltage applied to each pixel is alternately inverted in frames, and the inversion operation is performed after the scanning operation is stopped for an even number of frame periods. 5. The display device according to claim 4, wherein the display device is realized by restarting the scanning operation in a subsequent one frame period. 6. The display device according to claim 1, further comprising control means for variably setting a parameter relating to a stop of the scanning operation.