JPH09107095A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a much higher drivability by considerably increasing the ratio of the quantity of electric charge in an SiGe channel to the quantity of electric charge in a surface Si channel. SOLUTION: In a semiconductor region of a channel region below a gate oxide film 54, a multiple film layer 56 is formed where a first silicon semiconductor layer, a mixed crystal semiconductor layer and a silicon semiconductor layer are alternately formed in the order from the bottom of the gate oxide film 54, and a potential well for the electron hole is formed inside the multiple film layer 56. And at least in an operating state of the field-effect transistor, a potential difference of the base level of a potential well formed in the multiple film layer 56 to the base level of a potential well on the surface of a first silicon semiconductor layer directly below a gate oxide film 54 is made greater.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a p-type mixed crystal channel MOS field effect transistor which constitutes a MOS LSI.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view showing a structure of a conventional p-type channel MOS field effect transistor. FIG.
In one n-type silicon substrate, the source region of 2 p ⁺ diffusion layer, the p ⁺ drain region of the diffusion layer 3, 4 is a gate electrode, 5 denotes a gate oxide film, 6 is the channel. The p-type channel MOS field effect transistor configured as described above forms a state in which a current flows or does not flow between the source region 2 and the drain region 3 depending on whether or not a voltage is applied to the gate electrode 4 to perform switching. Used as an element.

The gate electrode 4 is applied with a negative voltage (drain voltage) applied to the drain region 3 with respect to the source region 2.
A negative voltage (gate voltage) is applied to. When the gate voltage exceeds a certain threshold voltage (V _T ), holes are induced immediately below the gate oxide film 5 and a channel 6 is formed. As a result, holes flow from the source region 2 through the channel 6 to the drain region 3 to form a drain current,
The transistor is turned on. When the gate voltage is equal to or lower than the threshold voltage, the channel 6 is not formed, so that no current flows between the source region 2 and the drain region 3 and the transistor is turned off.

FIGS. 11A and 11B show p shown in FIG.
It is a figure which shows the energy band diagram in the depth direction along the cross section between aa 'lines in the ON / OFF state of the type channel MOS field effect transistor. In FIG.
Reference numerals 7 and 10 denote Fermi levels E _{F of} the gate electrode 4 and the n-type silicon substrate 1, 13 is energy levels of ground state and excited state, 14 is holes in the channel, and 15 is a channel. FIG. 11A shows an off state in which the gate voltage V _G = 0V.

When a gate voltage higher than the threshold voltage V _T is applied to the gate electrode 4 as shown in FIG. 11B, the band is bent on the surface of the n-type silicon substrate 1, and the gate oxide film 5 in the valence band 12 is formed. An energy level 13 is formed immediately below. Holes 14 are induced here and a channel 15 is formed. As a result, when a voltage is applied between the source region 2 and the drain region 3 in FIG. 10, the formed channel 6 is formed.
Through the holes, holes flow from the source region 2 to the drain region 3.

FIG. 12 is a sectional view showing another structure of a conventional p-type channel MOS transistor. In FIG. 12, 16 is an n-type silicon substrate, 17 is a source region, 18
Is a drain region, 19 is a gate electrode, 20 is a gate oxide film, 21 is a silicon semiconductor layer, and 22 is a silicon-germanium (SiGe) mixed crystal semiconductor layer. This type of field effect transistor is disclosed in, for example, the literature (S. Subbanna, et al.
VLSI Technology Symp. Digest.pp.103-104.1991).

P-type channel MOS configured as described above
The transistor utilizes the fact that the mobility of holes in the SiGe mixed crystal semiconductor layer is higher than that in Si. Therefore, in addition to the surface channel of the silicon semiconductor layer, holes having high mobility are formed in the SiGe mixed crystal semiconductor layer. It is intended to obtain a larger drivability (drain current, mutual conductance) by forming a channel consisting of According to the above-mentioned documents, in the structure of FIG. 12, an increase in transconductance of about 70% is observed as compared with the conventional structure of FIG. 10, and it is possible to configure a higher performance LSI. The operation method of the field effect transistor of FIG.
It is similar to the field effect transistor of FIG.

Next, the principle that a channel is formed in the SiGe layer in addition to the surface channel of the silicon semiconductor layer to obtain a larger transconductance will be described with reference to FIG. FIG. 13 shows the potential distribution in the depth direction when cut along the line bb ′ in FIG. 12, and FIG.
Is the OFF state of the gate voltage V _G = 0V, FIG. 13B is the ON state of the gate voltage | V _G1 > threshold value | V _T |
(C) is an ON state in which the gate voltage | V _G | is further increased.

In FIG. 13, 29 and 32 are the Fermi level E _{F of} the gate electrode 23 and the semiconductor region, 34 is a potential well, 35 is a channel in the SiGe mixed crystal semiconductor layer 26,
36 is holes in the SiGe channel 35, 37 is surface Si
The channel, 38, is a hole in the surface Si channel 37. Here, the energy gap E _g of the SiGe mixed crystal semiconductor layer 26 changes depending on the mixed crystal ratio of Si and Ge, but is smaller than the energy gap of Si, and most of the gap difference ΔE _g is valence electrons. It is known that it appears as an energy level difference at the top of the band.

As a result, the potential well 34 for holes shown in FIG. 13A is formed in the valence band of the SiGe mixed crystal semiconductor layer 26. Here, Si that has been conventionally used
Conditions for forming the Ge mixed crystal semiconductor layer 26 (Ge content of about 0.
2, the film thickness is 10 nm).

Under this condition, the base of the energy level formed in the potential well 34 may be considered to be almost at the position of the valence band 33, and the energy level formed in the surface Si channel 37 may be considered. It can be considered that the base is almost equal to the position of the valence band 33 unless the gate voltage is extremely large. When a negative voltage is applied to the gate electrode 23, a depletion layer extends from the surface of the silicon semiconductor layer 25, and when the gate voltage exceeds a certain threshold voltage V _T , the SiGe mixed crystal semiconductor layer 26 is formed as shown in FIG. 13B. Holes 36 are induced inside,
The SiGe channel 35 is formed and the source and drain are turned on. In this state, it is still MOSFE
T is a low drain current region, and SiGe channel 35
It is composed of only holes flowing through.

A channel is formed in the SiGe mixed crystal semiconductor layer 26 prior to the surface of the silicon layer 25 because the potential well 34 causes the channel to be formed in the SiGe mixed crystal semiconductor layer 26 more than in the surface of the silicon semiconductor layer 25. Is due to the low potential with respect to the holes 36. When the negative voltage applied to the gate electrode 23 is further increased, holes 38 are also induced on the surface of the silicon semiconductor layer 25 and a surface Si channel 37 is formed, as shown in FIG. 13C. As a result, MOSFE
The drain current of T is composed of both the holes 38 flowing in the surface Si channel 37 and the holes 36 flowing in the SiGe channel 35. Therefore, the contribution of holes in the SiGe mixed crystal semiconductor layer 26 having a higher mobility than that in Si is added, so that a larger drain current can be obtained as a whole.

[0013]

As described above, the MOSFET using the SiGe channel of FIG.
A drain current larger than that of the normal Si channel MOSFET shown in FIG. 10 can be obtained. In order to increase the drain current flowing in the SiGe channel of this SiGe channel MOSFET, it is effective to increase the mobility of holes, and for that purpose, it is necessary to reduce the effective mass of holes. In order to reduce the effective mass of this hole, the Ge content (X) of the SiGe mixed crystal semiconductor layer must be increased. This is the effective mass of the hole (m
^X ) and the Ge content (X) approximately m ^X = a−
This is because there is a relationship of b · X (a and b are positive constants).

However, the G of the SiGe mixed crystal semiconductor layer is
Increasing the e content causes problems as described below. The relationship between the critical thickness (t _c ) of the SiGe layer and the Ge content (X) is described in the literature (R. People et al. Appl. Lett. V.
ol.47.pp.322, 1985), increasing the Ge content sharply reduces the critical thickness of the SiGe layer capable of strain growth on Si. For example, if the Ge content is 0.5, Si
Since the critical thickness of the Ge layer is about 10 nm, the thickness of the SiGe layer must be less than this. The SiGe channel layer having a large Ge content and a small film thickness becomes a two-dimensional quantum well of a deep potential well, and discrete energy levels are formed. These energy levels and level intervals are determined by the Ge content and the SiGe film thickness. S
A MOSFET using an iGe quantum well as a channel is
Although a larger drain current can be obtained than the normal SiGe channel MOSFET shown in FIG. 12, there are problems as described below.

FIG. 14 shows a SiGe quantum well channel MO.
It is a figure which shows the gate voltage dependence of the band structure of SFET. In FIG. 14, reference numeral 41 is the ground level formed in the SiGe quantum well, and 42 is the first excitation level. here,
For simplicity of explanation, it was assumed that the second excitation level and higher were not formed in the quantum well. In addition, 43 is a hole induced in the quantum well, 44 is a SiGe channel, 45 is a ground level of a potential well formed immediately below the gate oxide film 24, 46 is an excitation level, and 47 is a potential well. The generated holes, 48 are surface Si channels.

In such a structure, the gate voltage | V
Along with the increase of _G |, holes 43 are induced in the ground level 41 of the SiGe quantum well and a SiGe channel is formed, and then the charge amount in the SiGe channel gradually increases (FIG. 14A). When the surface Si channel 48 is subsequently formed, the field effect due to the gate voltage moves the ground level 45 in the potential well immediately below the gate oxide film 24 to a deeper energy position, and the surface Si channel 4 is formed.
Mostly spent in inducing charges in 8. Therefore, it is not effective as an effect of inducing the amount of charges in the SiGe channel 44 (FIG. 14B).

When the gate voltage | V _G | is further increased, the ground level 45 in the potential well becomes deeper than the ground level 41 of the SiGe quantum well, and the increase in the amount of induced charges is almost on the surface. As shown in FIG. 14C, which is in the Si channel 48, and the gate voltage dependence of the hole charge amount induced in each of the surface Si channel and the SiGe channel shown in FIG. Indicates a saturation tendency. Thus, despite the contribution of holes high mobility in SiGe channel, the contribution of holes in the SiGe channel to the total drain current gate voltage | there is a problem that Mau has decreased with increasing | V _G .

The gate voltage | V _G | although SiGe channel high mobility of holes by an increase in the formation, it is needless to say that the surface Si channel of low mobility of holes is not formed is ideal.

Therefore, the present invention has been made to solve the above-mentioned conventional problem, and its purpose is to reduce the contribution of holes in the SiGe channel to the total drain current as the gate voltage increases. It is intended to provide a MOS field effect transistor having higher drivability by suppressing the above phenomenon and significantly increasing the ratio of the charge amount in the SiGe channel to the charge amount in the surface Si channel.

[0020]

In order to achieve such an object, the present invention has a source region, a channel region and a drain region in a semiconductor region, and a gate on the channel region via a gate insulating film. In a field effect transistor having electrodes, a first silicon semiconductor layer, a multilayer film layer in which a mixed crystal semiconductor layer of silicon and germanium and a silicon semiconductor layer are alternately adjacent to each other are formed in this order from directly below the gate insulating film to below. The mixed crystal semiconductor layer formed in the multilayer film layer has a film thickness of 0.5 to 10 nm and a germanium content of 10 to 90%, and the silicon semiconductor layer in the multilayer film layer has a film thickness of 0.5 to 10%. 10 nm, and the multilayer film layer is provided under the first silicon semiconductor layer immediately below the gate insulating film,
A potential difference between the ground level of the potential well formed in the multilayer film layer and the ground level of the potential well on the surface of the first silicon semiconductor layer immediately below the gate insulating film is increased in at least the operating state of the field effect transistor. Is.

According to another invention, in the above-mentioned field effect transistor, the first silicon semiconductor layer, the mixed crystal semiconductor layer of silicon and germanium, and the silicon semiconductor layer are alternately arranged from directly below the gate insulating film to downward. A multilayer film layer adjacent to and a second silicon semiconductor layer are formed,
At least in the operating state, the first portion immediately below the gate insulating film
The control body that acts to reduce the potential difference at the lower end of the second silicon semiconductor layer with respect to the potential at the surface of the silicon semiconductor layer is provided below the second silicon semiconductor layer.

In still another aspect of the invention, in the field effect transistor, at least in an operating state, a depletion layer spreads immediately below the gate insulating film, reaches a lower end of the second silicon semiconductor layer, and is directly below the gate insulating film. An insulating film is arranged below the second silicon semiconductor layer as a control body that acts to reduce the potential difference at the lower end of the second silicon semiconductor layer with respect to the potential at the surface of the first silicon semiconductor layer. A silicon semiconductor region or a conductor region of the insulating film is arranged, and the thickness and the dielectric constant of this insulating film are respectively T ₁ and ε.
₁ , the first silicon semiconductor layer, the multilayer film layer and the second
The thickness of the semiconductor region of the channel region consisting of the three silicon semiconductor layers is T _S , and the dielectric constant ε _{S of} silicon is set. In this operating state of the field effect transistor, there is no insulating film below the second silicon semiconductor layer. , when the thickness of the depletion layer expanding from the first surface of the silicon semiconductor layer when the thickness of the second silicon semiconductor layer assumes a semi-infinite was _{W D, T 1> (W} D -T S ) It is configured so that ε ₁ / ε _S.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIG. 1 shows a structure in which a mixed crystal semiconductor layer of silicon and germanium and a silicon semiconductor layer are alternately arranged for explaining the structure of the field effect transistor according to the first embodiment of the present invention. P-type MO using adjacent semiconductor layers (SiGe / Si multilayer film layers) having a multilayer structure as channels
It is sectional drawing of SFET.

In FIG. 1, 50 is an n-type silicon substrate,
51 is a source region, 52 is a drain region, 53 is a gate electrode, 54 is a gate oxide film, 55 is a silicon semiconductor layer,
56 is a SiGe / Si multilayer film layer. This SiGe /
The sectional structure of the Si multilayer film layer 56 is shown in an enlarged sectional view in FIG. In FIG. 2, 57 is the SiGe first layer, and 58 is Si.
First layer, 59 is SiGe second layer, 60 is Si second layer, 6
1 is the SiGe third layer, 62 is the Si n-1 layer, and 63 is S
The iGe nth layer is a multilayer film of 2n-1 layers in total.
Further, 64 is the film thickness (L _SG ) of the SiGe layer, and 65 is the film thickness (L _Si ) of the Si layer.

In this embodiment, the mixed crystal composition ratio of each SiGe layer is the same, and the film thickness L _SG and each S of each SiGe layer are the same.
Although the film thickness L _{Si of the} i-layer is also constant, each SiGe layer and each S-Ge layer may have different composition ratios of SiGe layers.
It goes without saying that the film thickness may be different for each layer with i.

In this embodiment, the gate electrode 5
The semiconductor region of the lower channel region 3 is formed by the SiGe / Si multilayer film layer 56, and a potential well for holes is formed in the SiGe / Si multilayer film layer 56, and at least in the operating state of the field effect transistor, the SiG
The SiGe layer thicknesses L _SG and Si are set so that the valence band ground level of the e / Si multilayer film 56 is lower than the valence band ground level of the silicon semiconductor layer 55 immediately below the gate oxide film 54.
SiGe / Si multilayer film layer 56 in which the layer thickness L _Si is controlled
Is provided immediately below the silicon semiconductor layer 55.

With such a configuration, the ratio of the charge amount in the SiGe / Si multilayer film intra-layer channel (SiGe channel) to the charge amount in the surface Si channel is significantly increased as compared with the conventional structure, and a larger drivability is achieved. The realization of the p-channel MOSFET having the structure will be described with reference to the energy band diagram in the thermal equilibrium state of FIG. 3 and the energy band diagram of FIG.

FIG. 3A shows an energy band diagram of a p-type SiGe channel MOSFET in a thermal equilibrium state according to the conventional structure. In FIG. 3A, 70 is a gate oxide film, 71 is a silicon semiconductor layer, 72 is a SiGe layer,
73 is an n-type silicon substrate, 74 is a Fermi level E _F in the semiconductor region under the gate oxide film 70, and 75 is a single SiG.
A ground level 76 formed in the quantum well (SQW) formed of the e layer is a valence band E _C of the semiconductor region under the gate oxide film 70.

FIG. 3B shows SiGe / S according to the present invention.
i multilayer film structure, that is, p in thermal equilibrium state using a semiconductor layer of SiGe multiple quantum well structure (MQW) as a channel
In the type MOSFET, the energy band diagram when the Si layer thickness L _Si in the multilayer film structure is large is shown. In FIG. 3B, 77 is the first layer of SiGe, 78
Is SiGe second layer, 79 is SiGe third layer, and 80 is Si
Ge nth layer, 81 is each SiG of the SiGe / Si multilayer film layer
The ground level formed in the quantum well of the e layer, and 82 indicates the film thickness L _Si of the Si layer in the multilayer film layer.

Here, each Si in the SiGe / Si multilayer film layer
When the Ge content and the layer thickness of the Ge layer are the same and the thickness L _Si of each Si layer is sufficiently large, the SiGe / Si multilayer film layer is composed of n isolated SiGe quantum wells. Therefore, the ground level 81 of each quantum well coincides with the ground level 75 of the single SiGe quantum well of FIG.

FIG. 3C shows p in a thermal equilibrium state in which a SiGe multiple quantum well (MQW) according to the present invention is used as a channel.
In the type MOSFET, an energy band diagram when the Si layer film thickness 82 (L _Si ) is small and the quantum wells interfere with each other is shown. In this case, a miniband is formed in the multiple quantum well, and its ground level 83 is shown in FIG.
It moves to a position lower than the ground level 81 in (b). The moving distance is the distance between adjacent SiGe quantum wells (film thickness 8
It becomes larger as 2 (L _Si )) becomes smaller. This can be easily understood from the quantum mechanical calculation.

In this case, however, the above-mentioned SiGe / S
The film thickness of the SiGe layer in the i multilayer film layer is 0.5 to 10 nm. The lower limit of the film thickness of 0.5 nm is the minimum film thickness that can be used as a mixed crystal semiconductor in about 4 atomic layers, and the upper limit of the film thickness of 10 nm allows the SiGe layer to form a significant ground level as a quantum well. The film thickness.

Further, Ge of the SiGe quantum well layer described above is used.
The content rate is 10 to 90%. Lower limit of Ge content 10%
Is the lowest Ge content rate at which a potential well is formed so that holes are captured in the valence band in the SiGe layer, and the upper limit Ge content rate of 90% is the SiGe thickness of 0.5 nm or more.
This is the maximum Ge content of the SiGe layer that can be formed without generating lattice defects such as lattice mismatch dislocations on the Si layer.

Further, the thickness 82 (L _Si ) of the Si layer in the SiGe / Si multilayer film layer is 0.5 to 10 nm. The lower limit of the film thickness of 0.5 nm is about 4 atomic layers of Si.
The minimum film thickness that can exist as a layer, with an upper limit of 1
As shown in FIG. 3C, 0 nm is the maximum film thickness of the Si layer in which mutual interference between SiGe quantum wells in this multilayer film layer and formation of a miniband is observed.

FIG. 4 shows the p-type channel MOSFET of FIG.
5A and 5B are energy band diagrams when a gate voltage of a certain magnitude is applied to the device structures of FIGS. 4A, 4B, and 4C, respectively. ). FIG. 4A shows an energy band diagram in which a gate voltage is applied to the p-type MOSFET having the single SiGe quantum well of FIG. 3A as a channel. This MOS
When a gate voltage is applied to the FET, holes 87 are induced in the ground level 94 of a single SiGe quantum well, and a channel (SiGe channel) 85 is formed in the SiGe layer 72.

At the same time, a potential well is formed just below the gate oxide film 70, and holes 88 are induced in the ground level 84 to form a surface Si channel 86. Under the applied gate voltage, the ground level 84 of the potential well immediately below the gate oxide film 70 is at a lower energy level than the ground level 94 of the single SiGe quantum well, so that it is induced in the surface Si channel 86. Hole 88 is S
There are more holes 87 induced in the iGe channel 85.

FIG. 4B shows an energy band diagram in which a gate voltage is applied to the p-type MOSFET having the SiGe multiple quantum well of FIG. 3B as a channel. This M
When a gate voltage is applied to the OSFET, holes 87 are induced in the ground level 89 of the SiGe multiple quantum well, and the SiGe
Channel 85 is formed.

At the same time, holes 88 are induced in the ground level 90 of the potential well immediately below the gate oxide film 70, and the surface Si channel 86 is formed. In this case as well, under the applied gate voltage, the ground level 90 of the potential well immediately below the gate oxide film 70 is equal to the ground level 8 of the SiGe quantum well.
Since the energy position is lower than 9, the holes 88 induced in the surface Si channel 86 can be converted into the SiGe channel 85.
More.

FIG. 4C shows an energy band diagram in which a gate voltage is applied to the p-type MOSFET having the SiGe multiple quantum well of FIG. 3C as a channel. This M
When a gate voltage is applied to the OSFET, holes 87 are induced in the ground band 91 of the miniband formed in the SiGe multiple quantum well. Further, holes 88 are also induced in the ground level 92 of the potential well immediately below the gate oxide film 70, and the surface Si
A channel 86 is formed.

In this case, under the applied gate voltage, the ground level 92 of the potential well immediately below the gate oxide film 70.
Since the ground level 91 of the SiGe multiple quantum well is at a lower energy position, the number of holes 87 induced in the SiGe channel 93 in the SiGe / Si multilayer film layer is larger than that in the surface Si channel 86. That is, in the present embodiment, S with respect to the charge amount in the surface Si channel 86 is
The ratio of the amount of charges in the iGe channel 93 can be increased as compared with the conventional structure. That is, the SiGe channel 9
Since the contribution of holes having high mobility in 3 can be further increased, it is possible to realize a p-type MOSFET having even greater drivability.

The effects described above will be described in more detail with reference to FIG. FIG. 5 shows the surface Si channel and SiGe.
1 and FIG. 3 for the gate voltage dependence of the respective charge amounts with the SiGe channel in the / Si multilayer film layer.
(C), p-type S according to the present embodiment shown in FIG.
In the case of iGe channel MOSFET, and in FIGS.
4A is a comparison with the case of the p-type SiGe channel MOSFET having the conventional structure shown in FIGS.

In FIG. 5, when the gate voltage | V _G | is increased, in the transistor of the conventional structure, first, Si
A Ge channel is formed and the amount of charge in this channel increases. When the gate voltage | V _G | is further increased, a surface Si channel is formed and the hole charges tend to be saturated in the SiGe channel. Similarly, in the case of the transistor of this embodiment, a SiGe channel is first formed to increase the amount of charge in this channel, and when the gate voltage | V _G | is further increased, a surface Si channel is formed and the SiGe channel The amount of positive hole charges in the above shows a saturation tendency.

However, in the case of the present embodiment, for the reason described below, a larger gate voltage | V _G | for saturation of the hole charge amount in the SiGe channel than in the conventional structure.
Is required, and the value of the saturated charge amount also becomes large. That is, in the present embodiment, by forming the SiGe channel in the SiGe / Si multilayer film layer, the ground level in the quantum well can be made lower than in the case of forming the SiGe channel in the SiGe single layer having the conventional structure. . In other words, in this embodiment, holes are effectively induced in the SiGe channel. Therefore, the gate voltage | V
_By the increase of _G |, by the time the surface Si channel is formed,
As compared with the conventional structure, a larger amount of hole charges will be induced in the SiGe channel.

As a result, the surface S forming the drain current
With respect to the amount of charge in the i channel and the amount of charge in the SiGe channel, in the present embodiment, the ratio of the amount of charge in the SiGe channel to the amount of charge in the surface Si channel can be made larger than that in the conventional structure. And SiGe
Since the contribution of holes having high mobility in the channel can be increased, it is possible to realize a p-type channel MOSFET having even greater drivability.

(Second Embodiment) FIG. 6 is a sectional view of a p-type SiGe channel MOSFET for explaining the structure of the field effect transistor according to the second embodiment of the present invention. In FIG. 6, 101 is an n-type silicon substrate, 102 is a source region, 103 is a drain region, 10
4 is a gate electrode, 105 is a gate oxide film, 106 is a silicon semiconductor layer, 107 is a SiGe / Si multilayer film layer, 10
Reference numeral 8 is a silicon semiconductor layer, and 109 is a potential control body.

In the present embodiment, the semiconductor region of the channel region below the gate electrode 104 is arranged so that the semiconductor regions of the first silicon semiconductor layer 106 and
The potential well for holes is composed of the SiGe / Si multilayer film layer 107 and the second silicon semiconductor layer 108.
It is formed in the iGe / Si multilayer film layer 107, and at least in the operating state of this field effect transistor, the lower end of the second silicon semiconductor layer 108 with respect to the potential of the surface of the first silicon semiconductor layer 106 immediately below the gate oxide film 105 is formed. A potential control body 109 that acts to reduce the potential difference is provided below the second silicon semiconductor layer 108.

With this structure, the ratio of the hole charge amount in the SiGe channel to the hole charge amount in the surface Si channel is greatly increased as compared with the conventional structure, and a p-type channel MOSFET having further drivability is obtained. What can be realized will be described with reference to FIG. 7.

FIG. 7 shows p according to the present embodiment shown in FIG.
2 shows an energy band diagram of a SiGe channel MOSFET of a type. For comparison, FIG. 7 also shows an energy band diagram (FIG. 4C) of the p-type SiGe channel MOSFET according to the first embodiment shown in FIG. FIG.
, 110 is a gate oxide film, 111 is a first silicon semiconductor layer, 112 is a SiGe / Si multilayer film layer, 11
3 is a second silicon semiconductor layer, and 114 is a potential control body.

Further, 115 is the Fermi level E _F of the semiconductor region, and 116 is the p-type MOSF of the first embodiment of FIG.
In the case of the ET structure, the valence band upper level in the semiconductor region, 117 is the valence band upper level in the semiconductor region of the p-type MOSFET structure according to the present embodiment, and 118 is Si.
Potential well in Ge / Si multilayer film, 119 is SiGe channel, 120 is surface Si channel, 121 is SiGe
The holes induced by the channel and 122 are the holes induced by the surface Si channel.

Here, the valence band upper level 116 and the valence band upper level 117 are the same as those of the first silicon semiconductor layer 11.
1, the SiGe / Si multilayer film layer 112 and the second silicon semiconductor layer 113 are formed from the ground level of the valence band. In this embodiment, the first oxide film immediately below the gate oxide film 110 is formed.
The potential control body 114 that acts to reduce the potential difference at the lower end of the second silicon semiconductor layer 113 with respect to the potential of the surface of the second silicon semiconductor layer 111 of FIG.
It is provided under 13.

As a result, in the case of the same surface potential (potential at the surface of the first silicon semiconductor layer 111) as shown in FIG. 7 as compared with the structure of the first embodiment of FIG. In this structure, the potential for holes at the lower end of the second silicon semiconductor layer 113 becomes low, and the potential well 11 is inevitably formed.
The potential of 8 also becomes low. Therefore, the surface Si channel 1
Even if the hole charge amount in 20 is the same, the SiGe channel 11
The hole charge amount in 9 is larger in the structure of the present embodiment than in the structure of the first embodiment of FIG.

That is, in this embodiment, the SiGe channel 11 with respect to the charge amount in the surface Si channel 120 is used.
The ratio of the amount of charge in the SiGe channel 9 can be increased, and the contribution of holes having high mobility in the SiGe channel 119 can be further increased, so that a p-type channel MOSFET having even greater drivability is realized. It will be possible.

(Third Embodiment) FIG. 8 is a cross-sectional view of a p-type SiGe channel MOSFET for explaining the structure of the field effect transistor according to the third embodiment of the present invention. In FIG. 8, 130 is a silicon substrate,
131 is a source region, 132 is a drain region, 133 is a gate electrode, 134 is a gate oxide film, 135 is a silicon semiconductor layer, 136 is a SiGe / Si multilayer film layer, 137 is a silicon semiconductor layer, and 138 is a silicon oxide film.

In this embodiment, the depletion layer spreads immediately below the gate oxide film 134 at least in the operating state.
The upper silicon semiconductor layer 13 reaching the lower end of the lower silicon semiconductor layer 137 and immediately below the gate oxide film 134.
5, a silicon oxide film 138 is arranged below the lower silicon semiconductor layer 137 as a control body that acts to reduce the lower end potential difference of the lower silicon semiconductor layer 137 with respect to the surface potential of the silicon semiconductor film 138. A region 130 (this region may be a conductor region) is arranged.

In this case, the thickness of the silicon oxide film 138 and its dielectric constant are T ₁ and ε ₁ , respectively, and the upper silicon semiconductor layer 135, the SiGe / Si multilayer film layer 136, and the lower silicon semiconductor layer 137 are composed of three layers. When the thickness of the semiconductor region is T _S and the dielectric constant of silicon is ε _S , the lower silicon semiconductor layer 13 is
7 does not have a silicon oxide film 138 below it, and the thickness of the depletion layer spreading from the surface of the upper silicon semiconductor layer 135 is W when the thickness of the lower silicon semiconductor layer 137 is assumed to be semi-infinite.
_{When D} is set, T ₁ > (W _D −T _S ) ε ₁ / ε _S.

In such a structure, the upper silicon semiconductor layer 135, the SiGe / Si multilayer film layer 136, and the lower silicon semiconductor layer 137 are all depleted, and the potential control unit fixes the potential to the silicon oxide film 138. A silicon semiconductor region 130 (or a conductor region) formed by T ₁ > (W _D −T _S ) ε ₁ /
It means that the relation ε _S is satisfied in terms of structural composition.

Here, the above-mentioned T ₁ > (W _D −T _S ).
The meaning of ε ₁ / ε _S is as follows. The lower end of the silicon substrate 130 is usually fixed to the ground potential, and it can be considered that three capacitors are equivalently connected in series below the gate electrode 133. First
Is the capacitance C _ox due to the gate oxide film 134, and
Is the depleted upper silicon semiconductor layer 135, SiGe
/ Si multi-layer film layer 136 and lower silicon semiconductor layer 137, the capacitance C _S (= ε _S ′ / T _S , where ε
_S'is the effective dielectric constant of the three layers, and the third is the capacitance C _O (ε ₁ / T ₁ ) of the silicon oxide film 138. If the channel is not yet formed, the applied gate voltage is divided into these three capacitors.

On the other hand, in the structure of the first embodiment of FIG. 1, it can be assumed that the thickness of the lower silicon semiconductor layer 137 of FIG. 8 is semi-infinite. The thickness of the expanding depletion layer is W _D.
In the present embodiment, will have been suppressed by (W _D -T _S) content of the depletion layer is silicon oxide film 138. The capacitance C _n of inhibiting amount is expressed by _{ε S / (W D -T S} ).

The potential with respect to the holes at the lower end of the lower silicon semiconductor layer 137 in the present embodiment is set to the depth T _S (that is, the present embodiment) from the surface of the upper silicon semiconductor layer in the structure of the first embodiment of FIG. Potential difference with respect to holes at the lower silicon semiconductor layer in the form of (1) and the surface potential of the upper silicon semiconductor layer 135 (equivalently the potential difference applied to the capacitor C _S ).
In order to reduce the capacitance, the capacitance C _O in the structure of the present embodiment needs to be smaller than the capacitance C _n . _{Therefore, C O = ε 1 / T} 1 <C n = ε S / (W D -T S) , and becomes a condition for the foregoing.

In order to make the lower end potential difference of the lower silicon semiconductor layer 137 with respect to the surface potential of the upper silicon semiconductor layer 136 directly below the gate oxide film 134 smaller, the capacitance C _O should be sufficiently smaller than the capacitance C _n. Not to mention good things.

In manufacturing the embodiment of the present invention,
You can do the following: For example, on a SOI substrate such as a SIMOX substrate or a wafer bonded substrate, a lower silicon semiconductor layer, SiGe /
A Si multilayer film layer and an upper silicon semiconductor layer are epitaxially grown, a gate oxide film is formed by thermal oxidation after element isolation, then amorphous silicon doped with impurities is deposited, and the amorphous silicon is processed by photolithography and etching. Use as a gate electrode.
After that, after the source region and the drain region are formed in the same manner as in the usual manufacturing method, the Al wiring is formed to complete the device.

The operating principle of the p-type SiGe channel MOSFET according to the third embodiment will be described with reference to the energy band diagram shown in FIG. 9A and 9B show the potential distribution in the depth direction when cut along the line ee 'in FIG. 8, FIG. 8A shows an off state of the gate voltage V _G = 0V, and FIG. 8B shows a gate. The voltage | V _G |> the threshold voltage | V _T | is in the ON state, and FIG. 8C shows the ON state in which the gate voltage | V _G | is further increased.

In FIG. 8, 140 is a gate electrode and 14
1 is a gate oxide film, 142 is a silicon semiconductor layer, 143
Is a SiGe / Si multilayer film layer, 144 is a silicon semiconductor layer, 145 is a silicon oxide film, and 146 is a silicon substrate. Further, 151, 154 and 148 are a gate electrode 140 and a semiconductor region (silicon semiconductor layer 142, SiG, respectively).
e / Si multilayer film layer 143, silicon semiconductor layer 144),
Fermi level F _E of silicon substrate 146, 150, 15
3, 147 is the bottom level of the conductor (ground level of the conductor) E
_C , 152, 155, and 149 are valence band top levels (ground level of valence band) E _V , 156 is a potential well, and 157 is S
iGe channel, 158 are holes in the SiGe channel,
159 is a surface Si channel, and 160 is a hole in the surface Si channel 159.

In such a structure, SiGe / Si
The energy gap E _g of the multilayer film layer 143 is smaller than the energy gap of Si, and most of the gap difference ΔE _g between the two appears as a valence band upper end energy level difference. ), The electron well 156 for the hole 158 has the SiGe / Si multilayer film layer 143.
Formed within. When a negative voltage is applied to the gate electrode 140, a depletion layer extends from the surface of the silicon semiconductor layer 142, and when the gate voltage exceeds a certain threshold voltage V _T , FIG.
As shown in (b), holes 158 are induced in the SiGe / Si multilayer film layer 143, a SiGe channel 157 is formed, and the source and drain are turned on.

In this state, the MOSFET is still in the low drain current region, but when the negative voltage to the gate is further increased, the silicon semiconductor layer 1 is formed as shown in FIG. 9C.
Holes 160 are also induced on the surface of 42 and a surface Si channel 159 is formed. However, in the present embodiment, unlike the structure of the first embodiment of FIG. 1, since the silicon oxide film 145 exists, the lower end of the silicon semiconductor layer 144 (interface with the silicon oxide film 145) as described above. The electric potential becomes lower than the electric potential at the same depth in the structure of the first embodiment of FIG.

As a result, the SiGe / Si multilayer film layer 143 is formed.
Since the potential of the potential well 156 of the Si gate channel 157 also decreases, the ratio of the hole charge amount in the Si gate channel 157 to the hole charge amount in the surface Si channel 159 is larger than that in the structure of the first embodiment shown in FIG. Become. Therefore, the contribution of holes in SiGe, which has a higher mobility than that in Si, increases, so that a larger drain current can be obtained as compared with the structure of the first embodiment of FIG.

[0067]

As described above, according to the present invention,
By forming the SiGe channel with a SiGe / Si multilayer film layer and by introducing a silicon oxide film directly below the silicon semiconductor layer below the SiGe / Si multilayer film layer, the charge amount in the surface silicon channel is increased. It is possible to significantly increase the ratio of the amount of charge in the SiGe channel to that of the conventional structure, and it is possible to increase the contribution of holes in SiGe, which has a higher mobility than that in Si, so that the drivability is further increased. It is possible to obtain an extremely excellent effect that a p-type channel MOSFET having the above can be realized.

[Brief description of the drawings]

FIG. 1 is a p-type SiG according to a first embodiment of the present invention.
It is sectional drawing which shows the structure of an e-channel MOSFET.

2 is a p-type SiGe channel MOSF shown in FIG.
S formed by alternately admixing a mixed crystal semiconductor layer of silicon and germanium and a silicon semiconductor layer in ET
It is sectional drawing which shows the structure of an iGe channel.

FIG. 3 is a diagram showing an energy band diagram of a p-type MOSFET using a SiGe / Si multilayer film layer according to the present invention as a channel in comparison with an energy band diagram of a conventional p-type MOSFET.

FIG. 4 is a p-type MOSFET using a SiGe / Si multilayer film according to the present invention as a channel and a conventional p-type MOSFET.
It is a figure which shows the energy band diagram when a gate voltage is applied in T.

FIG. 5 shows the gate voltage dependence on the charge amount of each of the surface Si channel and the SiGe channel, and the p-type SiGe channel MO according to the first embodiment shown in FIG.
SFET and conventional p-type SiGe channel M shown in FIG.
It is a figure which compares and shows OSFET.

FIG. 6 is a p-type SiG according to a second embodiment of the present invention.
It is sectional drawing which shows the structure of an e-channel MOSFET.

7 is an energy band diagram of a p-type MOSFET using a SiGe / Si multilayer film layer according to the present invention for a channel shown in FIG. 6 and the SiGe / Si multilayer film according to the first embodiment of the present invention shown in FIG. P-type MO using a layer as a channel
It is the figure compared and shown with the energy band figure of SFET.

FIG. 8 is a p-type SiG according to a third embodiment of the present invention.
It is sectional drawing which shows the structure of an e-channel MOSFET.

9 is a diagram showing a change in energy band with respect to a gate voltage in the p-type SiGe channel MOSFET according to the present invention shown in FIG.

FIG. 10 is a sectional view showing a configuration of a conventional p-type Si channel MOSFET.

FIG. 11 shows a conventional p-type Si channel MO shown in FIG.
It is a figure which shows the energy band figure of SFET.

FIG. 12 Conventional p-type SiGe channel MOSFET
3 is a cross-sectional view showing the configuration of FIG.

13 is an energy band diagram showing holes induced in a surface Si channel and a SiGe channel with respect to a gate voltage in the conventional p-type SiGe channel MOSFET shown in FIG.

FIG. 14 is a diagram showing an energy band diagram in the case where the conventional p-type SiGe channel MOSFET shown in FIG. 12 has a quantum well structure in which the SiGe layer has a large Ge content and the layer thickness is thin.

FIG. 15 is a diagram showing the gate voltage dependence of the charge amount of each of the surface Si channel and the SiGe channel in the conventional p-type SiGe channel MOSFET shown in FIG.

[Explanation of symbols]

1, 16, 27, 50, 73, 101 ... N-type silicon substrate, 2, 17, 51, 102, 131 ... Source region,
3, 18, 52, 103, 132 ... Drain region, 4,
19, 23, 53, 104, 133, 140 ... Gate electrode, 5, 20, 24, 54, 70, 105, 110, 1
34, 141 ... Gate oxide film, 6, 15 ... Channel,
7, 29, 151 ... Fermi level in gate electrode, 8,
28,150 ... lower level of conduction band in gate electrode, 9,3
0, 152 ... Upper level of valence band in gate electrode, 10 ...
Fermi level in n-type silicon substrate, 11 ... conduction band bottom level in n-type silicon substrate, 12 ... valence band top level in n-type silicon substrate, 13 ... energy level, 14 ... in channel Holes 21, 25, 55, 71, 106, 1
08,111,113,135,137,142,14
4 ... Silicon semiconductor layer, 22, 26, 72 ... SiGe
Layers, 31, 153 ... Lower level of conduction band of semiconductor region, 3
2, 39, 74, 115, 154 ... Fermi level of semiconductor region, 33, 40, 76 ... Upper valence band level of semiconductor region, 34, 118, 156 ... Potential well, 35, 44,
85, 93, 119, 157 ... SiGe channel, 3
6, 43, 87, 121, 158 ... Holes in SiGe channel, 37, 48, 86, 120, 159 ... Surface Si
Channel, 38, 47, 88, 122, 160 ... Surface S
Holes in the i-channel, 41, 75, 81, 89, 94 ...
Ground level in SiGe quantum well, 42 ... excitation level in SiGe quantum well, 45, 84, 90, 92 ... ground level in Si potential well, 46 ... pump level in Si potential well, 56, 107, 112, 136, 143
... SiGe / Si multilayer film layer, 57, 77 ... SiGe first
Layer, 58 ... Si second layer, 59, 78 ... SiGe second layer,
60 ... Si second layer, 61, 79 ... SiGe third layer, 62
... Si n-1 layer, 63, 80 ... SiGe n layer 64
... SiGe film thickness L _SG , 65, 82 ... Si film thickness L _SI , 8
3, 91 ... Miniband ground level in SiGe multiple quantum well, 109, 114 ... Potential control body, 116 ... Valence band top level of the device structure of the first embodiment, 117 ... Second
Valence band top level of the device structure of the embodiment of 155 ...
Valence band top level of the device structure of the third embodiment, 13
8, 145 ... Silicon oxide film, 130, 146 ... Silicon substrate, 147 ... Conductor bottom level in silicon substrate, 1
48 ... Fermi level in silicon substrate, 149 ... Bottom valence band level in silicon substrate.

Claims (3)

[Claims] 1. A field effect transistor having a source region, a channel region and a drain region in a semiconductor region, and having a gate electrode on the channel region via a gate insulating film, wherein the channel region below the gate insulating film is formed. In the semiconductor region, a first silicon semiconductor layer and a multilayer film layer in which a mixed crystal semiconductor layer of silicon and germanium and a silicon semiconductor layer are alternately adjacent to each other are formed in this order from directly below the gate insulating film to below, A potential well for holes is formed in the multilayer film layer, and in at least the operating state of the field-effect transistor, the multilayer film with respect to the ground level of the potential well on the surface of the first silicon semiconductor layer immediately below the gate insulating film. A field effect transistor characterized in that a potential difference of a ground level of a potential well formed in a layer is increased. 2. A field effect transistor having a source region, a channel region and a drain region in a semiconductor region, and having a gate electrode on the channel region via a gate insulating film, wherein the field effect transistor extends downward from directly below the gate insulating film. A first silicon semiconductor layer, a multilayer film layer in which a mixed crystal semiconductor layer of silicon and germanium and a silicon semiconductor layer are alternately adjacent to each other, and a second silicon semiconductor layer, and the second silicon semiconductor layer is formed. A field-effect transistor characterized in that a potential control body is provided under a semiconductor layer. 3. The insulating film according to claim 2, wherein an insulating film is arranged below the second silicon semiconductor layer as the potential control body.
A third silicon semiconductor region or a conductor region is disposed under the insulating film, and the thickness and the dielectric constant of the insulating film are T ₁ and ε ₁ , respectively, and the first silicon semiconductor layer, the multilayer film layer, and The thickness of the semiconductor region of the channel region formed of three layers of the second silicon semiconductor layer is T _S , and the dielectric constant of silicon is ε _S. Under the second silicon semiconductor layer in the operating state of this field effect transistor, When the thickness of the depletion layer spreading from the surface of the first silicon semiconductor layer is W _D when the thickness of the second silicon semiconductor layer is assumed to be semi-infinite without the insulating film, T ₁ > (W _D -T _S) field effect transistor, characterized in that it is configured to be ε ₁ / ε _S.