CN117374082A - Short channel planar CMOS integrated circuit structure based on SOI technology - Google Patents
Short channel planar CMOS integrated circuit structure based on SOI technology Download PDFInfo
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- CN117374082A CN117374082A CN202311414167.8A CN202311414167A CN117374082A CN 117374082 A CN117374082 A CN 117374082A CN 202311414167 A CN202311414167 A CN 202311414167A CN 117374082 A CN117374082 A CN 117374082A
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- 238000005516 engineering process Methods 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 18
- 108091006146 Channels Proteins 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000013078 crystal Substances 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 5
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000004088 simulation Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002060 nanoflake Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H01L27/1222—
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- H01L27/127—
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- H01L29/0847—
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a short channel planar CMOS integrated circuit structure based on SOI technology, and relates to the fields of microelectronic technology and Integrated Circuits (ICs). The invention provides a short channel planar CMOS integrated circuit structure based on SOI technology, which can reduce the characteristic size of the silicon planar technology to below 12nm, improve the IC integration level and save the chip area. The invention can greatly reduce the channel length, and can also achieve the channel length below 12nm by using a planar process in combination with the current mature silicon planar process in China, thereby improving the chip integration level.
Description
Technical Field
The present invention relates to the field of microelectronics and integrated circuits.
Background
Integrated circuit technology is rapidly evolving from moore's law [1] It was proposed that, at the beginning, the development of integrated circuits has always followed the scaling principle [2] . With the increasing decrease in device size, the scaling down principle begins to face serious challenges. Accordingly, many researchers have begun considering improving integrated circuits from other angles, thereby continuing moore's law.
FinFET, fin field effect transistor, a technology taught by Hu Zheng, division of Bokrill, california university, 2000The annual formally published papers propose [3] . The main channel region of the FinFET is a fin-shaped semiconductor wrapped by the grid, and compared with a traditional planar CMOS, the semi-ring grid fin-shaped structure of the FinFET increases the control area of the grid on the channel, so that the grid control capability is greatly enhanced, and the short channel effect can be effectively restrained. TSMC began in 2018 and formally mass produced chips with 7nm process nodes, 5nm and 3nm processes were developed in recent years.
When the nodes are further miniaturized, the new problems can occur at the positions of 3nm, 2nm and 1nm after 5nm, and even the 3D FinFET transistor which saves the moore's law originally can not meet the requirements of the limit micro world. The use of nanoflakes instead of fins successfully further reduces short channel effects from smaller dimensions. Thus, a completely new structure is developed-GAA (Gate-All-Around FET). Channel length L at subsequent process node ch It is also difficult to scale down until 2028, L ch Shrink to 9.6nm, thereafter, L ch Will no longer be able to shrink
The invention provides a short channel planar CMOS integrated circuit structure based on SOI technology, which can reduce the characteristic size of the silicon planar technology to below 12nm and has a good inclusion range for the characteristic size of a device. The invention can improve the integration level of the IC and save the area of the chip. The invention can greatly reduce the channel length, and can also achieve the channel length below 12nm by using a planar process in combination with the current mature silicon planar process in China, thereby improving the chip integration level.
Reference to the literature
[1].Moore,Gordon E."Cramming more components onto integrated circuits".Electronics.Retrieved 2016-07-01.
[2].Thompson S,Packan P,Bohr M.MOS scaling:transistor challenges for the 21st century.Intel Technology Journal,1998；pp 1-18.
[3].Chenming Hu,Lee W C,Kedzierski J,et al.FinFET-a self-aligned double-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.
[4].J.P.Colinge,M.H.Gao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator “gate-all-around”MOS device[C].1990IEEE SOS/SOI Technology Conference.
Proceedings.Key West,FL,USA:IEEE,1990:137-138..
Disclosure of Invention
The invention according to claim 1 is a short channel planar CMOS integrated circuit structure based on SOI technology, as shown in fig. 1, characterized in that a silicon single crystal semiconductor region 101 is arranged at the lowest part of the structure, and SiO is arranged at the upper part of the silicon single crystal semiconductor region 101 2 A layer 102; at the SiO 2 Above layer 102 is a CMOS transistor fabricated from this structure; wherein, the two side areas 103 of the NMOS and the PMOS are silicon single crystal semiconductors or insulating substances; a silicon single crystal semiconductor P-type channel region 108 with an NMOS tube in the middle and a silicon single crystal semiconductor N-type channel region 116 with a PMOS tube in the middle; on both sides of the P-type channel region 108 are silicon single crystal semiconductor N-drift regions 106 and 107; on both sides of the N-type channel region 116 are silicon single crystal semiconductor P-drift regions 114 and 115; a silicon single crystal semiconductor n+ source region 104 and n+ drain region 105 distributed outside the N-drift regions 106 and 107; a silicon single crystal semiconductor p+ source region 112 and p+ drain region 113 distributed outside the P-drift regions 114 and 115; above the channel 108 is a gate oxide 109; above the channel 116 is a gate oxide 117; above the gate oxide 109 is a polysilicon electrode 110; above the gate oxide layer 117 is a polysilicon electrode 118; between 103 is SiO of NMOS and PMOS 2 An isolation layer 111; the isolation layer 111 may also be replaced by a PN junction, as shown in FIG. 10.
Further, the length of the P-channel semiconductor region 108 of the NMOS and the length of the N-channel semiconductor region 116 of the pmos are respectively in the range of 2nm to 100nm and 2nm to 100nm, respectively, of the short channel planar CMOS integrated circuit structure based on the SOI technology.
Further, the short channel planar CMOS integrated circuit structure based on the SOI process is characterized in that the length ranges of the n+ source region 104 and the n+ drain region 105 of the NMOS are 2nm to 1000nm, and the length ranges of the p+ source region 112 and the p+ drain region 113 of the pmos are 2nm to 1000nm.
Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the length of the N-drift regions 106 and 107 of NMOS ranges from 2nm to 1000nm, and the length of the P-drift regions 114 and 115 of pmos ranges from 2nm to 1000nm.
Further, the short channel planar CMOS integrated circuit structure based on the SOI process is characterized in that the thickness of the regions 103, 104, 105, 106, 107, 108, 112, 113, 114, 115 and 116 ranges from 2nm to 2000nm.
Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the thickness of the SOI region 102 ranges from 100nm to 10um.
Further, the short channel planar CMOS integrated circuit structure based on the SOI process is characterized in that the doping concentration of the NMOS P-channel semiconductor region 108 is more than 1 order of magnitude higher than that of the N-drift regions 106 and 107, and the doping concentration of the PMOS N-channel semiconductor region 116 is more than 1 order of magnitude higher than that of the P-drift regions 114 and 115.
Further, the short channel planar CMOS integrated circuit structure based on the SOI process is characterized in that the doping concentration of the n+ type source region 104 and the n+ type drain region 105 of the NMOS is higher than that of the P type channel semiconductor region 108 by more than 1 order of magnitude, and the doping concentration of the p+ type source region 112 and the p+ type drain region 113 of the PMOS is higher than that of the N type channel semiconductor region 116 by more than 1 order of magnitude.
Furthermore, the short channel planar CMOS integrated circuit structure based on SOI process is characterized in that the doping concentration range of all layers is 1e14cm -3 -1e22 cm -3 。
The invention provides a short channel planar CMOS integrated circuit structure based on SOI technology, which can reduce the characteristic size of the silicon planar technology to below 12 nm. The invention can greatly reduce the channel length, and can also achieve the channel length below 12nm by using a planar process in combination with the current mature silicon planar process in China, thereby improving the chip integration level.
Drawings
Fig. 1 is a schematic diagram of a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 2 is a process flow of a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention, implementing the structure described in claim 1.
FIG. 3 is a schematic diagram of an NMOS in a short channel planar CMOS integrated circuit structure based on SOI technology, constructed using a Sentaurus TCAD simulation tool.
FIG. 4 is a schematic diagram of a simulation structure of a PMOS in a short channel planar CMOS integrated circuit structure based on SOI technology, which is built by adopting a Sentaurus TCAD simulation tool.
Fig. 5 is a diagram showing the simulation result of the transfer characteristic curve of NMOS in a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 6 is a diagram showing the simulation result of the transfer characteristic curve of PMOS in a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 7 is a graph of simulation results of output characteristics of NMOS in a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 8 is a graph of simulation results of output characteristic curves of PMOS in a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 9 is a diagram of simulation results of an inverter built with a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Fig. 10 is a schematic diagram of another isolation scheme of a short channel planar CMOS integrated circuit structure based on SOI technology according to the present invention.
Detailed Description
Example 1: in order to clearly understand the structure of the short channel planar CMOS integrated circuit based on the SOI technology of the present invention, the present embodiment specifically describes the technological process for implementing the structure described in the technical scheme 1.
A first step, as shown in FIG. 2 (a), of a silicon single crystal;
second, as shown in fig. 2 (b), forming a buried oxide layer on the silicon single crystal by an SOI process;
third, as shown in fig. 2 (c), etching the silicon single crystal to form two silicon single crystal regions;
fourth step, as shown in FIG. 2 (d), an isolation layer SiO is grown between the two silicon single crystal regions 2 ；
Fifth step, as shown in FIG. 2 (e), a layer of SiO is grown 2 ；
A sixth step of performing ion implantation twice, respectively, to become a P-type semiconductor and an N-type semiconductor, as shown in fig. 2 (f);
seventh, as shown in fig. 2 (g), etching SiO2 to form a gate oxide layer;
eighth, as shown in fig. 2 (h), depositing a layer of polysilicon, etching the polysilicon, and aligning the oxide layer;
a ninth step of performing ion implantation twice, respectively, to form an N-drift region and a P-drift region, as shown in fig. 2 (i), wherein a mask and photolithography are used;
and tenth, as shown in fig. 2 (j), performing ion implantation twice respectively to form an n+ source drain region and a p+ source drain region, wherein the source drain region can completely cover the drift region, and a mask and photolithography are adopted.
Example 2: to verify the feasibility of the short channel planar CMOS integrated circuit structure based on SOI technology, the embodiment adopts a Sentaurus TCAD simulation tool to simulate the structure. The simulation structure is shown in fig. 3 and 4. Wherein the channel length is 10nm, the drift region length is 20nm, the source electrode and the drain electrode are 10nm, and the thickness is 5nm.
From the transfer characteristic simulation results of fig. 5 and 6 and the output characteristic simulation results of fig. 7 and 8, it can be seen that the device has excellent transistor characteristics.
From the simulation result of the inverter, as can be seen from fig. 9, the device satisfies the basic characteristics of CMOS and has superior performance.
Claims (10)
1. A short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that a silicon single is arranged at the lowest part of the structureA crystalline semiconductor region 101, siO being formed on the silicon single crystal semiconductor region 101 2 A layer 102; at the SiO 2 Above layer 102 is a CMOS transistor fabricated from this structure; wherein, the two side areas 103 of the NMOS and the PMOS are silicon single crystal semiconductors or insulating substances; a silicon single crystal semiconductor P-type channel region 108 with an NMOS tube in the middle and a silicon single crystal semiconductor N-type channel region 116 with a PMOS tube in the middle; on both sides of the P-type channel region 108 are silicon single crystal semiconductor N-drift regions 106 and 107; on both sides of the N-type channel region 116 are silicon single crystal semiconductor P-drift regions 114 and 115; a silicon single crystal semiconductor n+ source region 104 and n+ drain region 105 distributed outside the N-drift regions 106 and 107; a silicon single crystal semiconductor p+ source region 112 and p+ drain region 113 distributed outside the P-drift regions 114 and 115; above the channel 108 is a gate oxide 109; above the channel 116 is a gate oxide 117; above the gate oxide 109 is a polysilicon electrode 110; above the gate oxide layer 117 is a polysilicon electrode 118; between 103 is SiO of NMOS and PMOS 2 An isolation layer 111.
2. The SOI technology based short channel planar CMOS integrated circuit structure as defined in claim 1 wherein the NMOS P-channel semiconductor region 108 has a length in the range of 2nm to 100nm and the pmos N-channel semiconductor region 116 has a length in the range of 2nm to 100nm.
3. The SOI technology based short channel planar CMOS integrated circuit structure of claim 1 wherein the length of the NMOS n+ source 104 and n+ drain 105 ranges from 2nm to 1000nm, and the length of the pmos p+ source 112 and p+ drain 113 ranges from 2nm to 1000nm.
4. A short channel planar CMOS integrated circuit structure based on SOI technology as claimed in claim 1, wherein the length of the NMOS N-drift regions 106 and 107 ranges from 2nm to 1000nm and the length of the pmos P-drift regions 114 and 115 ranges from 2nm to 1000nm.
5. The SOI technology based short channel planar CMOS integrated circuit structure of claim 1 wherein the thickness of regions 103, 104, 105, 106, 107, 108, 111, 112, 113, 114, 115 and 116 is in the range of 2nm to 2000nm.
6. A short channel planar CMOS integrated circuit structure based on SOI technology as defined in claim 1, wherein the SOI region 102 has a thickness in the range of 100nm to 10um.
7. The SOI process-based short channel planar CMOS integrated circuit structure as claimed in claim 1, wherein the isolation layer 111 is formed of SiO 2 Isolation may also be performed using PN junctions.
8. A short channel planar CMOS integrated circuit structure according to claims 1-7 wherein NMOS P-channel semiconductor region 108 has a doping concentration greater than 1 order of magnitude higher than N-drift regions 106 and 107 and PMOS N-channel semiconductor region 116 has a doping concentration greater than 1 order of magnitude higher than P-drift regions 114 and 115.
9. A short channel planar CMOS integrated circuit structure according to claims 1-7 wherein NMOS n+ source 104 and n+ drain 105 are doped more than 1 order of magnitude higher than P-channel semiconductor 108, PMOS p+ source 112 and p+ drain 113 are doped more than 1 order of magnitude higher than N-channel semiconductor 116.
10. A short channel planar CMOS integrated circuit structure based on SOI technology as defined in claims 1-9, wherein all layers are doped with a concentration in the range of 1e14cm -3 -1e22 cm -3 。
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