CN117374082A - Short channel planar CMOS integrated circuit structure based on SOI technology - Google Patents

Abstract

The invention discloses a short channel planar CMOS integrated circuit structure based on SOI technology, and relates to the fields of microelectronic technology and Integrated Circuits (ICs). The invention provides a short channel planar CMOS integrated circuit structure based on SOI technology, which can reduce the characteristic size of the silicon planar technology to below 12nm, improve the IC integration level and save the chip area. The invention can greatly reduce the channel length, and can also achieve the channel length below 12nm by using a planar process in combination with the current mature silicon planar process in China, thereby improving the chip integration level.

Description

A short-channel planar CMOS integrated circuit structure based on SOI technology

Technical field

The invention relates to the fields of microelectronics technology and integrated circuits.

Background technique

Integrated circuit technology has developed rapidly. Since the introduction of Moore's Law ^[1] , the development of integrated circuits has always followed the principle of scaling down ^[2] . As the size of devices decreases day by day, the scaling principle begins to face serious challenges. Therefore, many scientific researchers began to consider improving integrated circuits from other perspectives to continue Moore's Law.

FinFET, that is, fin field effect transistor, this technology was formally proposed by Professor Hu Zhengming of the University of California, Berkeley, in 2000 ^[3] . The main channel area of FinFET is a fin-shaped semiconductor wrapped by the gate. Compared with traditional planar CMOS, the semi-ring gate fin structure of FinFET increases the control area of the gate to the channel, greatly enhancing the gate control capability. , which can effectively suppress the short groove effect. TSMC began to officially mass-produce 7nm process node chips in 2018, and has developed 5nm and 3nm processes in recent years.

When nodes shrink further, to 3nm, 2nm, and 1nm after 5nm, new problems will arise. Even the 3D FinFET transistors that originally saved Moore's Law will not be able to cope with the requirements of the extreme microscopic world. Replacing fins with nanosheets successfully further mitigates the short channel effect caused by the smaller size. As a result, a new structure came out - GAA (Gate-All-Around FET). In subsequent process nodes, it is difficult to scale down the channel length L _ch . Until 2028, L _ch will be reduced to 9.6nm. After that, L _ch will no longer be able to be reduced.

The present invention proposes a short-channel planar CMOS integrated circuit structure based on the SOI process. The invention can reduce the characteristic size of the silicon planar process to less than 12 nm, and has a good tolerance range for the characteristic size of the device. This invention can improve IC integration and save chip area. This invention can greatly reduce the channel length. Combined with the currently mature silicon planar process in China, the channel length can also be reduced to less than 12nm using planar technology, improving chip integration.

references

[1].Moore,Gordon E."Cramming more components onto integratedcircuits".Electronics.Retrieved 2016-07-01.

[2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21st century. Intel Technology Journal, 1998; pp 1-18.

[3].Chenming Hu,Lee W C,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.

[4].J.P.Colinge,M.H.Gao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator "gate-all-around" MOS device[C].1990IEEE SOS/SOI Technology Conference.

Proceedings. Key West, FL, USA: IEEE, 1990: 137-138..

Contents of the invention

Technical solution 1 of the present invention is a short-channel planar CMOS integrated circuit structure based on SOI technology, as shown in Figure 1. It is characterized in that at the bottom of the structure is a silicon single crystal semiconductor region 101, and in the silicon single crystal The upper part of the semiconductor region 101 is a SiO ₂ layer 102; above the SiO ₂ layer 102 is a CMOS transistor produced by this structure; among them, the two side regions 103 of NMOS and PMOS are silicon single crystal semiconductor or insulating material; the middle is an NMOS transistor. The silicon single crystal semiconductor P-type channel region 108 and the silicon single crystal semiconductor N-type channel region 116 of the PMOS tube; on both sides of the P-type channel region 108 are silicon single crystal semiconductor N-drift regions 106 and 107; on N On both sides of the channel region 116 are silicon single crystal semiconductor P- drift regions 114 and 115; silicon single crystal semiconductor N+ source region 104 and N+ drain region 105 are distributed outside the N- drift regions 106 and 107; silicon single crystal semiconductor The semiconductor P+ source region 112 and P+ drain region 113 are distributed outside the P- drift regions 114 and 115; above the channel 108 is the gate oxide layer 109; above the channel 116 is the gate oxide layer 117; Above the gate oxide layer 109 is the polysilicon electrode 110; above the gate oxide layer 117 is the polysilicon electrode 118; between 103 is the SiO ₂ isolation layer 111 of NMOS and PMOS; this isolation layer 111 can also be replaced by a PN junction. , as shown in Figure 10.

Further, the length range of the P-type channel semiconductor region 108 of the NMOS of the short-channel planar CMOS integrated circuit structure based on the SOI process is 2 nm to 100 nm, and the length range of the N-type channel semiconductor region 116 of the PMOS It is 2nm~100nm.

Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the length range of the N+ source region 104 and N+ drain region 105 of NMOS is 2nm ~ 1000nm, and the P+ source region 112 of PMOS is The length of the P+ drain region 113 ranges from 2 nm to 1000 nm.

Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the length range of the N-drift regions 106 and 107 of NMOS is 2nm ~ 1000nm, and the P-drift regions 114 and 1000nm of PMOS are The length range of 115 is 2nm~1000nm.

Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that area 103, area 104, area 105, area 106, area 107, area 108, area 112, area 113, area 114. The thickness range of region 115 and region 116 is 2nm～2000nm.

Further, the short-channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the thickness of the SOI region 102 ranges from 100nm to 10um.

Furthermore, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the doping concentration of the P-type channel semiconductor region 108 of the NMOS is one order of magnitude higher than that of the N-drift regions 106 and 107. As mentioned above, the doping concentration of the PMOS N-type channel semiconductor region 116 is more than one order of magnitude higher than that of the P-drift regions 114 and 115 .

Further, the short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the doping concentration of the N+ type source region 104 and the N+ type drain region 105 of the NMOS is higher than that of the P-type channel semiconductor region 108 The doping concentration of the P+ type source region 112 and the P+ type drain region 113 of PMOS is more than one order of magnitude higher than that of the N-type channel semiconductor region 116 .

Further, the short-channel planar CMOS integrated circuit structure based on SOI technology is characterized in that the doping concentration range of all layers is 1e14cm ^-3 -1e22 cm ^-3 .

The present invention proposes a short-channel planar CMOS integrated circuit structure based on the SOI process. This invention can reduce the characteristic size of the silicon planar process to less than 12 nm. The present invention is based on the SOI process and adds drift regions in the source and drain regions. , suppressing the short channel effect, thereby improving IC integration and saving chip area. This invention can greatly reduce the channel length. Combined with the currently mature silicon planar process in China, the channel length can also be reduced to less than 12nm using planar technology, improving chip integration.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of a short-channel planar CMOS integrated circuit based on SOI technology of the present invention.

Figure 2 is a process flow of a short channel planar CMOS integrated circuit structure based on SOI process of the present invention, which realizes the structure described in technical solution 1.

Figure 3 is a simulation structural diagram of NMOS in a short-channel planar CMOS integrated circuit structure based on SOI technology of the present invention, which is built using the Sentaurus TCAD simulation tool.

Figure 4 is a simulation structural diagram of PMOS in a short-channel planar CMOS integrated circuit structure based on SOI technology of the present invention, which is built using the Sentaurus TCAD simulation tool.

Figure 5 is a diagram showing the simulation results of the transfer characteristic curve of NMOS in a short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention.

Figure 6 is a diagram illustrating the simulation results of the transfer characteristic curve of PMOS in a short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention.

FIG. 7 is a simulation result diagram of the output characteristic curve of NMOS in a short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention.

FIG. 8 is a simulation result diagram of the output characteristic curve of PMOS in a short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention.

Figure 9 is a simulation result diagram of an inverter built with a short-channel planar CMOS integrated circuit structure based on SOI technology of the present invention.

FIG. 10 is a schematic diagram of another isolation method of a short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention.

Detailed ways

Embodiment 1: In order to clearly understand the short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention, this embodiment specifically introduces the process flow for realizing the structure described in technical solution 1.

The first step, as shown in Figure 2(a), is a silicon single crystal;

In the second step, as shown in Figure 2(b), a primary buried oxide layer is formed on the silicon single crystal through the SOI process;

In the third step, as shown in Figure 2(c), the silicon single crystal is etched to form two silicon single crystal regions;

In the fourth step, as shown in Figure 2(d), an isolation layer SiO ₂ is grown between the two silicon single crystal regions;

The fifth step, as shown in Figure 2(e), grows a layer of SiO ₂ ;

In the sixth step, as shown in Figure 2(f), ion implantation is performed twice to change into P-type semiconductor and N-type semiconductor;

The seventh step, as shown in Figure 2(g), is to etch SiO2 to form a gate oxide layer;

The eighth step, as shown in Figure 2(h), deposits a layer of polysilicon, etches the polysilicon, and aligns it with the oxide layer;

In the ninth step, as shown in Figure 2(i), two ion implantations are performed to form the N-drift region and the P-drift region, using masking and photolithography;

In the tenth step, as shown in Figure 2(j), two ion implantations are performed to form N+ source and drain regions and P+ source and drain regions. The source and drain regions can completely cover the drift region, using masks and photolithography.

Embodiment 2: In order to verify the feasibility of the short-channel planar CMOS integrated circuit structure based on the SOI process of the present invention, this embodiment uses the Sentaurus TCAD simulation tool to simulate the structure. The simulation structure diagram is shown in Figure 3 and Figure 4. The channel length is 10nm, the drift region length is 20nm, the source and drain lengths are 10nm, and the thickness is 5nm.

From the transfer characteristic curve simulation results in Figures 5 and 6, and the output characteristic curve simulation results in Figures 7 and 8, it can be seen that the device has excellent transistor characteristics.

It can be seen from Figure 9 of the inverter simulation results that this device meets the basic characteristics of CMOS and has superior performance.

Claims (10)

1. A short channel planar CMOS integrated circuit structure based on SOI technology is characterized in that a silicon single is arranged at the lowest part of the structureA crystalline semiconductor region 101, siO being formed on the silicon single crystal semiconductor region 101 ₂ A layer 102; at the SiO ₂ Above layer 102 is a CMOS transistor fabricated from this structure; wherein, the two side areas 103 of the NMOS and the PMOS are silicon single crystal semiconductors or insulating substances; a silicon single crystal semiconductor P-type channel region 108 with an NMOS tube in the middle and a silicon single crystal semiconductor N-type channel region 116 with a PMOS tube in the middle; on both sides of the P-type channel region 108 are silicon single crystal semiconductor N-drift regions 106 and 107; on both sides of the N-type channel region 116 are silicon single crystal semiconductor P-drift regions 114 and 115; a silicon single crystal semiconductor n+ source region 104 and n+ drain region 105 distributed outside the N-drift regions 106 and 107; a silicon single crystal semiconductor p+ source region 112 and p+ drain region 113 distributed outside the P-drift regions 114 and 115; above the channel 108 is a gate oxide 109; above the channel 116 is a gate oxide 117; above the gate oxide 109 is a polysilicon electrode 110; above the gate oxide layer 117 is a polysilicon electrode 118; between 103 is SiO of NMOS and PMOS ₂ An isolation layer 111.

2. The SOI technology based short channel planar CMOS integrated circuit structure as defined in claim 1 wherein the NMOS P-channel semiconductor region 108 has a length in the range of 2nm to 100nm and the pmos N-channel semiconductor region 116 has a length in the range of 2nm to 100nm.

3. The SOI technology based short channel planar CMOS integrated circuit structure of claim 1 wherein the length of the NMOS n+ source 104 and n+ drain 105 ranges from 2nm to 1000nm, and the length of the pmos p+ source 112 and p+ drain 113 ranges from 2nm to 1000nm.

4. A short channel planar CMOS integrated circuit structure based on SOI technology as claimed in claim 1, wherein the length of the NMOS N-drift regions 106 and 107 ranges from 2nm to 1000nm and the length of the pmos P-drift regions 114 and 115 ranges from 2nm to 1000nm.

5. The SOI technology based short channel planar CMOS integrated circuit structure of claim 1 wherein the thickness of regions 103, 104, 105, 106, 107, 108, 111, 112, 113, 114, 115 and 116 is in the range of 2nm to 2000nm.

6. A short channel planar CMOS integrated circuit structure based on SOI technology as defined in claim 1, wherein the SOI region 102 has a thickness in the range of 100nm to 10um.

7. The SOI process-based short channel planar CMOS integrated circuit structure as claimed in claim 1, wherein the isolation layer 111 is formed of SiO ₂ Isolation may also be performed using PN junctions.

8. A short channel planar CMOS integrated circuit structure according to claims 1-7 wherein NMOS P-channel semiconductor region 108 has a doping concentration greater than 1 order of magnitude higher than N-drift regions 106 and 107 and PMOS N-channel semiconductor region 116 has a doping concentration greater than 1 order of magnitude higher than P-drift regions 114 and 115.

9. A short channel planar CMOS integrated circuit structure according to claims 1-7 wherein NMOS n+ source 104 and n+ drain 105 are doped more than 1 order of magnitude higher than P-channel semiconductor 108, PMOS p+ source 112 and p+ drain 113 are doped more than 1 order of magnitude higher than N-channel semiconductor 116.

10. A short channel planar CMOS integrated circuit structure based on SOI technology as defined in claims 1-9, wherein all layers are doped with a concentration in the range of 1e14cm ^-3 -1e22 cm ^-3 。