JPH0897730A - Error correction device and method thereof - Google Patents

Abstract

PURPOSE: To improve the error correction performance by providing a generating means detecting an error code of data and generating combination of error flags and a correction means correcting the error code based on the signal from the generating means to the device. CONSTITUTION: Data inputted from an input terminal 1 is inputted to a syndrome calculation circuit 2 and a data memory 3. The syndrome calculation circuit 2 calculates syndromes in an inner code direction and in an outer code direction in parallel and syndromes are written in a syndrome memory 4. When each of the syndromes is not zero, it is judged that an error exists in its code word and flag data are written in a flag memory 5. Furthermore, received data have an error, a system control circuit 8 reads out an inner code flag stored in the flag memory 5 and reads out a syndrome corresponding to the inner code flag from the memory 4 and the syndrome in the inner code direction is inputted to a correction processing circuit 7 via a data bus 9, in which the inner code is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device and method for correcting an error code.

[0002]

2. Description of the Related Art In an apparatus for recording / reproducing or transmitting digital data such as a digital VTR or a codec, it is common to add an error correction code to the data when recording or transmitting the data.

By decoding this error correction code, it is possible to correct an error during recording / reproduction or transmission.

Here, a general error correction process will be described.

Here, a case will be described as an example in which two corrections are performed for both the inner code and the outer code in the 4-bit code configuration for both the inner code parity and the outer code parity in the Reed-Solomon product code configuration.

The error positions are i and j, and their error values are e respectively.
_{If i} and e _j , the syndrome is s ₀ = e _i + e _j s ₁ = e _i α ⁱ + e _j α ^j s ₂ = e _i α ²ⁱ + e _j α ^2j s ₃ = e _i α ³ⁱ + e _j α It will be ^3j .

If s ₀ = s ₁ = s ₂ = s ₃ = 0, it is determined that there is no error in this code.

Next, when s ₀ = s ₁ = s ₂ = s ₃ = 0 is not satisfied, the error locator polynomial σ (z) = 1 + σ ₁ z + σ ₂ z ² is obtained by considering double error. However, σ ₁ and σ ₂ can be obtained by solving the following simultaneous equations.

[0009]

[Outer 1] The root of the obtained error locator polynomial σ (z) is obtained by Chien search or the like. Then, since the reciprocals of the obtained roots are the error locators α ⁱ and α ^j , they are put in the syndrome equation to obtain the error values e _i and e _j .

For example, simultaneous equations of s ₀ and s ₁ are obtained.

From the obtained error locator, the error values e _i and e _j are subtracted from the positions of i and j, respectively, for correction.

If the error is a single byte,

[0013]

[Outside 2] The coefficient determinant of 0 becomes 0, and σ ₁ and σ ₂ cannot be determined. In this case, it is judged as a single error and σ ₂ = 0, and the coefficient σ ₁ of the error locator polynomial σ (z) = 1-σ ₁ z is s ₁ σ ₁ = s
Obtain from step ₂ and make corrections using the same procedure as above.

Here, if no error, double error, and single error could not be corrected, it is assumed that there are three or more errors, no correction is made, and an error correction impossible flag is set.

The above is the correction processing in the inner code direction. Next, the outer code is processed in the same manner as the inner code.

The data for which the correction processing of the inner code and the outer code has been completed is subjected to erasure correction in the outer code direction using the inner code flag as the erasure flag.

First, the number of flags of the inner code is checked.
If the number of inner code flags is 0, it is determined that there is no error in all data, and error correction ends.

If the number of inner code flags is 5 or more, erasure correction cannot be performed because the number of parity is 4, so the error flag is left as it is and the error correction is completed.

When the number of inner code flags is 1 to 4, erasure correction is executed.

Here, the erasure correction process will be described.

The error position is determined from the inner code flag and the outer code flag.

However, since the erasure correction is in the outer code direction, the error position is in the outer code direction.

[0023] The error position, and k, l, m, and n, respectively to the error value _{e k, e l, e m} , and e _n.

The syndrome in the outer code direction is as follows.

S ₀ = e _k + e _l + e _m + e _n s ₁ = α ^k e _k + α ^l e _l + α ^m e _m + α ⁿ e _n s ₂ = α ^2k e _k + α ^2l e _l + α ^2m e _m + α ²ⁿ e _n s ₃ = α ^3k e _k + α ^3l e _l + α ^3m e _m + α ³ⁿ e _n This syndrome has four error values of e _k , e _l , e _m , and e _n that are unknowns and four simultaneous equations. The error value is obtained by solving

Then, the subtraction data is corrected by adding an error value to each error position, and the error correction is completed.

[0027]

However, in the above conventional example, when an error flag is set beyond the correction capability of erasure correction, erasure correction is not performed.

Under the above circumstances, the present invention performs error correction processing using an error correction circuit having the same error correction capability as the conventional one, even if an error flag exceeding the error correction capability occurs. It is an object of the present invention to provide an error correction device and method that further improves the error correction capability.

Other objects and features of the present invention will be apparent from the following specification and drawings.

[0030]

In order to achieve the above object, according to the invention of claim 1, a detecting means for detecting an error code of encoded data and generating an error flag, and the number of the error flags. And counting means, counting means for generating a combination of the error flags according to the output of the counting means, and correction means for correcting the error code based on the generating means. An error correction device is presented.

In order to achieve the above object, in the invention according to claim 2, in claim 1, the correcting means can correct the error code when the error flag is less than a predetermined number, and the generating means includes the error flag. When the number is larger than the predetermined number, a predetermined number of error flag combinations are generated.

To achieve the above object, in the invention according to claim 3, it is determined that the correction result of the correction means is correct when there are at least two or more same correction results by the correction means in claim 1. An error correction device characterized by having a determination means for

In order to achieve the above object, in the invention according to claim 4, an error code of encoded data is detected, an error flag is generated according to the detection result, and the number of generated error flags is counted. An error correction method is characterized in that a combination of the error flags is generated according to the count result, and the error code is corrected based on the generated combination of the error flags.

[0034]

According to the above invention, even if an error flag that exceeds the error correction capability occurs, the error code is corrected by making a combination that makes the error flag within the correction capability, and the correction capability is improved as compared with the conventional case. Can be improved.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An error correction decoding device according to an embodiment of the present invention will be described below.

FIG. 1 is a block diagram of an error correction decoding apparatus according to an embodiment of the present invention.

In FIG. 1, 1 is an input terminal for data such as image data, 2 is a syndrome calculation circuit, 3 is a data memory, 4 is a syndrome memory, 5 is a flag memory, 6 is a combinational circuit, and 7 is a correction processing circuit. , 8 is a system control circuit, 9 is a data bus, and 10 is a flag determination circuit.

In this embodiment, the case where the inner code parity and the outer code parity of the Reed-Solomon product code structure are 4 (see FIG. 2) and both the inner code and the outer code are corrected will be described as an example.

The error correction processing operation of this embodiment will be described below with reference to the flowchart of FIG.

Data having the code structure shown in FIG. 2 to which the outer code and the inner code are added is input from the input terminal 1.

The data input from the input terminal 1 is input to the syndrome calculation circuit 2 and the data memory 3.

The syndromes in the inner code direction and the outer code direction are calculated in parallel by the syndrome calculation circuit 2, and the values of the syndromes (s _{0 to} s ₃ ) are written in the syndrome memory 4. Further, when the syndromes are not 0, it is judged that there is an error in the code word, and the flag data is written in the flag memory 5.

When the flag data is stored in the flag memory 5, it is determined that the input data has an error, and the system control circuit 8 reads the inner code flag stored in the flag memory 5 and corresponds to the inner code flag. The syndrome is read from the syndrome memory 4, and the syndrome in the inner code direction is input to the correction processing circuit 7 via the data bus 9.

The correction processing circuit 7 performs inner code correction according to the syndrome in the inner code direction (S101).

This correction processing calculation will be described.

The error positions are i and j, and their error values are e respectively.
_{If i} and e _j , the syndrome is s ₀ = e _i + e _j s ₁ = e _i α ⁱ + e _j α ^j s ₂ = e _i α ²ⁱ + e _j α ^2j s ₃ = e _i α ³ⁱ + e _j α It will be ^3j .

If s ₀ = s ₁ = s ₂ = s ₃ = 0, it is determined that there is no error in this code (S 102).

Next, when s ₀ = s ₁ = s ₂ = s ₃ = 0 is not satisfied, the error locator polynomial σ (z) = 1 + σ ₁ z + σ ₂ z ² is obtained by considering double error. However, σ ₁ and σ ₂ can be obtained by solving the following simultaneous equations.

[0049]

[Outside 3] The root of the obtained error locator polynomial σ (z) is obtained by Chien search or the like. Then, since the reciprocals of the obtained roots are the error locators α ⁱ and α ^j , they are put in the syndrome equation to obtain the error values e _i and e _j .

For example, simultaneous equations of s ₀ and s ₁ are obtained.

From the obtained error locator, the error values e _i and e _j are subtracted from the positions of i and j for correction (S1).
03).

If the error is a single byte (S10
2),

[0053]

[Outside 4] The coefficient determinant of 0 becomes 0, and σ ₁ and σ ₂ cannot be determined. In this case, it is judged as a single error and σ ₂ = 0, and the coefficient σ ₁ of the error locator polynomial σ (z) = 1-σ ₁ z is s ₁ σ ₁ = s
_Obtained from ₂ and correct it by the same procedure as above (S
103).

Here, if no error, double error, or single error could not be corrected, it is assumed that there are three or more errors, and correction is not performed, and a flag in the inner code direction is set (S1).
06).

The correction process in the inner code direction is performed as described above.

If the answer is not calculated after the correction processing is performed (S104), a flag is set (S).
106).

If this correction process is successful (S10
4), the inner code flag of the corrected portion of the flag memory 5,
The syndrome in the inner code direction in the syndrome memory 4,
The data in the data memory 3 is rewritten (S105).

Further, with respect to the corrected data,
The address in the outer code direction is calculated, and the syndrome memory 4
The syndrome of the inner outer code direction is rewritten (S1).
05).

Next, the system control circuit 8 reads the outer code flag in the flag memory 5, reads the syndrome corresponding to the outer code flag from the syndrome memory 4, and corrects the outer code syndrome via the data bus 9. 7 is input (S107).

By this syndrome in the outer code direction,
The correction processing circuit 7 performs the outer code correction processing similarly to the inner code correction (S108, S109).

In the case of the outer code as well as the inner code, the erasure correction process is performed when the correction process does not give a correct answer.

When the correction process is successful, the outer code flag of the corrected portion of the flag memory 405, the syndrome in the outer code direction in the syndrome memory 4, and the data memory 3
The data inside is rewritten (S111).

Further, for the corrected data, the address in the inner code direction is calculated, the syndrome in the outer code direction in the syndrome memory 4 is rewritten, and the inner code flag which has become syndrome 0 is rewritten (S111).

With the above, correction of the inner code and the outer code is completed.

Next, the data for which the inner code and the outer code have been corrected is subjected to erasure correction in the outer code direction using the inner code flag as the erasure flag (S112).

The system control circuit 8 checks the number of inner code flags in the flag memory 5 (S113). If the number of inner code flags is 0, it is determined that there is no error in all data, and error correction is completed (S113).

If the number of inner code flags is 1 to 4, erasure correction is executed (S113).

Here, the erasure correction process will be described.

The inner code flag and the outer code flag are output from the flag memory 5 to determine the error position.

However, since erasure correction is in the outer code direction, the error position is in the outer code direction.

The error positions are k, l, m and n, and the error values are e _k , e _l , e _m and e _n , respectively.

The syndrome in the outer code direction is as follows.

S ₀ = e _k + e _l + e _m + e _n s ₁ = α ^k e _k + α ^l e _l + α ^m e _m + α ⁿ e _n s ₂ = α ^2k e _k + α ^2l e _l + α ^2m e _m + α ²ⁿ e _n s ₃ = α ^3k e _k + α ^3l e _l + α ^3m e _m + α ³ⁿ e _n This syndrome has four error values of e _k , e _l , e _m , and e _n that are unknowns and four simultaneous equations. The error value is obtained by solving

Then, the data in the data memory 3 is corrected to each error position, and each error value is corrected to the subtracted data.

Further, the error flag in the flag memory 5 is rewritten as no error. Then, the error correction ends.

The data whose error correction has been completed is the data bus 9
Output by.

Next, the case where the number of inner code flags is 5 or more will be described (S113).

In FIG. 4, in the present embodiment, the error remains even after the inner code / outer code error correction, and the number of inner code flags is 5.
FIG. 3 is a diagram showing a data block having a product code configuration that is

The system control circuit 8 inputs the inner code flag data in the flag memory 5 to the combination circuit 6 via the data bus 9.

The combination circuit 6 controls combination of flag data.

Here, a concrete configuration of the combinational circuit 6 is shown in FIG.

In FIG. 5, 101 is a combination generating circuit,
102 is a flag memory, 103 is a combination memory, 304
Is a position / value memory.

In the case of this embodiment, the erasure correction is 4
Since up to 4 errors are corrected (the number of parity is 4), 4 out of 5 error flags are selected for each codeword. That is, in FIG. 4, (Fl
ag 1, Flag 2, Flag 3, Flag 5), (Flag 1, Flag 2, Flag 3,
Flag 4), ..., And 4 error flags among Flag 1 to Flag 5 are selected (S115).

This processing is performed by the combination generating circuit 1 having the configuration of FIG.
01.

This is ₅ C _{4 for} each outer codeword.
(= 5) combinations are required.

The obtained combination and outer code flag are written in the combination memory 103 and the flag memory 102 in FIG. 5, respectively.

Then, erasure correction is performed for each of the outer codes of the five combinations by the combination in the combination memory 303 (S116).

This erasure correction is performed as usual.
Four error positions are determined and four error values are obtained by solving four simultaneous equations.

Next, in the erasure correction by the combination of the error positions, there is a possibility that many erroneous corrections are involved, so it is necessary to check the corrected code (S117).

Here, in order to suppress the error correction probability,
An erasure correction by combination will be described by taking an example of a check method for determining that only the results of a plurality of combinations having the same error position and the same error value can be corrected.

As a result of the erasure correction of each code word by the combination, the error position and the error value obtained for each code word combination are written in the position / value memory 104 in FIG.

In FIG. 4, it is assumed that there are three errors in each outer code word for five inner code flags. In that case,
There are two combinations of inner code flags that include three errors. For example, in the leftmost outer codeword in FIG.
(Flag 1, Flag 2, Flag 3, Flag 4) and (Flag 1, Flag 2, Fla
The error position and error value of g 3, Flag 5) are the same.

Similarly, in other outer codewords, there should be two combinations in which the error position and the error value are the same value.

Therefore, if there is the same error position and the same error value in the same outer code in the position / value memory 104, this value is judged to be correct and this is taken as the erasure correction result.

Further, if the same error position and the same error value do not exist in the same outer code in the position / value memory 304, it is judged that the erasure cannot be corrected (S11).
7).

When erasure correction is possible, the data in the data memory 3 and the error flag in the flag memory 5 are rewritten (S118) and output by the bus 9.

Other methods are also conceivable as the above-mentioned erasure correction code checking means.

For example, a method may be used in which the error flags of the outer codewords are determined and it is determined that only the syndromes of all the codes for which the inner code flag was set are all zero.

The above-described embodiments are merely examples in all respects and should not be construed as limiting.

For example, although the number of parities is 4 in this embodiment, the number of parities is not limited to this.

FIG. 6 shows the processing when the number of parities is n (n: natural number). Here, only the characteristic part of the process when the number of parity is n will be described.

When the number of parities is n, the number of error-correctable numbers is n / 2, which is the number of decimal points truncated.

Erasure can be corrected if the error flag in the inner code direction is n or less.

Therefore, the number of error flags in the inner code direction is m.
When (m ≧ n + 1, m: natural number), erasure correction is executed for each of _m C _n combinations (S201, S2).
02), it is determined whether or not the error position and the error value calculated by the above are two or more in the same outer codeword. If two or more are present, it is determined that the correction is correct, and if they are not present, erasure correction is performed. It may be determined that the correction result is incorrect (S203).

[0105]

As described above, according to the present invention,
An error code of encoded data is detected, an error flag is generated, the number of the error flags is counted, and a combination of the error flags is generated according to the count number.
Since the error code is corrected based on the generated combination of the error flags, even if an error flag exceeding the error correction capability occurs, an error correction process is performed by creating a combination that puts the error flag within the correction capability. The error correction capability can be improved by executing the above.

Further, according to the present invention, the reliability of the error correction processing is high because the correction processing is judged to be correct when there are at least two same error correction results.

[Brief description of drawings]

FIG. 1 is a block diagram of an error correction device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an error code configuration.

FIG. 3 is a flowchart illustrating an error correction process of this embodiment.

FIG. 4 is a diagram showing an example of a data block in which an error flag is set.

5 is a block diagram of a combinational circuit 6 in FIG.

FIG. 6 is a flowchart illustrating an error correction process when the number of parity is n.

Claims (4)

[Claims] 1. A detection means for detecting an error code of encoded data and generating an error flag, a counting means for counting the number of the error flags, and the error flag according to the output of the counting means. An error correction apparatus comprising: a generating unit that generates a combination of the above and a correcting unit that corrects an error code based on the generating unit. 2. The correction means is capable of correcting an error code when the number of error flags is less than or equal to a predetermined number, and the generation means generates a combination of the predetermined number of error flags when the number of error flags is greater than the predetermined number. The error correction device according to claim 1, wherein the error correction device is generated. 3. The error correction apparatus according to claim 2, further comprising a judgment means for judging that the correction result of the correction means is correct when there are at least two same correction results by the correction means. . 4. An error code of encoded data is detected, an error flag is generated according to the detection result, the number of generated error flags is counted, and a combination of the error flags is calculated according to the count result. An error correction method characterized in that an error code is corrected based on a combination of error flags that have occurred.