JP3583903B2 - Error correction device and error correction method - Google Patents

Description

【００３７】
ここで、（１）式はシンドローム多項式の係数Ｓ_ｊ を表示し、（２）式はシンドローム多項式Ｓ（ｘ）そのものを表示している。（１）式におけるαは、ガロア体ＧＦ（２^８ ）の元であり、γ_ｉ はＰＩ系列の符号（シンボル）を表わしている。
【００３８】
次に、ステップＳ４において、誤り位置／数値多項式生成回路１１は、上述のシンドローム多項式Ｓ（ｘ）の係数Ｓ_ｊ をもとに、次式で定義される誤り位置多項式σ（ｘ）および誤り数値多項式ω（ｘ）の係数を求める。
【００３９】
【数２】

【００４０】
ここで、（３），（４）式は誤り位置多項式σ（ｘ）を表わし、（５），（６）式は誤り数値多項式ω（ｘ）を表わしている。ここでＥは誤りの集合を表わし、Ｌ_ｉ は符号上の誤り位置を示している。これらの多項式の係数とは、具体的には次式で示すものである。
【００４１】
【数３】

【００４２】
ここで、上述のシンドローム多項式の係数から、誤り位置多項式および誤り数値多項式の係数を算出するための方法として、ピーターンアルゴリズム、ユークリッドアルゴリズム等が考えられるが、いずれの方法を用いて誤り位置／数値多項式生成回路１１を構成してもよい。
【００４３】
またステップＳ４においては、次数演算回路１２により、誤り位置多項式σ（ｘ）の次数も求められる。
【００４４】
次に、ステップＳ５において、誤りパターン生成訂正回路１３は、誤りパターンを算出して誤り訂正を行なう。誤りのパターンは次式のように求められる。
【００４５】
【数４】

【００４６】
ここで、（７）式を満たすＬ_ｉ はｉ番目の誤り位置を表わしており、おのＬ_ｉ に対して（８）式を計算することにより、誤りパターンｅ_ｉ が求められる。このように（７）式が成り立つか否かを判定してＬ_ｉ を求める方法はチェンサーチ法として知られている。
【００４７】
一方、（８）式におけるσ′（ｘ）はσ（ｘ）の形式微分を表わし、次式によって定義される。
【００４８】
【数５】

【００４９】
上記の（７），（８）および（９）式における、次式に列挙する要素は、誤りパターン生成訂正回路１３により生成される。
【００５０】
【数６】

【００５１】
また、（８）式の誤りパターンｅ_ｉ も誤りパターン生成訂正回路１３により生成される。そして、（７）式が成立する場合にのみ、ステップＳ５においてラインバッファ９に格納されているシンボルの訂正が行なわれる。
【００５２】
上述のチェンサーチ法により誤りパターン生成訂正回路１３で検出された誤り符号の数は誤り数カウンタ１５によりカウントされる。ここで誤り位置／数値多項式生成回路１１によって求められた誤り位置多項式が正確なものであれば、検出される誤りの数と誤り位置多項式の次数とが一致するはずである。したがって、符号長ｎ_ｉ のデータに対してチェンサーチ法による誤り検出が終了した後、ステップＳ６において、比較回路１６により、次数演算回路１２から出力される誤り位置多項式の次数ｄｉｍσと誤りカウンタ１５の出力ｎ_ｅ とを比較することにより、訂正の正誤判定がなされる。
【００５３】
すなわち、ステップＳ６において両者が互いに一致すれば訂正は正しいと判断され、ラインバッファ９の訂正済みの符号（情報シンボル）がバッファメモリ５へ書き戻される（ステップＳ７）。一方、ステップＳ６において両者が互いに一致しなければ、誤りの数が訂正能力を超えていたと判断し、消失数カウンタ１７のカウント値をインクリメントする（ステップＳ９）とともに、そのときのラインカウンタ１８のカウント値であるライン番号を消失位置として消失位置レジスタ１９に格納する（ステップＳ９）。この記憶された消失位置は、後述するＰＯ系列の訂正を行なう際に消失ライン情報として利用される。
【００５４】
以上のように、１ライン分のデータの訂正が終了するか（ステップＳ７）、または訂正不能が判断され消失ライン情報が記憶されると（ステップＳ９）、ラインカウンタ１８はインクリメントされ（ステップＳ１０）、以上のステップＳ１〜Ｓ１０の誤り訂正動作をＰＩ系列の各ラインごとに繰返す。
【００５５】
ステップＳ１１において、ＰＩ系列のすべてのラインに対する訂正が終了したことが判定されると、ステップＳ１２において、ＰＩ系列の検出動作は終了し、消失数カウンタ１７には消失個数が、消失位置レジスタ１９にはＰＯ系列での消失位置が格納されていることになる。
【００５６】
なお、上述のステップＳ１〜Ｓ１２の動作は、シーケンスコントローラ２０によって制御される。
【００５７】
次に、ＰＯ系列（縦方向）のラインでは、上述のＰＩ系列と同様の検出訂正の他に、消失ラインカウンタ１７の消失個数が２ｔ_ｏ （ｔ_ｏ は検出訂正における最大訂正能力）個以下の場合には、消失訂正が可能である。
【００５８】
図４は、図２の誤り訂正装置６を用いたＰＯ系列の消失訂正動作を示すフロー図である。以下に、図２および図４を参照して、この発明の実施の形態による消失訂正動作について説明する。
【００５９】
ＰＯ系列の消失訂正がスタートすると、まず、ステップＳ１０１において、ラインカウンタ１８のカウント値がリセットされる。
【００６０】
次に、ステップＳ１０２において、ＰＯ系列（縦方向）の１ライン分のデータがバッファメモリ５からラインバッファ９に読込まれる。次に、ステップＳ１０３において、シンドローム演算回路１０により、ラインバッファ９からデータが読出され、（１），（２）式で定義されるＰＩ系列のシンドローム多項式Ｓ（ｘ）に対応するＰＯ系列のシンドローム多項式Ｓ（ｘ）の係数Ｓ_ｊ が演算される。この場合、（１）式のγ_ｉ はＰＯ系列のシンボルを表わしているものとする。また、（１），（２）式のｎ_ｉ ，ｔ_ｉ はＰＯ系列の場合ｎ_ｏ ，ｔ_ｏ としてそれぞれ表現されることになる。
【００６１】
次に、ステップＳ１０４において、消失位置／数値多項式生成回路２１は、次の（１０）式で定義される消失位置レジスタ１９の消失位置に基づいて、消失位置多項式を求める。
【００６２】
【数７】

【００６３】
また、消失位置／数値多項式生成回路２１は、シンドローム多項式および（１０）式の消失位置多項式に基づいて、次の（１１）式で定義される消失数値多項式を求める。
【００６４】
【数８】

【００６５】
ここで、消失訂正では、前述のように予めわかっている消失位置以外に符号の誤りが存在すると、正確な訂正を行なうことができなくなり誤訂正となる。消失位置以外に誤りが存在するか否かは、次数演算回路１２によって求められた、消失数値多項式（１１）式の次数と、消失数カウンタ１７の値とを比較することにより、検出することができる。
【００６６】
したがって、ステップＳ１０５において、次式に示す比較が比較回路１６により行なわれる。
【００６７】
【数９】

【００６８】
ここで（１２）式の左辺は、次数演算回路１２で求められた消失数値多項式の次数であり、右辺は消失数カウンタ１７の示す消失個数である。上記（１２）式が成り立てば、消失位置以外に誤りは存在しないものと判断し、誤りパターン生成訂正回路１３は消失訂正を実行する（ステップＳ１０６）。一方、（１２）式が成り立たない場合は、消失位置以外に誤りが存在するため、そのまま消失訂正を実行すると誤訂正が生じてしまう。
【００６９】
上述の（１２）式が成立し、消失訂正が可能な場合には、ステップＳ１０６において、誤りパターン生成訂正回路１３により消失パターンが生成される。
【００７０】
次に、消失位置すなわち次式を満たすＬ_ｉ が求められる。
【００７１】
【数１０】

【００７２】
次に、このＬ_ｉ に対して次式が求められる。
【００７３】
【数１１】

【００７４】
消失パターンε_ｉ を用いて、ラインバッファ９内のシンボルの訂正が行なわれ（ステップＳ１０６）、訂正された符号はバッファメモリ５に書き戻される（ステップＳ１０７）。
【００７５】
一方、上述の（１２）式が成立せず、消失訂正が不可能な場合には、検出訂正を行なう。すなわち、ステップＳ１０３において、シンドローム演算回路１０によって算出されたシンドローム多項式の係数に基づいて、ステップＳ１０８において、誤り位置／数値多項式生成回路１１は、誤り位置多項式および誤り数値多項式を生成し、次数演算回路１２は、誤り位置多項式の次数を算出する。
【００７６】
ステップＳ１０９において、誤りパターン生成訂正回路１３は、誤りパターンを求めるのに必要な下記の値を求める。
【００７７】
【数１２】

【００７８】
ステップＳ１０９において、誤りパターン生成訂正回路１３はさらに、次式を満たすＬ_ｉ に対する誤りパターンを生成し、ラインバッファ９内のシンボルを訂正する。
【００７９】
【数１３】

【００８０】
次に、ステップＳ１１０において、次数演算回路１２から出力される誤り位置多項式の次数と、誤り数カウンタ１５のカウント値とが、比較回路１６で比較される。一致すれば訂正は正しいと判断され、ラインバッファ９内の訂正済みのシンボルがバッファメモリ５へ書き戻される（ステップＳ１１１）。
【００８１】
このようにして、消失訂正または検出訂正により、ＰＯ系列の１ライン分の訂正が終了するごとに、ステップＳ１１２において、ラインカウンタ１８はインクリメントされる。以上のステップＳ１０１〜Ｓ１１２の誤り訂正動作をＰＯ系列の各ラインごとに繰返す。
【００８２】
ステップＳ１１３において、ＰＯ系列のすべてのラインに対する訂正が終了したことが判定されると、ステップＳ１１４においてＰＯ系列の検出訂正は終了する。
【００８３】
なお、以上のステップＳ１０１〜Ｓ１１４の動作は、シーケンスコントローラ２０によって制御される。
【００８４】
以上のように、図２に示した誤り訂正装置６によれば、ＰＩ系列に対しては検出訂正を行ない、ＰＯ系列に対してはラインごとに消失訂正の可否を判断し、そのまま消失訂正を行なえば誤訂正となることが判定された場合には、訂正方式を検出訂正に切換えているので、誤訂正を防止することができる。また、たとえ検出訂正に切換えたとしても、誤りの数がｔ_ｏ 個までであれば訂正を行なうことができるので、全体として訂正能力の向上が期待できる。
【００８５】
【発明の効果】
以上のように、この発明によれば、異なる方向の誤り訂正符号を付加することによって積符号ブロック化されたデータに対し、第１の方向の符号に対してラインごとに検出訂正を実行し、その結果訂正不能であったラインの位置を消失位置として記憶し、第２の方向の符号に対しこの消失位置以外に符号の誤りが存在するか否かをラインごとに判定し、存在しない場合には第２の方向の符号に対して消失訂正を実行し、存在する場合には第２の方向の符号に対して検出訂正を実行するように構成したので、消失位置以外に誤り符号が存在するような場合にも、誤訂正が生じることを防止することができ、誤り訂正能力の向上を図ることができる。
【図面の簡単な説明】
【図１】この発明による誤り訂正装置を用いた光ディスク再生システムの構成を示す概略ブロック図である。
【図２】図１に示した誤り訂正装置の構成を示すブロック図である。
【図３】図２の誤り訂正装置を用いたＰＩ系列の検出訂正動作を示すフロー図である。
【図４】図２の誤り訂正装置を用いたＰ０系列の消失訂正動作を示すフロー図である。
【図５】積符号がデジタルデータに付加される態様を模式的に示す図である。
【図６】積符号が付加されたデータの誤りが訂正されていく過程を模式的に示す図である。
【図７】積符号が付加されたデータの誤りが訂正されていく過程を模式的に示す図である。
【図８】積符号が付加されたデータの誤りが訂正されていく過程を模式的に示す図である。
【符号の説明】
１ 光ディスク
２ 読み出し二値化回路
３ サーボ制御回路
４ 復調デフォーマット回路
５ バッファメモリ
６ 誤り訂正装置
７ 出力インタフェース回路
８ コントローラ
９ ラインバッファ
１０ シンドローム演算回路
１１ 誤り位置／数値多項式生成回路
１２ 次数演算回路
１３ 誤りパターン生成訂正回路
１５ 誤り数カウンタ
１６ 比較回路
１７ 消失数カウンタ
１８ ラインカウンタ
１９ 消失位置レジスタ
２０ シーケンスコントローラ
２１ 消失位置／数値多項式生成回路
２２ 選択回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an error correction device and an error correction method, and more particularly, to an error correction device and an error correction method for sequentially performing error correction of a code in each direction on reception reproduction data divided into product codes in a digital data reception reproduction system. Regarding the correction method.
[0002]
[Prior art]
In an environment in which data is digitally transmitted and processed, such as a digital transmission system and a peripheral device of a computer, an error correction code is generally used in order to improve the reliability of digital data. In particular, recently, with the improvement of the data processing capability on the digital data receiving / reproducing side, an error correction code having a high correction capability has been used. A typical example of such an error correction code is a product code of a long distance code having a large code length and redundancy.
[0003]
FIG. 5 is a diagram schematically illustrating a mode in which such a product code is added to digital data (information symbols). Referring to FIG. 5, a product code is generally a combination of error correction codes in different vertical and horizontal directions, and more specifically, a parity PO of an outer code added in a vertical direction of an information symbol and a parity PO of an outer code. , An information symbol, and a parity PI of an inner code added in the horizontal direction of the PO.
[0004]
As each error correction code, a Reed-Solomon (RS) code capable of performing error correction in byte units is often used. In the example of FIG. 5, the error correction code in the PO direction has a code length n. _o , Information length k _o , Minimum distance d _o And the error correction code in the PI direction has a code length n _i , Information length k _i , Minimum distance d _i RS code.
[0005]
Here, d _i = 2t _i +1, d _o = 2t _o It is assumed that the relationship of +1 holds.
[0006]
Decoding (error correction) on the receiving / reproducing side of the product code-blocked data to which the RS error correction codes in two directions are added as described above is generally performed by repeating the error correction of the code in each direction. . As a method of error correction itself, there are two types of detection correction and erasure correction described below.
[0007]
Detection correction consists of the following three steps:
(1) Find a syndrome polynomial from the received and reproduced code;
(2) calculating an error location polynomial and an error numerical polynomial from the syndrome polynomial;
(3) An error position is obtained from the error position polynomial by the Chien search method, and an error pattern for the position is obtained to perform error correction.
[0008]
On the other hand, erasure correction determines only an error pattern on the assumption that the position (erasure position) of an error code (symbol) is known in advance. That is, as a result of performing error correction (detection correction) of a code in one direction on the product code-blocked data, the position of a line that cannot be corrected (an error code and another code coexist) Is stored as the erasure position, the position of the erroneous code is known in advance when performing the error correction of the code in the other direction, and it is not necessary to find the error position again. That is, in the erasure correction, only the error pattern needs to be obtained, and only one of the erasure numerical polynomials needs to be obtained from the syndrome polynomial as compared with the detection and correction. Therefore, the correction capability is twice that of the detection correction.
[0009]
Such an erasure correction is roughly composed of the following three steps:
(1) Find a syndrome polynomial from the received and reproduced code;
(2) correcting the syndrome polynomial by using the erasure position polynomial obtained from the erasure position to obtain an erasure numerical polynomial;
(3) Error correction is performed for an erasure position by obtaining an erasure pattern.
[0010]
Next, FIGS. 6 to 8 are diagrams schematically showing an example of a process in which errors in data to which a product code is added are being corrected. Each of FIGS. 6 to 8 corresponds to the entire structure of the product-code-blocked data in FIG. 5, and for the sake of simplicity, a PO of parity length 4 and a PI of parity length 6 are added to information symbols. It is assumed that Black portions in the figure indicate erroneous codes (symbols). The hatched portion indicates a code (symbol) in which an error has been corrected.
[0011]
Referring to FIG. 6, first, the above-described detection and correction is performed for each line of a PI sequence composed of horizontal codes. In this detection and correction, for example, it is assumed that up to three error codes can be corrected for each line.
[0012]
Therefore, as shown in FIG. 7, no correction is performed on the first, eighth, and 14th lines in which four or more erroneous codes exist, assuming that the number of error codes exceeds the correction capability. Error codes on other lines are corrected by detection and correction.
[0013]
Next, referring to FIG. 8, the above-described erasure correction is performed for each line of the PO sequence composed of codes in the vertical direction. Here, for each line of the PO sequence, an error remains only on the first, eighth, and 14th horizontal lines that could not be corrected by the PI sequence. Therefore, the erasure correction is performed by determining only the error pattern using the first, eighth, and 14th horizontal lines as the error position (erasure position) without re-determining the error position. In addition, on the 1st, 8th, and 14th lines, which are the erasure positions, there are many non-error codes other than the error codes (empty erasure). The erasure pattern for such a non-error code is zero.
[0014]
As described above, by performing detection correction on horizontal codes and erasure correction on vertical codes, all error codes are corrected.
[0015]
[Problems to be solved by the invention]
As described above, erasure correction has a higher (double) correction capability than detection correction. Therefore, in order to improve the error correction capability using a product code, erasure correction is generally performed on a code of a vertical PO series.
[0016]
However, if an erroneous correction has occurred during the correction of the preceding horizontal PI sequence code, such an error code may not be treated as an erasure position. In other words, even if the operation for correction is correctly performed, the result of the correction may not always be correct, and such error correction may be performed at the erasure position (for example, lines 1, 8, and In the case where there is a line other than 14, a line in which an error code exists other than the erasure position appears in each line of the vertical PO sequence.
[0017]
Therefore, erasure correction does not function correctly for such a line code. As a result, after the erasure correction is performed, there is a possibility that a code that is not corrected remains, or a code that does not need to be corrected is corrected and an error occurs.
[0018]
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and prevents erroneous correction by changing a correction method according to an error state of a code of product-code-blocked data, thereby preventing erroneous correction. It is an object of the present invention to provide an error correction device and an error correction method in which the error correction is improved.
[0019]
[Means for Solving the Problems]
An error correction apparatus according to claim 1 is an error correction apparatus for sequentially performing error correction of a code in each direction to data product-blocked by adding error correction codes in different directions. Means for detecting and correcting the error of the code by calculating the error position and error pattern for each line for the code in the direction, and storing the position of the line that could not be corrected as a result of the detection and correction as an erasure position Means for determining whether there is a code error other than the erasure position for each line for a code in a second direction different from the first direction; If it is determined that there is no erasure, a means for performing an erasure correction for calculating an erasure pattern for the erasure position of the line and correcting a code error, and the presence of a code error other than the erasure position If it is determined, and a means for performing the detection and correction for correcting errors of the code to calculate the error position and error pattern of the line.
[0020]
An error correction device according to a second aspect of the present invention is the error correction device according to the first aspect, wherein the means for determining whether or not there is a code error other than the erasure position is a syndrome for the code in the second direction of the line. Means for calculating an erasure value polynomial using a polynomial and an erasure position polynomial, means for comparing the degree of the calculated erasure number polynomial, and the number of stored erasure positions, and an erasure value based on a result of the comparison. If the degree of the polynomial is smaller than the number of erasure positions, a means for determining that there is no code error other than the erasure position, and otherwise determining means that a code error exists other than the erasure position.
[0021]
An error correction method according to a third aspect is an error correction method for sequentially performing error correction of a code in each direction to data product-blocked by adding an error correction code in a different direction. Calculating the error position and error pattern for each line for the code in the direction and performing detection and correction to correct the code error; and storing the uncorrectable line position as a lost position as a result of the detection and correction. And determining whether there is a code error other than the erasure position for each line for the code in the second direction different from the first direction. If it is determined that there is no erasure, a step of calculating an erasure pattern for the erasure position of the line and performing erasure correction to correct a code error; If There is judged that the present, and a step of performing detection and correction for correcting errors of the code to calculate an error location and an error pattern for each corresponding line.
[0022]
An error correction method according to a fourth aspect of the present invention is the error correction method according to the third aspect, wherein the step of determining whether or not there is a code error other than the erasure position is performed on the code of the line in the second direction. Calculating the erasure numerical value polynomial using the polynomial and the erasure position polynomial; comparing the calculated degree of the erasure numerical value polynomial with the number of the stored erasure positions; If the degree of the polynomial is smaller than the number of erasure positions, it is determined that no code error exists other than at the erasure position; otherwise, it is determined that a code error exists other than at the erasure position.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a schematic block diagram showing a configuration of an optical disk reproduction system as an example of an information reception / reproduction system using an error correction device according to the present invention.
[0024]
Referring to FIG. 1, a signal read from optical disc 1 is converted into a digital signal by read / binarization circuit 2 and then applied to demodulation / deformatting circuit 4, where a product code block of the form shown in FIG. Demodulated into coded data. One block of data in the form shown in FIG. 5 is stored in the buffer memory 5.
[0025]
On the other hand, the servo control circuit 3 servo-controls a drive mechanism (not shown) of the optical disc 1 based on the output of the demodulation / deformatting circuit 4. The operations of the demodulation / deformatting circuit 4 and the servo control circuit 3 are controlled by the controller 8.
[0026]
Further, the controller 8 gives a decoding (error correction) instruction for the data of one block stored in the buffer memory 5 to the error correction device 6. The error correction device 6 performs an error correction described below in detail on the data stored in the buffer memory 5 in response to the instruction. The error-corrected data is read from the buffer memory 5 via the output interface circuit 7 controlled by the controller 8.
[0027]
Next, FIG. 2 is a block diagram showing the configuration of the error correction device 6 shown in FIG. 1 in detail. In FIG. 2, an error correction device 6 includes a line buffer 9 for storing one line of data in the horizontal direction (PI sequence) or the vertical direction (PO sequence) of the product code-blocked data stored in the buffer memory 5. And a syndrome operation circuit 10 for reading data stored in the line buffer 9 and performing a syndrome operation.
[0028]
The syndrome polynomial calculated by the syndrome calculation circuit 10 is provided to an error position / numerical value polynomial generation circuit 11 and an erasure position / numerical value polynomial generation circuit 21. On the other hand, when there is a line having an error code exceeding the correction capability, the count value of the erasure number counter 17 is incremented to indicate the number of erasures, and the line number of the line counter 18 is the line number of the uncorrectable line, that is, the erasure position. It is stored in the position register 19.
[0029]
The error position / numerical polynomial generation circuit 11 calculates the error position / numerical polynomial based on the syndrome polynomial, and the erasure position / numerical polynomial generation circuit 21 calculates the syndrome polynomial and the erasure position stored in the erasure position register 19. The vanishing position / numerical polynomial is calculated based on this.
[0030]
The error position polynomial calculated by the error position / numerical polynomial generation circuit 11 and the erasure numerical polynomial calculated by the erasure position / numerical polynomial generation circuit 21 are given to an order calculation circuit 12, and the order of each position polynomial is calculated. On the other hand, the error position / numerical polynomial calculated by the error position / numerical polynomial generation circuit 11 and the erasure position / numerical polynomial calculated by the erasure position / numerical polynomial generation circuit 21 are also given to the error pattern generation / correction circuit 13 and A pattern and a disappearance pattern are calculated. The error number counter 15 counts the number of errors detected by the error pattern generation and correction circuit 13.
[0031]
The selection circuit 22 selects one of the number of erasures counted by the erasure number counter 17 and the number of errors counted by the error number counter 15 and supplies the selected number to the comparison circuit 16. The comparison circuit 16 compares the counter output given in this way with the order of the position polynomial calculated by the order calculation circuit 12, and gives the comparison result to the sequence controller 20.
[0032]
The sequence controller 20 includes a line buffer 9, a syndrome operation circuit 10, an error position / numerical polynomial generation circuit 11, an error pattern generation and correction circuit 13, an error counter 15, an erasure counter 17, and a line counter 18. , The erasure position register 19, the erasure position / numerical polynomial generation circuit 21, and the selection circuit 22.
[0033]
Next, FIG. 3 is a flowchart showing a PI sequence detection / correction operation using the error correction device 6 of FIG. First, a PI sequence detection / correction operation according to the embodiment of the present invention will be described with reference to FIGS.
[0034]
When detection and correction of the PI sequence are started, first, in step S1, the count values of the line counter 18 and the erasure number counter 17 are reset.
[0035]
Next, in step S2, one line of data in the PI sequence (horizontal direction) is read from the buffer memory 5 into the line buffer 9. Next, in step S3, data is read from the line buffer 9 by the syndrome arithmetic circuit 10, and the coefficient S of the syndrome polynomial S (x) defined by the following equation is calculated. _j Is calculated.
[0036]
(Equation 1)

[0037]
Here, equation (1) is the coefficient S of the syndrome polynomial. _j And equation (2) represents the syndrome polynomial S (x) itself. Α in the equation (1) is a Galois field GF (2 ⁸ ) And γ _i Represents a code (symbol) of the PI sequence.
[0038]
Next, in step S4, the error position / numerical polynomial generation circuit 11 calculates the coefficient S of the syndrome polynomial S (x). _j , The coefficients of the error locator polynomial σ (x) and the error numerical polynomial ω (x) defined by the following equation are obtained.
[0039]
(Equation 2)

[0040]
Here, equations (3) and (4) represent the error locator polynomial σ (x), and equations (5) and (6) represent the error numerical polynomial ω (x). Where E represents a set of errors, L _i Indicates an error position on the code. The coefficients of these polynomials are specifically represented by the following equations.
[0041]
(Equation 3)

[0042]
Here, as a method for calculating the coefficients of the error locator polynomial and the error numerical polynomial from the coefficients of the syndrome polynomial described above, a P-turn algorithm, a Euclidean algorithm, or the like can be considered. The polynomial generation circuit 11 may be configured.
[0043]
In step S4, the order of the error locator polynomial σ (x) is also obtained by the order calculation circuit 12.
[0044]
Next, in step S5, the error pattern generation and correction circuit 13 calculates an error pattern and performs error correction. The error pattern is obtained as follows.
[0045]
(Equation 4)

[0046]
Here, L satisfying the expression (7) _i Represents the ith error position, and each L _i By calculating the expression (8) with respect to _i Is required. As described above, it is determined whether or not Expression (7) holds, and L _i Is known as the Chien search method.
[0047]
On the other hand, σ ′ (x) in Expression (8) represents a formal derivative of σ (x), and is defined by the following expression.
[0048]
(Equation 5)

[0049]
The elements listed in the following equations in the above equations (7), (8) and (9) are generated by the error pattern generation and correction circuit 13.
[0050]
(Equation 6)

[0051]
In addition, the error pattern e in equation (8) _i Is also generated by the error pattern generation and correction circuit 13. Then, only when the equation (7) is satisfied, the symbol stored in the line buffer 9 is corrected in step S5.
[0052]
The number of error codes detected by the error pattern generation and correction circuit 13 by the above-described Chien search method is counted by the error number counter 15. Here, if the error location polynomial obtained by the error location / numerical polynomial generation circuit 11 is accurate, the number of detected errors and the order of the error location polynomial should match. Therefore, the code length n _i After the error detection by the Chien search method is completed for the data of step (c), in step S6, the degree dimσ of the error locator polynomial output from the degree arithmetic circuit 12 and the output n of the error counter 15 are output by the comparison circuit 16 _e Is compared, the correctness of the correction is determined.
[0053]
That is, if they match each other in step S6, it is determined that the correction is correct, and the corrected code (information symbol) of the line buffer 9 is written back to the buffer memory 5 (step S7). On the other hand, if they do not match each other in step S6, it is determined that the number of errors has exceeded the correction capability, the count value of the erasure counter 17 is incremented (step S9), and the count of the line counter 18 at that time is increased. The line number, which is a value, is stored in the erasure position register 19 as an erasure position (step S9). This stored erasure position is used as erasure line information when correcting the PO sequence described later.
[0054]
As described above, when the correction of the data for one line is completed (step S7), or when it is determined that the correction is impossible and the lost line information is stored (step S9), the line counter 18 is incremented (step S10). The above-described error correction operation of steps S1 to S10 is repeated for each line of the PI sequence.
[0055]
In step S11, when it is determined that the correction for all the lines of the PI sequence has been completed, the detection operation of the PI sequence is completed in step S12, Means that the disappearance position in the PO sequence is stored.
[0056]
The operations in steps S1 to S12 are controlled by the sequence controller 20.
[0057]
Next, in the line of the PO series (vertical direction), in addition to the detection and correction similar to the PI series described above, the number of lost lines of the lost line counter 17 is 2t. _o (T _o Is the maximum correction capability in detection and correction), erasure correction is possible.
[0058]
FIG. 4 is a flowchart showing the erasure correction operation of the PO sequence using the error correction device 6 of FIG. The erasure correction operation according to the embodiment of the present invention will be described below with reference to FIGS.
[0059]
When the erasure correction of the PO sequence is started, first, in step S101, the count value of the line counter 18 is reset.
[0060]
Next, in step S102, one line of data in the PO sequence (vertical direction) is read from the buffer memory 5 into the line buffer 9. Next, in step S103, data is read from the line buffer 9 by the syndrome arithmetic circuit 10, and the PO series syndrome corresponding to the PI series syndrome polynomial S (x) defined by the equations (1) and (2). Coefficient S of polynomial S (x) _j Is calculated. In this case, γ in equation (1) _i Represents a PO series symbol. Also, n in the expressions (1) and (2) _i , T _i Is n for PO series _o , T _o Respectively.
[0061]
Next, in step S104, the erasure position / numerical polynomial generation circuit 21 obtains the erasure position polynomial based on the erasure position of the erasure position register 19 defined by the following equation (10).
[0062]
(Equation 7)

[0063]
Further, the erasure position / numerical polynomial generation circuit 21 obtains an erasure numerical polynomial defined by the following equation (11) based on the syndrome polynomial and the erasure position polynomial of the equation (10).
[0064]
(Equation 8)

[0065]
Here, in the erasure correction, if there is a code error other than the previously known erasure position as described above, accurate correction cannot be performed, resulting in erroneous correction. Whether or not there is an error other than the erasure position can be detected by comparing the degree of the erasure numerical polynomial (11) obtained by the degree operation circuit 12 with the value of the erasure number counter 17. it can.
[0066]
Therefore, in step S105, the comparison expressed by the following equation is performed by the comparison circuit 16.
[0067]
(Equation 9)

[0068]
Here, the left side of the equation (12) is the order of the erasure numerical polynomial obtained by the degree calculation circuit 12, and the right side is the number of erasures indicated by the erasure number counter 17. If the above equation (12) holds, it is determined that there is no error other than the erasure position, and the error pattern generation / correction circuit 13 performs erasure correction (step S106). On the other hand, if the equation (12) does not hold, there is an error other than the erasure position, and if the erasure correction is executed as it is, an erroneous correction will occur.
[0069]
If the above equation (12) is satisfied and erasure correction is possible, an erasure pattern is generated by the error pattern generation and correction circuit 13 in step S106.
[0070]
Next, the disappearance position, that is, L satisfying the following equation: _i Is required.
[0071]
(Equation 10)

[0072]
Next, this L _i The following equation is obtained for
[0073]
(Equation 11)

[0074]
Vanishing pattern ε _i Is used to correct the symbols in the line buffer 9 (step S106), and the corrected code is written back to the buffer memory 5 (step S107).
[0075]
On the other hand, if the above equation (12) does not hold and erasure correction is impossible, detection and correction are performed. That is, based on the coefficients of the syndrome polynomial calculated by the syndrome calculation circuit 10 in step S103, the error position / numerical polynomial generation circuit 11 generates an error position polynomial and an error numerical polynomial in step S108. 12 calculates the order of the error locator polynomial.
[0076]
In step S109, the error pattern generation and correction circuit 13 obtains the following values required for obtaining the error pattern.
[0077]
(Equation 12)

[0078]
In step S109, the error pattern generation and correction circuit 13 further performs L _i Is generated, and the symbol in the line buffer 9 is corrected.
[0079]
(Equation 13)

[0080]
Next, in step S110, the degree of the error locator polynomial output from the degree arithmetic circuit 12 and the count value of the error number counter 15 are compared by the comparison circuit 16. If they match, the correction is determined to be correct, and the corrected symbol in the line buffer 9 is written back to the buffer memory 5 (step S111).
[0081]
In this way, each time the correction for one line of the PO sequence is completed by the erasure correction or the detection correction, the line counter 18 is incremented in step S112. The error correction operation of steps S101 to S112 is repeated for each line of the PO sequence.
[0082]
If it is determined in step S113 that the correction for all the lines of the PO sequence has been completed, the detection and correction of the PO sequence ends in step S114.
[0083]
The operations of steps S101 to S114 are controlled by the sequence controller 20.
[0084]
As described above, according to the error correction device 6 shown in FIG. 2, the PI sequence is detected and corrected, and the PO sequence is determined on a line-by-line basis as to whether or not erasure correction is possible. If it is determined that an erroneous correction will be made if the correction is performed, the erroneous correction can be prevented because the correction method is switched to the detection correction. Even if the mode is switched to the detection and correction, the number of errors is t _o Since the correction can be performed up to the number, the improvement of the correction capability can be expected as a whole.
[0085]
【The invention's effect】
As described above, according to the present invention, detection and correction are performed line by line with respect to a code in a first direction with respect to data product-blocked by adding error correction codes in different directions, As a result, the position of the line that could not be corrected is stored as an erasure position, and it is determined for each line whether or not a code error exists in the code in the second direction other than the erasure position. Is configured to perform erasure correction on the code in the second direction and, if present, perform detection and correction on the code in the second direction. Therefore, there is an error code other than the erasure position. In such a case, it is possible to prevent erroneous correction from occurring, and to improve the error correction capability.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a configuration of an optical disk reproduction system using an error correction device according to the present invention.
FIG. 2 is a block diagram showing a configuration of the error correction device shown in FIG.
FIG. 3 is a flowchart showing a PI sequence detection / correction operation using the error correction device of FIG. 2;
FIG. 4 is a flowchart showing an erasure correction operation of a P0 sequence using the error correction device of FIG. 2;
FIG. 5 is a diagram schematically illustrating a mode in which a product code is added to digital data.
FIG. 6 is a diagram schematically illustrating a process in which errors in data to which a product code is added are corrected.
FIG. 7 is a diagram schematically illustrating a process in which errors in data to which a product code is added are corrected.
FIG. 8 is a diagram schematically illustrating a process in which an error in data to which a product code is added is corrected.
[Explanation of symbols]
1 optical disk
2 Readout binarization circuit
3 Servo control circuit
4 Demodulation Deformat Circuit
5 Buffer memory
6 Error correction device
7. Output interface circuit
8 Controller
9 line buffer
10. Syndrome arithmetic circuit
11 Error location / numerical polynomial generation circuit
12th order arithmetic circuit
13 Error pattern generation and correction circuit
15 Error counter
16 Comparison circuit
17 Elimination counter
18 line counter
19 Erasure position register
20 Sequence controller
21 Erasure position / numerical polynomial generation circuit
22 Selection circuit

Claims (4)

An error correction device for sequentially performing error correction of a code in each direction on data product-blocked by adding error correction codes in different directions,
Means for calculating an error position and an error pattern line by line for the code in the first direction, and performing detection and correction for correcting the code error;
As a result of the detection and correction, means for storing the position of the uncorrectable line as a lost position,
Means for determining, for a code in a second direction different from the first direction, whether there is a code error other than the erasure position for each line,
When it is determined that there is no code error other than the erasure position, means for performing erasure correction to correct a code error by calculating an erasure pattern for the erasure position of the line,
Means for calculating an error position and an error pattern of the line and performing detection and correction for correcting the code error when it is determined that a code error exists other than the erasure position. . Means for determining whether there is a code error other than the erasure position,
Means for calculating an erasure numerical polynomial using a syndrome polynomial and an erasure position polynomial for the code in the second direction of the line;
Means for comparing the degree of the calculated erasure numerical polynomial and the number of the stored erasure positions,
Based on the result of the comparison, if the degree of the erasure numerical polynomial is smaller than the number of the erasure positions, it is determined that there is no code error other than the erasure position. 2. The error correction device according to claim 1, further comprising: means for determining that an error exists. An error correction method for sequentially performing error correction of a code in each direction on data product-blocked by adding error correction codes in different directions,
Calculating the error position and error pattern line by line for the code in the first direction and performing detection and correction to correct the code error;
As a result of the detection and correction, storing the position of the uncorrectable line as a lost position,
Determining, for a code in a second direction different from the first direction, whether or not there is a code error other than the erasure position for each line;
If it is determined that there is no code error other than the erasure position, executing erasure correction to correct the code error by calculating the erasure pattern for the erasure position of the line,
Performing a detection and correction to correct the code error by calculating an error position and an error pattern of the line when it is determined that a code error exists other than the erasure position. . The step of determining whether there is a code error other than the erasure position,
Calculating an erasure numerical polynomial using a syndrome polynomial and an erasure position polynomial for the code in the second direction of the line;
Comparing the degree of the calculated erasure numerical polynomial with the number of the stored erasure positions,
Based on the result of the comparison, if the degree of the erasure numerical polynomial is smaller than the number of the erasure positions, it is determined that there is no code error other than the erasure position. Determining the presence of an error.

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