JPH0897366A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a rectifying circuit with a minimum of leak current where no parasitic bipolar transistor is forward biased. CONSTITUTION: When a node n1 provides potential higher than a node n2, a P-type field-effect transistor PI is turned in an OFF state while a P-type field- effect transistor is turned in an ON state so that the potential of the node n1 may be conveyed to a node n3 by way of the field-effect transistor P2. On the contrary, when the node n2 is in a higher potential than the node n1, the P-type field-effect (transistor P1 is turned in an ON state while the P-type field-effect transistor P2 is turned in an OFF state so that the potential of the node n2 may be conveyed to the node n3 by way of the P-type field-effect transistor P1 where the potential of an N-type well 10 is turned to be higher, thereby preventing a parasitic transistor from being forward-biased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device used as a circuit in a charge pump circuit or the like.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a specific example of a charge pump circuit for generating a voltage higher than a power supply voltage.

In FIG. 6, the charge pump circuit includes rectifier circuits D1 and D2 and capacitors C1 and C2.

At the node n1, one electrode of the capacitor C1 is connected to the output of the diode D1 in the forward bias direction and the input of the diode D2 in the forward bias direction.
Then, the one electrode of the capacitor C2 and the output of the diode D2 in the forward bias direction are connected, and the terminal n11 to which the input of the diode D1 in the forward bias direction is connected is connected to the power supply voltage V1.
The control signal CLK1 is input to the other electrode of the capacitor C1 connected to cc, and the other electrode of the capacitor C2 is grounded.

A power supply voltage is applied to the terminal n11, and a voltage higher than the power supply voltage is charged by controlling the control signal CLK1 using the capacitors C1 and C2.

The rectifier circuits D1 and D2 are composed of diode-connected N-type field effect transistors or diode-connected P-type field effect transistors.

FIG. 7 is a circuit diagram showing the diode-connected N-type field effect transistor.

FIG. 8 is a circuit diagram showing the diode-connected P-type field effect transistor.

7 and 8, terminals n1 and n2
Are the nodes n1 of the rectifier circuit D2 in FIG.
It corresponds to n2, and also corresponds to the terminal n11 and the node n1 of the rectifier circuit D1.

[0010]

However, in the diode-connected P-type field effect transistor of FIG. 8, when the source potential becomes high, the flow of electrons from the source to the back surface of the substrate hardly occurs due to the substrate bias effect. However, there is a problem that the threshold voltage becomes high and the boosting efficiency of the charge pump circuit becomes poor.

FIG. 9 is a sectional view of the vertical structure of the diode-connected P-type field effect transistor of FIG.

In FIG. 9, the diode-connected P-type field effect transistor includes a P-type substrate 200 (GND (ground) potential), an N-type well 100 (same potential as the node n2), and a P ⁺ layer source ( Same potential as node n1), and P
The drain of the ⁺ layer (the same potential as the node n2), the gate (the same potential as the node n2), and the N ⁺ impurity layer (the same potential as the node n2) are included.

An N-type well 100 is formed on a P-type substrate 200, a source (P ⁺ ) formed on the N-type well 100 is connected to a node n1, and a drain (P ⁺ ) and a gate are connected to a node n2. ing. At this time, a parasitic bipolar transistor is formed in which the source (P ⁺ ), N-type well 100 and P-type substrate 200 correspond to the emitter, base and collector electrodes, respectively.

When the diode-connected P-type field effect transistor is forward biased and the node n1 is at a higher potential than the N-type well 100, the parasitic bipolar transistor is forward biased and a base current flows.
In response to this, a collector current flows, and the node n1 to GN
P-type substrate 200 connected to D (grounded)
A leak current flows.

There is a problem that the boosting efficiency of the charge pump circuit becomes rough due to the leak current.

The present invention has been made to solve the above problems, and in a rectifier circuit of a charge pump circuit using a P or N type field effect transistor as a diode, the parasitic bipolar transistor is forward biased. To prevent it from being grounded and grounded to a P-type or N-type
An object of the present invention is to provide an improved rectifier circuit of a charge pump circuit, which has a very small leak current to a mold substrate.

[0017]

According to another aspect of the present invention, there is provided a semiconductor device having a first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the first conductivity type semiconductor substrate, and a second conductivity type. A first conductivity type first field effect transistor formed on the type impurity region, one electrode of the first conductivity type first field effect transistor is connected to a first potential, and the other electrode and the control electrode are second. Connected to the electric potential. Then, the first and second impurity regions are formed on the second conductivity type impurity region.
Selective application means for selectively applying the higher one of the potentials to the second conductivity type impurity region is provided.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the selective applying means is the first device.
A first potential type second field effect transistor provided between a first potential type supply terminal for supplying a potential and a second conductivity type impurity region; a second potential type supply terminal for supplying a second potential;
A first conductivity type third field effect transistor provided between the first conductivity type second field effect transistor and a control electrode of the first conductivity type second field effect transistor, the control electrode being connected to the second potential supply terminal; The control electrode of the conductivity type third field effect transistor is connected to the first potential supply terminal.

A semiconductor device according to a third aspect of the present invention is formed on a first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the first conductivity type semiconductor substrate, and a second conductivity type impurity region. And a first field effect transistor of the first conductivity type, wherein one electrode of the first field effect transistor of the first conductivity type is connected to the first potential and the other electrode is connected to the second potential. Further, a selective applying means for selectively applying the higher one of the first and second potentials to the second conductivity type impurity region is provided, and the selective applying means applies the first potential to A first conductivity type second field effect transistor provided between a first potential supply terminal for supplying and a second conductivity type impurity region, a second potential supply terminal for supplying a second potential and a second conductivity type impurity region. And a third field effect transistor of the first conductivity type, wherein a control electrode of the second field effect transistor of the first conductivity type is provided at a second potential supply terminal. The control electrode of the transistor is connected to the first potential supply terminal. Furthermore, the first
And a third potential preparation means for outputting a third potential which is the higher one of the second potential and the ground potential, and the third potential preparation means is configured such that the third potential is the first conductivity. Type field effect transistor is connected to the control electrode.

[0020]

In the semiconductor device according to the first aspect of the present invention, since the higher potential of the first and second potentials is applied to the impurity region of the second conductivity type, the impurity region of the second conductivity type is The higher one of the first and second potentials.

In the semiconductor device according to claim 2 of the present invention, when the first potential is higher, the first conductivity type second field effect transistor is turned on and the first conductivity type third field effect transistor is turned off, Since the first potential is applied to the second conductivity type impurity region, the second conductivity type impurity region has the first potential. On the other hand, when the second potential is higher, the first conductivity type third field effect transistor is turned on, the first conductivity type second field effect transistor is turned off, and the second potential is applied to the second conductivity type impurity region. Therefore, the second conductivity type impurity region has the second potential. That is, the second conductivity type impurity region is the first
And the higher one of the second potentials.

In the semiconductor device according to claim 3 of the present invention, when the first potential is higher, the first conductivity type second field effect transistor is turned on, the first conductivity type third field effect transistor is turned off, and the first conductivity type third field effect transistor is turned off. Since the potential is applied to the second conductivity type impurity region, the second conductivity type impurity region has the first potential. on the other hand,
When the second potential is higher, the first conductivity type third field effect transistor is turned on, the first conductivity type second field effect transistor is turned off, and the second potential is applied to the second conductivity type impurity region. The second conductivity type impurity region has the second potential. Further, since the control electrode of the first conductivity type first field effect transistor is applied with the higher one of the first and second potentials or the third potential which is the ground potential, the potential of the control electrode is Swing between the higher one of the first and second potentials and the ground potential.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device of the present invention applied to a rectifier circuit used in a charge pump circuit or the like will be described below with reference to the drawings. (1) First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a rectifier circuit used in a charge pump circuit or the like using the semiconductor device of the present invention.

In FIG. 1, the rectifier circuit includes P-type field effect transistors P1 and P2. At the node n1, the gate of the P-type field effect transistor P1 and the source of the P-type field effect transistor P2 are connected, and at the node n2, P
The source of the P-type field effect transistor P1 is connected to the gate of the P-type field effect transistor P2, and the drain of the P-type field effect transistors P1 and P2 is connected to the N-type well 100 at the node 3.

Hereinafter, this rectifier circuit is called a champion circuit. When the node n1 is at a higher potential than the node n2, the P-type field effect transistor P1 is off and the P-type field effect transistor P2 is on. Therefore, the node n1 passes through the P-type field effect transistor P2.
Is transmitted to the node n3.

Conversely, when the node n2 is at a higher potential than the node n1, the P-type field effect transistor P1 is on and the P-type field effect transistor P2 is off.
Therefore, the potential of the node n2 is transmitted to the node n3 through the P-type field effect transistor P1.

The potential transmitted to the node n3 can be used as a potential for preventing forward bias of the parasitic bipolar transistor. (2) Second Embodiment FIG. 2 is a circuit diagram showing a second embodiment of a rectifier circuit used in a charge pump circuit or the like using the semiconductor device of the present invention.

In FIG. 2, the rectifier circuit includes a champion circuit of the first embodiment and a node n3 of the champion circuit.
And a P-type field effect transistor P3 connected to.

The structure and connection relationship of the champion circuit are the same as in the first embodiment. The source and gate of the P-type field effect transistor P3 are connected to the node n2,
The drain is connected to the node n1 and the N-type well 100 is connected to the node n3.

FIG. 3 is a sectional view showing the vertical structure of the rectifier circuit of the second embodiment of the present invention. In FIG. 3, the rectifier circuit according to the second embodiment includes a P-type substrate 200 (GND potential), an N
Type well 100 (same potential as node n3), gate P ⁺ (same potential as node n1) and source P ⁺ (same potential as node n2) and drain P ⁺ (same potential as node n3) of P-type field effect transistor P1. ), A gate P ⁺ (same potential as the node n2) and a source P ⁺ (same potential as the node n1) and a drain P ⁺ (same potential as the node n3) of the P-type field effect transistor P2, and a P-type field effect transistor P3. Gate P ⁺ (same potential as node n2), source P ⁺ (same potential as node n2), and drain P of
⁺ (The same potential as the node n1).

The N-type well 100 is formed on the P-type substrate 200, and the gate of the P-type field effect transistor P1, the source of the P-type field effect transistor P2, and the P-type field effect transistor formed on the N-type well 100. The drain of P3 is connected to the node n1, the source of the P-type field effect transistor P1 and the gate of the P-type field effect transistor P2, the source and gate of the P-type field effect transistor P3 are connected to the node n2, and the N-type well 100, the drain of the P-type field effect transistor P1 and the drain of the P-type field effect transistor P2 are connected to the node n3.

At this time, the node n1 or n2 (source of each P-type field effect transistor) and the N-type well 1 are used.
00 and the P-type substrate 200 correspond to the emitter, base and collector electrodes, respectively.

When the node n1 is at a higher potential than the node n2, the P-type field effect transistor P1 is in the off state, P
The field effect transistor P2 is in the ON state. Therefore, through the P-type field effect transistor P2, the node n
The potential of 1 is transmitted to the node n3.

Conversely, when the node n2 is at a higher potential than the node n1, the P-type field effect transistor P1 is on and the P-type field effect transistor P2 is off.
Therefore, the potential of the node n2 is transmitted to the node n3 through the P-type field effect transistor P1.

Due to the potential transmitted to the node n3, the N-type well 1 of the P-type field effect transistors P1, P2 and P3.
00 becomes a high potential, and a rectifier circuit having a simple configuration as shown in FIG. 2 is provided, in which the parasitic bipolar transistor of each P-type field effect transistor is prevented from being forward biased and the leak current is very small. Obtainable. (3) Third Embodiment FIG. 4 is a circuit diagram showing a third embodiment of a rectifier circuit used in a charge pump circuit or the like using the semiconductor device of the present invention.

In FIG. 4, the rectifier circuit is a level shift circuit connected to the champion circuit of the first embodiment, a P-type field effect transistor P4 connected to n3 of the champion circuit, a field effect transistor P4, and a node n3. L1 and.

The structure and connection relationship of the champion circuit are the same as in the first embodiment. The source of the P-type field effect transistor P4 is connected to the node n2, the gate is connected to the node n6 of the level shift circuit L1, and the drain is connected to the node n1. Further, the node n7 of the level shift circuit L1 is connected to the node n3 of the champion circuit.

FIG. 5 is a sectional view showing the vertical structure of the rectifier circuit of the third embodiment of the present invention except for the level shift circuit L1.

In FIG. 5, the rectifier circuit of the third embodiment has a P-type substrate 200 (GND potential) and an N-type well 10.
0 (the same potential as the node n3), the gate P ⁺ (the same potential as the node n1) and the source P ⁺ (the same potential as the node n2) and the drain P ⁺ (the same potential as the node n3) of the P-type field effect transistor P1. , P-type field effect transistor P2
Gate P ⁺ (same potential as node n2) and source P ⁺
(Same potential as node n1) and drain P ⁺ (node n
3), the gate P ⁺ (the same potential as the node n2), the source P ⁺ (the same potential as the node n2) and the drain P ⁺ (the same potential as the node n1) of the P-type field effect transistor P4.

The N-type well 100 is formed on the P-type substrate 200, and the gate of the P-type field effect transistor P1, the source of the P-type field effect transistor P2, and the P-type field effect formed on the N-type well 100. The drain of the transistor P4 is connected to the node n1, and the source of the P-type field effect transistor P1 and the P-type field effect transistor P2.
And the source of the P-type field effect transistor P4 are connected to the node n2, the N-type well 100, the drain of the P-type field effect transistor P1 and the drain of the P-type field effect transistor P2 are connected to the node n3, and The gate of the field effect transistor P4 is connected to the node n6.

At this time, the node n1 or n2 (source of each P-type channel field effect transistor), the N-type well 100, and the P-type substrate 200 correspond to an emitter, a base, and a collector electrode, respectively. A transistor is formed.

The level shift circuit L1 includes N-type field effect transistors N5, N6 and N7, P-type field effect transistors P5, P6 and P7, and an inverter INV.
Including and

In the level shift circuit L1, the node n
4, the source of the N-type field effect transistor N5, the drain of the P-type field effect transistor P5 and the gate of the P-type field effect transistor P6 are connected, and at the node n5, N
Source of N-type field effect transistor N6, gate of N-type field effect transistor N7 and P-type field effect transistor P
5 is connected to the drain of the P-type field effect transistor P6 and the gate of the P-type field effect transistor P7, and at the node n6, the source of the N-type field effect transistor N7 and the drain of the P-type field effect transistor P7 are connected. At the node n7, the P-type field effect transistor P5
Source and P-type field effect transistor P6 source and P
The source of the field effect transistor P7 is connected.

Further, the control signal CLK2 is input to the gate of the N-type field effect transistor N5 and the inverter INV. The output of the inverter INV is connected to the gate of the N-type field effect transistor N6. The drains of the N-type field effect transistors N5, N6 and N7 are grounded.

The operation of the level shift circuit will be described. First, the control signal CLK2 changes to the power supply voltage level V _dd (“H”).
At this time, the N-type field effect transistor N5 is in the ON state,
The field effect transistor N6 is turned off. Then, the node n4 becomes the GND potential through the N-type field effect transistor N5. When the node n4 becomes the GND potential, the P-type field effect transistor P6 is turned on. Since the P-type field effect transistor P6 is on and the N-type field effect transistor N6 is off, the node n5 becomes the node n.
It becomes the same potential as 3. When the node n5 has the same potential as the node n3, the N-type field effect transistor N7 turns on and the P-type field effect transistor P7 turns off. This gives P
The gate potential of the field effect transistor P4 becomes the GND potential.

On the other hand, when the control signal CLK2 is at the GND potential ("L"), the N-type field effect transistor N5 is turned off and the N-type field effect transistor N6 is turned on. The node n5 becomes the GND potential through the N-type field effect transistor N6. When the node n5 becomes GND potential, the P-type field effect transistor P5 is turned on. Since the P-type field effect transistor P5 is on and the N-type field effect transistor N5 is off, the node n4 is the node n.
It becomes the same potential as 3. When the node n5 becomes GND potential,
The N-type field effect transistor N7 turns off and the P-type field effect transistor P7 turns on. As a result, the gate potential of the P-type field effect transistor P4 becomes the same potential as the node n3.

Thus, by the level shift circuit L1,
The output signal (the potential of the gate of the P-type field effect transistor P4) swings between the potential of the node n3 and the potential of GND according to the input signal (CLK2) swinging _Vcc- GND.

Therefore, when the control signal CLK2 is "H" in the level shift circuit L1, the P-type field effect transistor P7 is in the off state, the N-type field effect transistor N7 is in the on state, and the gate potential of the P-type field effect transistor P4. Becomes GND level. At this time, since the P-type field effect transistor P4 is on, the nodes n1 and n2 are electrically connected.

On the other hand, in the level shift circuit L1, the control signal C
When LK2 is "L", P-type field effect transistor P7
Is turned on, the N-type field effect transistor N7 is turned off, and the gate potential of the P-type field effect transistor P4 becomes the same potential as the node n3 which is the output of the champion circuit. At this time, since the P-type field effect transistor P4 is off, the nodes n1 and n2 are electrically cut off.

Therefore, when the rectifier circuit is biased in the forward direction, the control signal CLK2 is set to "H", and when it is biased in the reverse direction, the control signal CLK2 is set to "L". It is possible to realize an efficient rectifier circuit that prevents the absolute value of the output voltage of the charge pump circuit from decreasing due to.

In this rectifier circuit, since the node n3, which is the output of the champion circuit, is connected to the N-type well 100 of the P-type field effect transistors P4, P5, P6 and P7, the parasitic of each P-type field effect transistor. Bipolar transistors are not forward biased and have very little or no leakage current.

In all the above-mentioned embodiments, the P-type field effect transistor formed in the N-type well on the P-type substrate is used. However, the N-type field effect transistor formed in the P-type well on the N-type substrate is used. It can be configured by changing.

[0053]

As described above, according to the present invention, claim 1
Of the first conductivity type semiconductor substrate, the second conductivity type impurity region formed on the first conductivity type semiconductor substrate, and the first conductivity type impurity region formed on the second conductivity type impurity region.
A first conductivity type field effect transistor, wherein one electrode of the first conductivity type first field effect transistor is connected to a first potential, the other electrode and a control electrode are connected to a second potential, and the second conductivity type is included. Since the higher potential of the first and second potentials is applied to the impurity region, the second conductivity type impurity region has the higher potential of the first and second potentials.

As a result, the forward bias of the parasitic bipolar of the first conductivity type first field effect transistor is prevented,
It is possible to obtain a rectifier circuit with a very small leak current.

According to another aspect of the semiconductor device of the present invention, when the first potential is higher, the first conductivity type second field effect transistor is turned on, the first conductivity type third field effect transistor is turned off, and the first potential is the above. Since it is applied to the second conductivity type impurity region, the second conductivity type impurity region has the first potential.

On the other hand, when the second potential is higher, the first conductivity type third field effect transistor is turned on, the first conductivity type second field effect transistor is turned off, and the second potential is the second conductivity type impurity. Since it is applied to the region, the impurity region of the second conductivity type has the second potential, and the impurity region of the second conductivity type can have the higher potential of the first and second potentials.

As a result, forward bias of the parasitic bipolar of the first conductivity type first field effect transistor can be prevented with a simple structure, and a rectifier circuit with a very small leak current can be obtained.

In the semiconductor device of claim 3, when the first potential is higher, the first conductivity type second field effect transistor is turned on, the first conductivity type third field effect transistor is turned off, and the first potential is changed. Since it is applied to the second conductivity type impurity region, the second conductivity type impurity region has the first potential.

On the other hand, when the second potential is higher, the first conductivity type third field effect transistor is turned on, the first conductivity type second field effect transistor is turned off, and the second potential is the second conductivity type impurity. Since it is applied to the region, the second conductivity type impurity region has the second potential.

Further, since the higher potential of the first and second potentials or the third potential which is the ground potential is applied to the control electrode of the first conductivity type first field effect transistor, the potential of the control electrode is increased. Swings between the higher one of the first and second potentials and the ground potential.

As a result, the forward bias of the parasitic bipolar of the first conductivity type first field effect transistor is prevented,
It is possible to obtain a rectifier circuit with a very small leak current.

Further, by controlling the conduction of the first conductivity type first field effect transistor by utilizing the swing of the potential of the control electrode, the absolute value of the output voltage of the charge pump due to the threshold voltage of the rectifier circuit can be controlled. It is possible to prevent the decrease and increase the efficiency of the rectifier circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a rectifier circuit used in a charge pump circuit or the like using a semiconductor device of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of a rectifier circuit used in a charge pump circuit or the like using the semiconductor device of the present invention.

FIG. 3 is a sectional view showing a vertical structure of a rectifier circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of a rectifier circuit used in a charge pump circuit or the like using the semiconductor device of the present invention.

FIG. 5 is a sectional view showing a vertical structure of a rectifier circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific example of a charge pump circuit that generates a voltage higher than a conventional power supply voltage.

FIG. 7 is a circuit diagram showing a diode-connected N-type field effect transistor used as a rectifier circuit in a conventional charge pump circuit.

FIG. 8 is a circuit diagram showing a diode-connected P-type field effect transistor used as a rectifier circuit in a conventional charge pump circuit.

FIG. 9 is a sectional view of a vertical structure of a diode-connected P-type field effect transistor used as a rectifier circuit in a conventional charge pump circuit.

[Explanation of symbols]

P1, P2, P3, P4, P5, P6, P7 P type field effect transistor, N5, N6, N7 N type field effect transistor, INV inverter, 200 P type substrate,
100 N-type well.

Claims (3)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the first conductivity type semiconductor substrate, and the first conductivity type formed on the second conductivity type impurity region. A first field effect transistor, one electrode of the first conductivity type first field effect transistor is connected to a first potential, the other electrode and a control electrode are connected to a second potential, and the second conductivity type impurity region is included. Which is formed on the upper surface of the first and second electric potentials, the higher electric potential being selectively applied to the second electric potential.
A semiconductor device including a selective applying means for applying to a conductivity type impurity region. 2. The second conductive type second element is provided between the first potential supply terminal supplying the first potential and the second conductive type impurity region.
A field effect transistor, a second potential supply terminal that supplies the second potential, and the first conductivity type third region provided between the second conductivity type impurity region.
A field effect transistor, wherein the control electrode of the first conductivity type second field effect transistor is connected to the second potential supply terminal, and the first conductivity type third
The semiconductor device according to claim 1, wherein a control electrode of the field effect transistor is connected to the first potential supply terminal. 3. A first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the first conductivity type semiconductor substrate, and the first conductivity type formed on the second conductivity type impurity region. A first field effect transistor, wherein one electrode of the first conductivity type first field effect transistor is connected to a first potential and the other electrode is connected to a second potential; A selectively applying means for selectively applying the higher potential of the two to the second conductivity type impurity region, wherein the selectively applying means includes a first potential supply terminal for supplying the first potential and the second potential supply terminal for supplying the first potential. A first conductivity type second field effect transistor provided between the conductivity type impurity region and a second potential supply terminal for supplying the second potential and the second conductivity type impurity region. One conductivity type third field effect transistor A control electrode of the first conductivity type second field effect transistor is connected to the second potential supply terminal, and a control electrode of the first conductivity type third field effect transistor is connected to the first potential supply terminal. Further comprising a third potential preparation means for outputting a third potential which is the higher one of the first and second potentials or a ground potential, wherein the third potential is the first conductivity type field effect transistor. A semiconductor device connected to the control electrode.