JPH0897235A - Forming method of gate electrode and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for forming a gate electrode of small gate length by using lithography. CONSTITUTION: After an SiO2 film 12 is deposited on a GaAs substrate 11, a resist pattern 13 is formed on the SiO2 film 12 which pattern has two oblong apertures formed at an interval of 0.5μm. The resist pattern 13 is used as a mask, and an aperture 14 is formed by etching the SiO2 film 12. After a pair of GaAs layers 15 having mushroom-shaped sections are epitaxially grown at an interval of 0.1μm on the GaAs substrate 11, the SiO2 film 12 is eliminated. A gate electrode whose gate length is 0.1μm is formed by evaporating metal for a gate electrode on the GaAs substrate 11, from the part between the GaAs layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode and a method for manufacturing a semiconductor device using the method for forming a gate electrode.

[0002]

2. Description of the Related Art Increasing the cutoff frequency ft is most effective for increasing the frequency of FETs.
In order to increase, the shortening of the gate length of the FET gate electrode (shortening the gate) is most effective.

In order to shorten the gate of the FET, a method of directly drawing a pattern of the gate electrode on the resist film with an electron beam (electron beam exposure method) has been conventionally used.

[0004]

However, according to the conventional electron beam exposure method, the pattern of the gate electrode is 1
Since the wafers are exposed one by one, the larger the diameter of the wafer, the longer the process of forming the resist pattern and the inability to process a large number of wafers at a time.Therefore, the electron beam exposure method is not suitable for mass production. are doing.

In view of the above, the present invention is a method of forming a gate electrode having a small gate length and a method of manufacturing a semiconductor device having a gate electrode having a small gate length by a conventional lithography technique without using an electron beam exposure method. The purpose is to realize.

[0006]

In order to achieve the above-mentioned object, a means for solving the problems according to the invention of claim 1 is to form a gate electrode by forming a pair of rectangular shapes on a semiconductor substrate at predetermined intervals. A first step of forming a mask pattern having an opening, and epitaxial growth on the semiconductor substrate exposed in the opening of the mask pattern to form a tip of an umbrella portion on the semiconductor substrate and the mask pattern. A second step of forming a pair of crystal bodies having a mushroom-shaped cross section so that the distance becomes the gate length of the gate electrode, and removing the mask pattern to expose the semiconductor substrate from between the pair of crystal bodies. A structure including a third step and a fourth step of forming a gate electrode by vapor-depositing a metal for forming a gate electrode on the semiconductor substrate from between the pair of crystal bodies. A.

According to a second aspect of the present invention, in the structure of the first aspect, in the fourth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies. A pair of crystals is vapor-deposited on the inner slopes of the umbrellas to form a cross section Y.
The configuration is added, which is a step of forming a gate electrode having a V-shape.

According to a third aspect of the present invention, a method for forming a gate electrode comprises a first step of epitaxially growing a gate electrode on a semiconductor substrate to form a first semiconductor layer, and a step of forming the first semiconductor layer. A second step of epitaxially growing on the second semiconductor layer to form a second semiconductor layer having an etching rate slower than that of the first semiconductor layer with respect to a particular etchant; A third step of forming a mask pattern having an opening; and etching the second semiconductor layer using the mask pattern as a mask to form a second semiconductor layer on the lower surface of the second semiconductor layer. A fourth step of forming a second semiconductor layer opening having an inverted trapezoidal cross-section whose opening width corresponds to the gate length of the gate electrode, and to the first semiconductor layer using the mask pattern as a mask. Etching selectively with the specific etchant, communicating with the first semiconductor layer opening and having an opening width larger than the opening width of the second semiconductor layer opening; 1) A fifth step of forming a semiconductor layer opening, and a sixth step of forming a gate electrode by depositing a metal for forming a gate electrode on the semiconductor substrate from the second semiconductor layer opening. It is configured to be.

According to a fourth aspect of the invention, in the structure of the third aspect, in the sixth step, a metal for forming a gate electrode is added to the second electrode.
It is a step of forming a gate electrode having a Y-shaped cross section by depositing on the semiconductor substrate from the conductor layer opening and depositing on the slopes on both sides of the second semiconductor layer opening in the second semiconductor layer. The configuration is added.

According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first step of forming source / drain regions on a semiconductor substrate; and a pair of semiconductor devices on the semiconductor substrate at predetermined intervals. A second step of forming a mask pattern having a rectangular opening, a third step of forming an ohmic electrode on the source / drain regions on the semiconductor substrate, and an opening of the mask pattern. Epitaxially growing on the exposed semiconductor substrate to form a pair of crystal bodies having a mushroom-shaped cross section on the semiconductor substrate and the mask pattern so that the distance between the tips of the umbrella portions becomes the gate length of the gate electrode. 4 step, a fifth step of removing the mask pattern to expose the semiconductor substrate from between the pair of crystal bodies, and a metal for forming a gate electrode It is an arrangement which from between the crystal bodies and a sixth step of forming a gate electrode by depositing on the semiconductor substrate.

According to a sixth aspect of the present invention, in the structure of the fifth aspect, the sixth step comprises depositing a metal for forming a gate electrode on the semiconductor substrate from between the pair of crystal bodies. A pair of crystals is vapor-deposited on the inner slopes of the umbrellas to form a cross section Y.
The configuration is added, which is a step of forming a gate electrode having a V-shape.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first step of forming source / drain regions on a semiconductor substrate; and a pair of semiconductor devices on the semiconductor substrate at predetermined intervals. A second step of forming a mask pattern having a rectangular opening, and epitaxial growth on the semiconductor substrate exposed in the opening of the mask pattern, and on the semiconductor substrate and the mask pattern,
A third step of forming a pair of crystal bodies having a mushroom-shaped cross section so that the distance between the tips of the umbrella portions becomes the gate length of the gate electrode, and removing the mask pattern to form the semiconductor substrate on the pair of crystal bodies. A fourth step of exposing the metal for forming a gate electrode on the semiconductor substrate from between the pair of crystal bodies to form a gate electrode; A sixth step of forming an ohmic electrode on the source / drain regions above.

According to an eighth aspect of the invention, in the structure of the seventh aspect, in the fifth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies. A pair of crystals is vapor-deposited on the inner slopes of the umbrellas to form a cross section Y.
The configuration is added, which is a step of forming a gate electrode having a V-shape.

According to a ninth aspect of the present invention, there is provided a solving means, which comprises a first step of forming source / drain regions on a semiconductor substrate and a first epitaxial growth on the semiconductor substrate.
Second step of forming the semiconductor layer, and epitaxially growing on the first semiconductor layer to form a second semiconductor layer having an etching rate slower than that of the first semiconductor layer for a specific etchant. A third step, a fourth step of forming a mask pattern having an opening of a predetermined width on the second semiconductor layer, and an ohmic electrode formed on the source / drain region of the semiconductor substrate. 5th to do
And the second step using the mask pattern as a mask.
Of the second semiconductor layer is etched to form a second semiconductor layer opening having an inverted trapezoidal cross-section whose opening width on the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode. A sixth step of forming, and using the mask pattern as a mask, the first semiconductor layer is selectively etched by the specific etchant, and the second semiconductor layer opening is formed in the first semiconductor layer. Forming a first semiconductor layer opening communicating with the first semiconductor layer opening and having an opening width larger than the opening width at the lower surface of the second semiconductor layer opening;
And the eighth step of forming a gate electrode by vapor-depositing a metal for forming a gate electrode on the semiconductor substrate from the opening of the second semiconductor layer.

According to a tenth aspect of the present invention, there is provided the structure of the ninth aspect.
In the eighth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from the second conductor layer opening, and slopes on both sides of the second semiconductor layer opening in the second semiconductor layer are formed. The structure is added to the step of forming a gate electrode having a Y-shaped cross section by vapor deposition.

According to an eleventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first step of forming source / drain regions on a semiconductor substrate; and a first step of epitaxial growth on the semiconductor substrate. Second forming a semiconductor layer
And a third step of epitaxially growing on the first semiconductor layer to form a second semiconductor layer having an etching rate slower than that of the first semiconductor layer with respect to a specific etchant, A second step of forming a mask pattern having an opening of a predetermined width on the second semiconductor layer, and etching the second semiconductor layer using the mask pattern as a mask to form the second semiconductor A fifth step of forming in the layer a second semiconductor layer opening having an inverted trapezoidal cross section whose opening width on the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode; and using the mask pattern as a mask. The first semiconductor layer is selectively etched by the specific etchant,
A sixth step of forming in the semiconductor layer a first semiconductor layer opening communicating with the second semiconductor layer opening and having an opening width larger than the opening width of the second semiconductor layer opening; A seventh step of forming a gate electrode by vapor-depositing a metal for forming a gate electrode on the semiconductor substrate from the opening of the second semiconductor layer, and forming an ohmic electrode on the source / drain regions of the semiconductor substrate. And an eighth step.

According to a twelfth aspect of the present invention, in the structure of the eleventh aspect, in the seventh step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from the second conductor layer opening. A configuration is added, which is a step of forming a gate electrode having a Y-shaped cross section by vapor deposition on the slopes on both sides of the second semiconductor layer opening in the second semiconductor layer.

[0018]

According to the structure of claim 1, a pair of crystal bodies having a mushroom-shaped cross section is formed on the semiconductor substrate so that the distance between the tips of the umbrella portions becomes the gate length of the gate electrode. Since the gate electrode is formed by vapor deposition on the semiconductor substrate from between the pair of crystal bodies, the gate length of the gate electrode is the distance between the tips of the umbrella portions of the pair of crystal bodies. In this case, since the crystal body having the mushroom-shaped cross section is formed by epitaxial growth on the semiconductor substrate exposed in the pair of rectangular openings, the distance between the tips of the umbrella portions of the crystal body having the mushroom-shaped cross section and thus the gate electrode gate The length is smaller than the distance between the pair of openings.

According to the second aspect of the present invention, the metal for forming the gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies and is vapor-deposited on the inner slope of the umbrella portion of the pair of crystal bodies to form a Y-shaped section. Since the gate electrode is formed in a striped shape, a mushroom-shaped gate electrode having a small gate length and a large contact area with the metal wiring is formed.

According to the structure of claim 3, from the opening of the second semiconductor layer which is formed in the second semiconductor layer and whose opening width in the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode, the second semiconductor layer has an inverted trapezoidal cross section. Since the gate electrode is formed by depositing the metal for forming the gate electrode on the semiconductor substrate, the gate length of the gate electrode is the opening width of the second semiconductor layer opening having an inverted trapezoidal cross section. In this case, since the second semiconductor layer opening having the inverted trapezoidal cross section is formed by etching using the mask pattern having the opening having the predetermined width as the mask, the opening width of the second semiconductor layer opening having the inverted trapezoidal cross section, and thus the opening. The gate length is smaller than the predetermined width of the opening of the mask pattern. Further, since the opening width of the first semiconductor layer opening is larger than the opening width of the second semiconductor layer opening, the gate electrode does not contact the first semiconductor layer.

According to the structure of claim 4, the metal for forming the gate electrode is vapor-deposited on the semiconductor substrate from the opening of the second conductor layer, and on the slopes on both sides of the opening of the second semiconductor layer in the second semiconductor layer. Since the gate electrode having a Y-shaped cross section is formed by vapor deposition, a mushroom-shaped gate electrode having a short gate length and a large contact area with a metal wiring is formed.

According to the structure of claim 5 or 7, in the same manner as in claim 1, a semiconductor device having a gate electrode having a gate length smaller than a distance between a pair of openings is manufactured.

According to the sixth or eighth aspect of the invention, similarly to the second aspect, a semiconductor device having a mushroom-shaped gate electrode having a short gate length and a large contact surface property with a metal wiring is manufactured.

According to the configuration of claim 9 or 11, claim 3
Similarly, a semiconductor device having a gate electrode having a gate length smaller than the width of the opening of the mask pattern is manufactured. According to the structure of claim 10 or 12, similarly to claim 4, a semiconductor device having a mushroom-shaped gate electrode having a short gate length and a large contact surface property with a metal wiring is manufactured.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 3 show a first embodiment of the present invention.
7A to 7C show each step of the method of forming the gate electrode according to the example.

First, as shown in FIG. 1A, plasma C is formed on a GaAs substrate 11 having a substrate plane orientation of (001).
After depositing the SiO ₂ film 12 to a thickness of 20 nm by using the VD method, as shown in FIGS. 1B and 1C, the SiO ₂ film 12 has a width of 0.5 μm and a long length on the SiO ₂ film 12. Forming a resist pattern 13 having an opening 13a extending in the [0-11] direction by photolithography using a mask having two rectangular openings formed with a width equal to the gate width and at an interval of 0.5 μm. To do.

Next, using the resist pattern 13 as a mask, the SiO ₂ film 12 is etched using buffered hydrofluoric acid (a mixture of ammonium fluoride and hydrofluoric acid: NH ₄ F-6% HF). 2
After forming the opening 14 in the SiO ₂ film 12 as shown in (a), the resist pattern 13 is removed by acetone as shown in FIG. 2 (b). After that, as shown in FIG. 2C, G
On the aAs substrate 11, a pair of GaAs layers 15 as a crystal body having a mushroom-shaped cross section is epitaxially grown to a height of 0.656 μm. This metal-organic vapor phase epitaxy is performed under the following growth conditions, for example. Trimethylgallium (Ga (CH ₃ ) ₃ ) and arsine (As
H ₃ ), the V / III ratio (molar ratio of the group V element and the group III element) is 100, the growth temperature is 700 ° C., the growth pressure is 100 torr, and hydrogen gas is used as a carrier gas. Flow rate is 6000 c. c. / Min, the (111) A plane of GaAs is selectively grown as shown in FIG. 2 (c). In this case, as shown in FIG. 2C, when the GaAs layer 15 is grown to a height of 0.656 μm, the distance between the inner tips of the caps of the GaAs layer 15 becomes 0.1 μm. . Next, FIG. 2 (d)
As shown in FIG. 5, the SiO ₂ film 12 is removed by buffered hydrofluoric acid.

Next, as shown in FIG.
After forming a resist pattern 17 having an opening 16 on the gate electrode formation region on the substrate 11 and the GaAs layer 15 by photolithography, vapor deposition is performed on the resist pattern 17 as shown in FIG. 3B. Thus, the gate electrode metal film 18A is entirely deposited. After that, FIG.
As shown in (c), the gate electrode metal film 18A is lifted off to have a gate length of 0.1 μm.
Form B.

(Second Embodiment) FIGS. 4 and 5 show respective steps of a method of forming a gate electrode according to a second embodiment of the present invention.

First, as shown in FIG. 4A, a GaAs layer 22 as a first semiconductor layer is epitaxially grown to a thickness of 20 nm on a GaAs substrate 21 having a substrate plane orientation of (001), and then GaAs is formed. the Al _0.15 Ga _{0. 85} as layer 23 as a second semiconductor layer 210nm on the layer 22
Epitaxially grown to a thickness of. Then, a resist pattern 24 having an opening 24a extending in the [1-10] direction is formed on the Al _0.15 Ga _0.85 As layer 23 by photolithography using a mask having an opening width of 0.5 μm in the gate length direction. To do. Then, for example, HNO
Using an etchant composed of ₃ : H ₂ O = 1: 3, A
Isotropic etching is performed on the _0.15 Ga _0.85 As layer 23. In this case, as shown by the chain double-dashed line in FIG. 4C, the Al _0.15 Ga _0.85 As layer 23 is prevented from being etched deeper in the horizontal direction than the opening 24 a of the resist pattern 24. HNO ₃ : H ₂ O = 1: 3 is an isotropic etchant with the (111) A plane exposed.
Also, this isotropic etching _{results in} Al _0.15 Ga _0.85
An inverted trapezoidal opening 25A is formed in the As layer 23 as a second semiconductor layer opening having an opening width of 0.1 μm on the lower surface of the Al _0.15 Ga _0.85 As layer 23. in this case,
On the upper surface of the GaAs layer 22, a recess having a triangular cross section is formed which communicates with the inverted trapezoidal opening 25A.

Next, as shown in FIG. 5A, for example,
Add aqueous ammonia to citric acid: H ₂ O ₂ = 50: 1 and add p
The inverted trapezoidal opening 2 is formed by an etchant adjusted to H = 6.5 (hereinafter referred to as a citric acid-based etchant).
The GaAs layer 22 is selectively removed from 5A to form a rectangular opening 25B as a first semiconductor layer having an opening width larger than the opening width of 0.1 μm of the inverted trapezoidal opening 25A. The citric acid type etchant is Al _0.15 G
a The etching rate ratio of GaAs to _0.85 As is 80
And a selective etchant having a high selection ratio with respect to GaAs (Study Tech. Report ED93-99). After that, FIG.
As shown in (b), the gate electrode metal film 2 is formed by vapor deposition.
After depositing 6A on the entire surface, the gate electrode metal film 26A
Is lifted off to form a gate electrode 26B having a gate length of 0.1 μm as shown in FIG.

(Third Embodiment) FIGS. 6 to 12 show steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. The third embodiment is a MESFET manufacturing method to which the gate electrode forming method according to the first embodiment is applied.

First, as shown in FIG. 6A, a semi-insulating GaAs substrate 31 having a substrate surface orientation of (001) is formed on a semi-insulating GaAs substrate 31 by, for example, a molecular beam epitaxy apparatus (MBE).
After the type GaAs buffer layer 32 is laminated to a thickness of 500 nm, Si is doped at 5 × 10 ¹⁷ cm ⁻³ and the n ⁻ type GaAs layer 33 is laminated to a thickness of 50 nm on the i type GaAs buffer layer 32. Then, similarly, Si is doped at 5 × 10 ¹⁸ cm ⁻³ and the n ⁺ type GaAs layer 3 is formed on the n ⁻ type GaAs layer 33.
4 is laminated to a thickness of 50 nm. Thereafter, as shown in FIG. 6B, the FET on the n ⁺ type GaAs layer 34
A resist pattern 35 is formed by photolithography in the region where the is to be formed. After that, resist pattern 3
5 is used as a mask to perform mesa etching to a depth of 150 nm with a phosphoric acid-based etchant to separate the elements.

Next, as shown in FIG. 7A, after removing the resist pattern 35, a first SiO ₂ film 36 is formed to a thickness of 6 μm.
Deposit to a thickness of 0 nm. After that, as shown in FIG. 7B, the width dimension (FIG. 7) is formed on the FET formation region on the first SiO ₂ film 36 by photolithography.
A resist pattern 37 having a rectangular opening with a horizontal dimension in (b) of 2 μm and a length dimension equal to the gate width is formed. The resist pattern 3
The reason why the width of the opening of 7 is 2 μm will be described later. Thereafter, as shown in FIG. 7C, the first SiO ₂ film 36 is etched using the resist pattern 37 as a mask, and then the resist pattern 37 is removed.

Next, as shown in FIG. 8A, the first S
The n ⁺ -type GaAs layer 34 is recess-etched with, for example, a phosphoric acid-based etchant using the iO ₂ film 36 as a mask. In this case, the width of the opening of the resist pattern 37 is 2
Since it is μm, the width of the opening formed in the n ⁺ type GaAs layer 34 is also 2 μm. After that, as shown in FIG. 8B, after removing the first SiO ₂ film 36, plasma C
After depositing the second SiO ₂ film 39 to a thickness of 20 nm by using the VD method, the width is 0.5 μm, the length is equal to the gate width, and the interval is 0.5 μm, as in the first embodiment. A resist pattern having an opening extending in the [0-11] direction is formed by photolithography using a mask having two rectangular openings formed in 1., and buffered hydrofluoric acid is used with the resist pattern as a mask. By performing etching, the second SiO ₂ film 39 is formed on the second SiO ₂ film 39 according to the first embodiment as shown in FIG. 8B (see FIG. 2B).
An opening similar to that is formed. After that, for example, by the metal organic chemical vapor deposition method under the same conditions as in the first embodiment, as shown in FIG.
As shown in FIG. 6, a pair of GaAs layers 38 as a crystal body having a mushroom-shaped cross section are formed on the GaAs substrate 31 at 0.656 μm.
Grow to the height of. In this case, the distance between the inner tips of the caps of the GaAs layer 38 is 0.1 μm, and
The distance between the outer tips of the umbrella portions of No. 8 is 1.9 μm. In order to secure the distance between the outer tips, n ⁺
The width of the opening formed in the type GaAs layer 34, that is, the width of the opening of the resist pattern 37 is 2 μm. Then, as shown in FIG. 8C, the GaAs layer 38
A resist pattern 40 for forming an ohmic electrode to be a source / drain electrode is formed thereon.

Next, as shown in FIG. 9A, after selectively etching the second SiO ₂ film 39 by using, for example, buffered hydrofluoric acid (HF 6%) with the resist pattern 40 as a mask, For example, AuGe / Ni is vapor-deposited to a thickness of 130 nm / 40 nm, respectively.
As shown in (b), the ohmic electrode forming metal film 41A is deposited over the entire surface.

Next, as shown in FIG. 10A, the ohmic electrode forming metal film 41A is lifted off to form an ohmic electrode 41B, and then the GaAs layer 38 and the ohmic electrode 41B are formed as shown in FIG. 10B. A resist pattern 42 for forming a gate electrode is formed on the electrode 41B.

Next, as shown in FIG. 11A, the second SiO ₂ film 39 is etched by using, for example, buffered hydrofluoric acid (HF 6%) with the resist pattern 42 as a mask, thereby forming a _second film. The gate electrode formation region in the SiO ₂ film 39 is removed to expose the n ⁻ type GaAs layer 33. After that, as shown in FIG. 11B, the gate electrode formation region in the n ⁻ type GaAs layer 33 is recess-etched to a depth of several nm with, for example, a phosphoric acid-based etchant. Next, as shown in FIG. To
For example, Ti / Pt / Au are 50/50/40 respectively
Metal film 43 for gate electrode is deposited on the entire surface to a thickness of 0 nm.
After depositing A, as shown in FIG. 12B, when the gate electrode metal film 43A is lifted off to form the gate electrode 43B, a MESFET having a gate length of 0.1 μm is formed.
Can be manufactured.

(Fourth Embodiment) FIGS. 13 to 17 show steps of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The fourth embodiment is a MESFET manufacturing method to which the gate electrode forming method according to the second embodiment is applied.

First, as shown in FIG. 13A, an i-type GaAs buffer layer 52 is formed on a semi-insulating GaAs substrate 51 having a substrate surface orientation of (001) by, for example, a molecular beam epitaxy (MBE) device. After stacking to a thickness of 500 nm, Si is doped at 5 × 10 ¹⁷ cm ⁻³ to form i-type GaA.
An n ⁻ -type GaAs layer 53 having a thickness of 50 nm is stacked on the s buffer layer 52, and then Si is also added at 5 × 10 ¹⁸ cm ^−3.
N ⁺ type GaAs on the n ⁻ type GaAs layer 53 by doping
Layer 54 is laminated to a thickness of 50 nm. After that, FIG.
As shown in (b), after forming a resist pattern 55 by photolithography in the FET formation region on the n ⁺ -type GaAs layer 54, as shown in FIG. 13C, using the resist pattern 55 as a mask, for example, The elements are separated by performing mesa etching to a depth of 150 nm with a phosphoric acid-based etchant.

Next, as shown in FIG. 14A, after removing the resist pattern 55, the first pattern is formed in the same manner as in the second embodiment.
After epitaxially growing a GaAs layer 56 as a semiconductor layer of 20 nm in thickness, a second layer is formed on the GaAs layer 56.
Of Al _0.15 Ga _0.85 As layer 57 as a semiconductor layer of
Epitaxially grow to a thickness of 0 nm. Then, Figure 1
As shown in FIG. 4B, a resist pattern 58 for forming an ohmic region is formed on the Al _0.15 Ga _0.85 As layer 57 by photolithography, and then the resist pattern 58 is formed by a reactive ion etching apparatus (RIE). Is used as a mask to perform RIE etching. As shown in FIG. 14 (c), Al _0.15 Ga _0.85 A
The s layer 57 and the GaAs layer 56 are selectively removed.

Next, for example, AuGe / Ni is added to 130 nm.
/ 40nm thickness is vapor-deposited on the entire surface.
As shown in (a), the ohmic electrode metal film 5 for forming ohmic electrodes that are source / drain electrodes.
After depositing 9A, the ohmic electrode metal film 59A is lifted off to form an ohmic electrode 59B as shown in 15 (b). After that, as shown in FIG. 15C, the Al _0.15 Ga _0.85 As layer 57 and the ohmic electrode 5 are formed.
Similar to the second embodiment, a gate electrode for forming a gate electrode having a length corresponding to the gate width, a width of 0.5 μm, and an opening extending in the [1-10] direction is formed on 9B by photolithography. After forming the resist pattern 60, the Al _0.15 Ga _0.85 As layer 57 and the GaAs layer 56 are isotropically etched using the resist pattern 60 as a mask. By this isotropic etching, Al _0.15 Ga _0.85
The width of the lower side of the inverted trapezoidal opening as the second semiconductor layer opening formed in the As layer 57 is 0.1 μm. afterwards,
From the inverted trapezoidal opening of the Al _0.15 Ga _0.85 As layer 57 to Ga
The As layer 56 is selectively removed to form a rectangular opening as the first semiconductor layer opening.

Next, as shown in FIG. 16 (a), after the recess etching by selective etchant n ⁺ -type GaAs layer 54, in order to improve the breakdown voltage, as shown in FIG. 16 (b), n ^- -type The GaAs layer 53 is slightly recessed. Then, as shown in FIG. 16C, for example, Ti / Pt / Au is added to 50/50/400 nm, respectively.
Then, a metal film for gate electrode 61A is deposited by vapor deposition over the entire thickness.

Next, as shown in FIG. 17, the gate electrode metal film 61A is lifted off so that the gate length is 0.1 μm.
Is manufactured.

(Fifth Embodiment) FIG. 18 shows steps of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.
The fifth embodiment is a method of manufacturing an HFET (heterojunction field effect transistor) to which the gate electrode forming method according to the first embodiment is applied.

The fifth embodiment is different from the third embodiment only in the film structure, and the other structures are the same as those in the third embodiment. Therefore, only the manufacturing process of the film structure will be described below.

As shown in FIG. 18, semi-insulating GaAs
An i-type GaAs buffer layer 72 having a thickness of 500 nm is stacked on the substrate 71 by, for example, a molecular beam epitaxy apparatus, and then an i-type Al _0.2 layer is formed on the i-type GaAs buffer layer 72.
A Ga _0.8 As layer 73 is laminated to a thickness of 2 nm. Then, Si is doped at 5 × 10 ¹⁷ cm ⁻³ and n ⁻ type Al _{0.2 is formed.}
A Ga _0.8 As layer 74 is laminated to a thickness of 30 nm, and then Si is also doped at 5 × 10 ¹⁸ cm ^−3, and then n ⁺ type GaAs.
Layer 75 is deposited to a thickness of 50 nm. In FIG. 18, 76 is a SiO ₂ film, 77 is a GaAs layer, 78 is an ohmic electrode, and 79 is a gate electrode.

(Sixth Embodiment) FIG. 19 shows steps of a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.
The sixth embodiment is a method of manufacturing an HFET to which the gate electrode forming method according to the second embodiment is applied.

The fifth embodiment is different from the third embodiment only in the film structure, and the other structures are the same as those in the third embodiment. Therefore, only the manufacturing process of the film structure will be described below.

As shown in FIG. 19, semi-insulating GaAs
An i-type GaAs buffer layer 82 having a thickness of 500 nm is stacked on the substrate 81 by, for example, a molecular beam epitaxy apparatus, and then an i-type Al _0.2 layer is formed on the i-type GaAs buffer layer 82.
A Ga _0.8 As layer 83 is laminated to a thickness of 2 nm. Then, Si is doped at 5 × 10 ¹⁷ cm ⁻³ and n ⁻ type Al _{0.2 is formed.}
A Ga _0.8 As layer 84 having a thickness of 30 nm is laminated, and then Si is also doped at 5 × 10 ¹⁸ cm ⁻³ and n ⁺ type GaAs.
Layer 85 is deposited to a thickness of 50 nm. In FIG. 19, 86 is a GaAs layer and 87 is Al _0.15 Ga _0.85 As.
A layer, 88 is an ohmic electrode, and 89 is a gate electrode.

[0052]

According to the method of forming a gate electrode of the first aspect of the present invention, a pair of crystal bodies having a mushroom-shaped cross section is formed on a semiconductor substrate so that the distance between the tips of the umbrella portions becomes the gate length. Since the gate electrode is formed by vapor-depositing the metal for forming the gate electrode on the semiconductor substrate from between the pair of crystal bodies, the gate length is the distance between the tips of the umbrella portions of the pair of crystal bodies and the pair of openings. Since it is smaller than the distance between the openings, it is possible to realize a gate electrode having a gate length smaller than the distance between the pair of openings of the mask pattern formed by photolithography. Since a gate electrode having a small gate length can be formed using a mask pattern formed by photolithography in this manner, that is, a large number of large-diameter wafers can be processed at a time by a simple method. Suitable for mass production.

According to the method of forming a gate electrode of the second aspect of the present invention, the metal for forming the gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies and at the same time, inside the umbrella portion of the pair of crystal bodies. Since a gate electrode having a Y-shaped cross section is formed by vapor deposition on a slope, a gate electrode having a small gate length and a large contact area with a metal wiring can be formed. An electrode can be realized.

According to the method of forming a gate electrode of the third aspect of the present invention, the inverted trapezoidal cross section is formed in the second semiconductor layer and the opening width in the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode. Since the gate electrode is formed by depositing a metal for forming a gate electrode on the semiconductor substrate from the second semiconductor layer opening of the second semiconductor layer opening, the gate length becomes the opening width of the second semiconductor layer opening having an inverted trapezoidal cross section. A gate electrode having a gate length smaller than the opening width of a mask pattern formed by lithography can be realized. Since a gate electrode having a small gate length can be formed using a mask pattern formed by photolithography in this manner, that is, a large number of large-diameter wafers can be processed at a time by a simple method. Suitable for mass production.

According to the method of forming a gate electrode of the fourth aspect of the present invention, the metal for forming the gate electrode is vapor-deposited on the semiconductor substrate from the opening of the second conductor layer, and the second semiconductor in the second semiconductor layer is formed. Since the gate electrode having a Y-shaped cross section is formed by vapor deposition on the slopes on both sides of the layer opening, the gate electrode having a small gate length and a large contact area with the metal wiring can be formed. Therefore, a gate electrode having a low gate resistance can be realized.

In the method of manufacturing a semiconductor device according to the invention of claim 5 or 7, since the semiconductor device is manufactured by using the method of forming a gate electrode according to the invention of claim 1, it has a gate electrode having a small gate length. A high frequency FET can be manufactured with high productivity.

Since the method of manufacturing a semiconductor device according to the invention of claim 6 or 8 uses the method of forming a gate electrode according to the invention of claim 2, the gate resistance is small despite the small gate length. Since the gate electrode can be realized, a high frequency FET having excellent high frequency characteristics can be manufactured with high productivity.

According to the method of manufacturing a semiconductor device of the ninth or eleventh aspect of the invention, the semiconductor device is manufactured by using the method of forming a gate electrode of the third aspect of the invention. The high-frequency FET included therein can be manufactured with high productivity.

According to the semiconductor device manufacturing method of the tenth or twelfth aspect of the invention, since the method of forming the gate electrode of the fourth aspect of the invention is used, the gate resistance is small despite the small gate length. Since a small gate electrode can be realized, a high frequency FET having excellent high frequency characteristics can be manufactured with high productivity.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of a method of forming a gate electrode according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step in a method of forming a gate electrode according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step in a method of forming a gate electrode according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step in a method of forming a gate electrode according to the second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step in a method of forming a gate electrode according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the invention.

FIG. 7 is a cross-sectional view showing a step in a method for manufacturing a semiconductor device according to a third exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the third example of the present invention.

FIG. 9 is a cross-sectional view showing a step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the third example of the present invention.

FIG. 11 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the third example of the present invention.

FIG. 13 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the fourth example of the present invention.

FIG. 14 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the fourth example of the present invention.

FIG. 15 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the fourth exemplary embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the fourth example of the present invention.

FIG. 17 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device according to the fourth example of the present invention.

FIG. 18 is a cross-sectional view showing a step in the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a step in the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

[Explanation of symbols]

11 GaAs Substrate 12 SiO ₂ Film 13 Resist Pattern 14 Rectangular Opening 15 GaAs Layer (Crystalline Mushroom Crystal) 16 Opening 17 Resist Pattern 18A Gate Electrode Metal Film 18B Gate Electrode 21 GaAs Substrate 22 GaAs Layer (First) 1 semiconductor layer) 23 Al _0.15 Ga _0.85 As layer (second semiconductor layer) 24 Resist pattern 25A Reverse trapezoidal opening (second semiconductor layer opening) 25B Rectangular opening (first semiconductor layer opening) 26A Metal film for gate electrode 26B Gate electrode 31 GaAs substrate 32 i-type GaAs buffer layer 33 n ^- GaAs layer 34 n ⁺ GaAs layer 35 Resist pattern 36 First SiO ₂ film 37 Resist pattern 38 GaAs layer (Crystalline mushroom body in cross section) ) 39 second SiO ₂ film 40 resist pattern 41A Ohmic electrode metal film 41B Ohmic electrode 42 Resist pattern 43A Gate electrode metal film 43B Gate electrode 51 GaAs substrate 52 i-type GaAs buffer layer 53 n ^- type GaAs layer 54 n ⁺ type GaAs layer 55 Resist pattern 56 GaAs layer (first) Semiconductor layer) 57 Al _0.15 Ga _0.85 As layer (second semiconductor layer) 58 Resist pattern 59A Ohmic electrode metal film 59B Ohmic electrode 60 Resist pattern 61A Gate electrode metal film 61B Gate electrode 71 GaAs substrate 72 i-type GaAs buffer Layer 73 i-type Al _0.2 Ga _0.8 As layer 74 n ^- type Al _0.2 Ga _0.8 As layer 75 n ⁺ GaAs layer 76 SiO ₂ film 77 GaAs layer 78 Ohmic electrode 79 gate electrode 81 GaAs substrate 82 GaAs buffer layer 83 i-type Al _0.2 G _0.8 As layer 84 n ^- Al _0.2 Ga _0.8 As layer 85 n ⁺ GaAs layer 86 GaAs layer 87 Al _0.15 Ga _0.85 As layer 88 ohmic electrode 89 gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/28 G 21/027

Claims (12)

[Claims] 1. A first mask pattern is formed on a semiconductor substrate, the mask pattern having a pair of rectangular openings at predetermined intervals.
And a step of epitaxially growing on the semiconductor substrate exposed in the opening of the mask pattern, and a cross-section on the semiconductor substrate and the mask pattern such that the distance between the tips of the umbrella portions is the gate length of the gate electrode. A second step of forming a pair of mushroom-shaped crystal bodies, a third step of removing the mask pattern to expose the semiconductor substrate from between the pair of crystal bodies, and a third step for forming a gate electrode A fourth step of forming a gate electrode by vapor-depositing a metal from between the pair of crystal bodies on the semiconductor substrate. 2. In the fourth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies and on the inner slope of the umbrella portion of the pair of crystal bodies. The method of forming a gate electrode according to claim 1, which is a step of forming a gate electrode having a Y-shaped cross section. 3. A first step of epitaxially growing on a semiconductor substrate to form a first semiconductor layer; and an epitaxial growth on the first semiconductor layer to perform a specific etchant on the first semiconductor layer. A second step of forming a second semiconductor layer having an etching rate slower than that; a third step of forming a mask pattern having an opening of a predetermined width on the second semiconductor layer; Etching is performed on the second semiconductor layer using the pattern as a mask, and the second semiconductor layer has an inverted trapezoidal cross section whose opening width at the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode. A fourth step of forming a second semiconductor layer opening, and selectively etching the first semiconductor layer with the etchant using the mask pattern as a mask, A fifth step of forming in the first semiconductor layer a first semiconductor layer opening communicating with the second semiconductor layer opening and having an opening width larger than the opening width of the second semiconductor layer opening; Forming a gate electrode by depositing a metal for forming a gate electrode on the semiconductor substrate through the opening of the second semiconductor layer;
And a step of forming a gate electrode. 4. In the sixth step, a metal for forming a gate electrode is deposited on the semiconductor substrate through the second conductor layer opening, and the second metal in the second semiconductor layer is deposited.
4. The method of forming a gate electrode according to claim 3, which is a step of forming a gate electrode having a Y-shaped cross section by vapor-depositing on slopes on both sides of the semiconductor layer opening. 5. A first step of forming source / drain regions on a semiconductor substrate, and a second step of forming a mask pattern having a pair of rectangular openings at predetermined intervals on the semiconductor substrate. A third step of forming an ohmic electrode on the source / drain regions on the semiconductor substrate, and epitaxial growth on the semiconductor substrate exposed in the opening of the mask pattern to form the semiconductor substrate and the mask. A fourth step of forming a pair of crystal bodies having a mushroom-shaped cross section on the pattern so that the distance between the tips of the umbrella portions becomes the gate length of the gate electrode; and removing the mask pattern to form the semiconductor substrate. A fifth step of exposing from between the pair of crystal bodies, and a gate by depositing a metal for forming a gate electrode on the semiconductor substrate from between the pair of crystal bodies. The method of manufacturing a semiconductor device characterized by and a sixth step of forming a pole. 6. In the sixth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies and on the inner slope of the umbrella portion of the pair of crystal bodies. The method for manufacturing a semiconductor device according to claim 5, wherein the step is a step of forming a gate electrode having a Y-shaped cross section. 7. A first step of forming source / drain regions on a semiconductor substrate, and a second step of forming a mask pattern having a pair of rectangular openings at predetermined intervals on the semiconductor substrate. And a pair of cross-sections that are epitaxially grown on the semiconductor substrate exposed in the opening of the mask pattern and on the semiconductor substrate and the mask pattern such that the distance between the tips of the umbrella portions is the gate length of the gate electrode. A third step of forming a mushroom-shaped crystal body, a fourth step of removing the mask pattern to expose the semiconductor substrate from between the pair of crystal bodies, and a metal for forming a gate electrode. A fifth step of forming a gate electrode by vapor-depositing on the semiconductor substrate from between the pair of crystal bodies, and ohmic contact on the source / drain regions on the semiconductor substrate. The method of manufacturing a semiconductor device characterized by and a sixth step of forming a pole. 8. In the fifth step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from between the pair of crystal bodies and on the inner slope of the umbrella portion of the pair of crystal bodies. 8. The method of manufacturing a semiconductor device according to claim 7, which is a step of forming a gate electrode having a Y-shaped cross section. 9. A first step of forming source / drain regions on a semiconductor substrate, a second step of epitaxially growing on the semiconductor substrate to form a first semiconductor layer, and the first semiconductor layer. A third step of forming a second semiconductor layer having an etching rate slower than that of the first semiconductor layer with respect to a specific etchant by epitaxial growth on the second semiconductor layer, and a predetermined width on the second semiconductor layer. A fourth step of forming a mask pattern having an opening of the semiconductor substrate, a fifth step of forming an ohmic electrode on the source / drain regions of the semiconductor substrate, and the second semiconductor using the mask pattern as a mask. The second semiconductor layer is etched into a second half having an inverted trapezoidal cross section whose opening width at the lower surface of the second semiconductor layer corresponds to the gate length of the gate electrode. A sixth step of forming a body layer opening; and using the mask pattern as a mask, selectively etching the first semiconductor layer with the specific etchant to form the first semiconductor layer with the first A second step of forming a first semiconductor layer opening communicating with the second semiconductor layer opening and having an opening width larger than the opening width of the lower surface of the second semiconductor layer opening; Forming a gate electrode by depositing a metal for forming a gate electrode on the semiconductor substrate
The manufacturing method of the semiconductor device characterized by the above-mentioned. 10. In the eighth step, a metal for forming a gate electrode is deposited on the semiconductor substrate from the second conductor layer opening portion, and the second semiconductor layer opening in the second semiconductor layer is formed. 10. The method for manufacturing a semiconductor device according to claim 9, which is a step of forming a gate electrode having a Y-shaped cross section by vapor deposition on slopes on both sides of the portion. 11. A first step of forming source / drain regions on a semiconductor substrate, a second step of epitaxially growing on the semiconductor substrate to form a first semiconductor layer, and the first semiconductor layer. A third step of forming a second semiconductor layer having an etching rate slower than that of the first semiconductor layer with respect to a specific etchant by epitaxial growth on the second semiconductor layer, and a predetermined width on the second semiconductor layer. A fourth step of forming a mask pattern having an opening, and etching the second semiconductor layer using the mask pattern as a mask to form a second semiconductor layer on the second semiconductor layer. A fifth step of forming a second semiconductor layer opening having an inverted trapezoidal cross section whose opening width on the lower surface corresponds to the gate length of the gate electrode; and the first semiconductor using the mask pattern as a mask. An opening is formed in the first semiconductor layer, the opening being in communication with the second semiconductor layer opening and larger than the opening width of the second semiconductor layer opening, by selectively etching the layer with the specific etchant. A sixth step of forming a first semiconductor layer opening having a width, and a seventh step of forming a gate electrode by depositing a metal for forming a gate electrode on the semiconductor substrate from the second semiconductor layer opening
And a step of forming an ohmic electrode on the source / drain regions of the semiconductor substrate, the method of manufacturing a semiconductor device. 12. In the seventh step, a metal for forming a gate electrode is vapor-deposited on the semiconductor substrate from the second conductor layer opening portion, and the second semiconductor layer opening in the second semiconductor layer is formed. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the step is a step of forming a gate electrode having a Y-shaped cross section by vapor deposition on slopes on both sides of the portion.