JPH089262A - Ccd signal reading circuit - Google Patents

Abstract

PURPOSE:To effectively reduce the CCD noises. CONSTITUTION:A signal 100 outputted from a CCD 11 of a solid-state image pickup camera includes a reset period, a feed-through period containing a reset noise, and a pixel signal period in a single pixel period. A pulse generator circuit 12 generates the gate pulses 101 and 102 in response to a feed-through signal (b) and a pixel signal (c) respectively, and the gates 13 and 14 extract a feed-through signal 201 and a pixel signal 301 by both gate pulses. The LPF 15 and 16 output the signals 202 and 302 which are free from the high band noises. The sample-and-hold circuits 18, 20 and 19 hold a signal 203 that extracted the peak value or the signal 202 by a sampling pulse 103, a signal 303 corresponding to the signal 302 by a sampling pulse 104, and a signal 204 corresponding to the peak of the signal 203 respectively. Then a differential amplifier 21,performs the subtraction between both signals 204 and 303 and outputs an image signal 304 where the CCD reset noise and the 1/f noise correlative with the signals (b) and (c) respectively are offset each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CCD signal readout circuit,
In particular, it relates to a signal readout circuit of a CCD (charge coupled device) used as a solid-state image pickup device.

[0002]

2. Description of the Related Art A CCD solid-state image pickup device has one line or one line on a photodiode arranged in a one-dimensional or matrix form.
The signal charges of the pixels for the field are stored, and the charges of the pixels are sequentially transferred to the floating capacitor of the CCD by horizontal scanning. This capacitor holds a transfer charge from the photodiode after a reset pulse is applied to each pixel to clear the existing charge, and this charge is transferred to the CC through the floating diffusion amplifier (FDA).
It is output as a D signal, that is, a video signal. This signal contains the reset noise (kTC noise) of the floating diffusion amplifier, and the fluctuation noise (1 / f noise) generated by the semiconductor device included in this amplifier. These noises were removed by the correlated double sampling circuit (CDS circuit) or the clamp circuit. Examples of the correlated double sampling circuit include Japanese Unexamined Patent Publication No. 3-229580, Japanese Utility Model No. 3-36138 and Japanese Utility Model No. 4-6688.
There is a signal reading device described in 0.

[0003]

In the correlated double sampling circuit, the signal level in the feed-through period following the reset period in one pixel period is clamped by the clamp pulse, and the signal in the subsequent pixel signal period is sampled. Sample by pulse. Thus, when a signal is clamped or sampled, basically a signal containing high frequency noise becomes mismatched with the Nyquist frequency of sampling and becomes 1/2 of the sampling frequency.
The noise in the above band is returned to the signal. If you limit the band to the low range before performing correlated double sampling,
Foldback noise is reduced. However, the signal waveform may be distorted, the noise suppression effect by correlated double sampling may be reduced, and this may cause signal interference between adjacent pixels, deterioration of resolution, and color mixing.

The present invention solves the above-mentioned drawbacks of the prior art, and a CCD for obtaining an image with little aliasing noise and a good SN ratio.
An object is to provide a signal reading circuit.

[0005]

In order to solve the above-mentioned problems, the present invention receives a first signal output from a CCD,
A second signal from which reset noise has been removed by correlated double sampling is output, and the first signal includes a plurality of pixel periods, each of the plurality of pixel periods including a reset period and a feedthrough period following the reset period. And a CCD signal readout circuit including a pixel signal period following the first pixel signal period.
Signal extraction means for separating the feedthrough signal and the pixel signal in each of a plurality of pixel periods, a low-pass filtering means for low-pass filtering the feedthrough signal and the pixel signal, and a filtered feedthrough signal. Signal holding means for sampling and holding, and differential amplifier means for subtracting the filtered pixel signal from the sampled and held signal and outputting a second signal are included.

Further, according to the present invention, the CCD signal reading circuit receives the first signal and separates the feedthrough signal and the pixel signal in each of the plurality of pixel periods, and the feedthrough signal and the pixel signal. Low pass filtering means for respectively low pass filtering, delay means for delaying the filtered feedthrough signal to the pixel period, and a difference for subtracting the filtered pixel signal from the delayed signal and outputting a second signal. Dynamic amplifier means.

Further, according to the present invention, the CCD signal reading circuit receives the delayed signal by the delay means for delaying the first signal to the pixel period and separates the feedthrough signal in each of the plurality of pixel periods. A first signal extraction unit, a second signal extraction unit that receives the first signal and separates the pixel signal in each of the plurality of pixel periods, and low-pass filters each of the separated feedthrough signal and pixel signal. Low pass filtering means and differential amplifier means for subtracting the filtered pixel signal from the filtered feedthrough signal to output a second signal.

Further, the CCD signal read circuit according to the present invention receives the first signal and averages the feedthrough signal and the pixel signal by a signal extracting means for separating the feedthrough signal and the pixel signal in each of the plurality of pixel periods. It includes averaging means for converting the signals into the same phase, and differential amplifier means for subtracting the signal output from the averaging means and outputting the second signal.

[0009]

According to the present invention, the feedthrough signal and the pixel signal are separated from the first signal by the signal extraction means, and these are supplied to the low-pass filtering means to obtain a signal from which high frequency noise is removed. Next, the feed through signal and the pixel signal are made in-phase by the signal holding means, delay means or averaging means, and both are subtracted by the differential amplifier means and output as the second signal. As a result, a signal in which the noise is canceled is output.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a CCD signal read circuit according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a block configuration of a CCD signal read circuit 10 according to an embodiment of the present invention, and FIG. 2 shows a timing chart of its operation.
For example, a charge-coupled device (CCD) 11 having a two-dimensional photodiode array applied to a solid-state imaging camera is a solid-state imaging device that outputs a pixel signal 100 at a clock timing of 7.16 MHz in this embodiment. In the following description, signals are designated by the reference signs of the connecting lines in which they appear. Pixel signal
As can be seen from FIG. 2, 100 has a 1 pixel period 500, which is 140 ns long in the present embodiment, which corresponds to a reset period 5
02, followed by a feedthrough period 504, and further a pixel signal period 506 following this. Reset component a
The feedthrough signal b following and the pixel signal c following this include high frequency noise n having a band of about 50 MHz. Such a pixel signal 100 has two gates
Input to 13 and 14, both gates 13 and 14 are driven by a pulse generation circuit (PG) 12 described later, and in response to gate pulses 101 and 102, a feedthrough signal 201 and a pixel signal 301 are extracted from a signal 100. It is a signal extraction circuit. The pulse generation circuit (PG) 12 is a timing signal generation circuit that generates various timing pulses for operating the respective units of the present device. For example, a signal b in the feedthrough period 504 and a signal c in the pixel signal period 506 are generated. Correspondingly, in this embodiment, a gate pulse 101 with a length of 20 ns and
102 occurs at gates 13 and 14.

The respective outputs 201 and 301 of the gates 13 and 14
Are connected to low-pass filters (LPF) 15 and 16, respectively, which have a cut-off frequency of, for example, 14 MHz and which feedthrough signal 20
Signal 20 with high-frequency noise removed from 1 and image signal 301
It is a low-pass filter that outputs 2 and 302. Their outputs 202 and 302 are correlated double sampling (CDS)
Connected to circuit 17.

The correlated double sampling circuit 17 cancels the reset noise and 1 / f noise of the charge-coupled device 11 which are correlated and superimposed on the feedthrough signal b and the pixel signal c, and minimizes them. This circuit outputs the signal 304. The correlated double sampling circuit 17 has three sample-hold circuits (SH) 18, 19 and 20, and the sample-hold circuit 18 is connected to the low pass filter 15 and the pulse generating circuit 12 and Signal in response to sampling pulse (clamp pulse) 103
It is a circuit that extracts the peak value of 202 and holds it as the signal 203. The other sample-hold circuit 20 is connected to the low-pass filter 16 and the pulse generation circuit 12, extracts the peak value of the signal 302 in response to the sampling pulse 104 from the pulse generation circuit 12, and outputs the signal corresponding to this peak value. 3
This is the circuit that holds 03. Still another sample and hold circuit 19 is a circuit which is connected to the sample and hold circuit 18, samples the signal 203 in response to the sampling pulse 104 from the pulse generation circuit 12, and holds the signal 204 corresponding thereto. Sample and hold circuits 19 and 20
The respective outputs 204 and 303 are connected to the differential amplifier 21, and the differential amplifier 21 is an arithmetic circuit that subtracts the signal 303 from the signal 204 and outputs the image signal 304.

In operation, the charge coupled device 11
Outputs the pixel signal 100 at the 7.16MHz clock timing. Pixel signal 100 is input to gates 13 and 14,
The gates 13 and 14 extract the feedthrough signal 201 and the pixel signal 301 from the pixel signal 100 in response to the gate pulses 101 and 102 from the pulse generating circuit 12, respectively. The extracted feed-through signal 201 is input to the low-pass filter 15, high-frequency noise in a band higher than the cutoff frequency is removed, and the signal 202 is input to the sample-hold circuit 18. Sample and hold circuit 18
Extracts the peak value of the signal 202 with the sampling pulse 103 and holds it as the signal 203. Retained signal 203
Is input to the sample-and-hold circuit 19 and is sampled by the sampling pulse 104 and the corresponding signal 20
Retained as 4

According to this embodiment, the input pixel signal is low-pass filtered to remove high-frequency noise, and then the correlated double sampling circuit 17 samples and holds it. Therefore, the reduction of the SN ratio due to the return of high frequency noise is small. Further, the gate circuits 13 and 14 separate the feed-through signal and the pixel signal, and then perform low-pass filtering. Therefore, there is no reduction in the noise suppression effect of the correlated double sampling circuit 17 due to the rounding of the waveform, and the CCD
Signal reset noise and 1 / f noise are suppressed and SN
An image with good ratio can be obtained.

On the other hand, the pixel signal 301 extracted by the gate 14
Is input to the low-pass filter 16 to remove high-pass noise higher than its cutoff frequency. The high frequency-removed signal 302 is input to the sample hold circuit 20, and the sample hold circuit 20 holds the signal 303 corresponding to the peak value of the signal 302 by the sampling pulse 104. The signals 204 and 303 held in the sample-hold circuits 19 and 20 in this way are input to the differential amplifier 21, which subtracts the latter signal 303 from the former signal 204 and outputs the image signal 304. . As a result, the image signal 30
4 is a signal in which the reset noise and 1 / f noise of the charge coupled device 11 which are superimposed in correlation with the feedthrough signal b and the pixel signal c are canceled. In particular, sampling noise (clock noise) generated during sample hold is canceled by the subtraction of the differential amplifier 21.

Another embodiment of the CCD signal read circuit according to the present invention is shown in FIG. The CCD signal read circuit 23 according to the embodiment of the figure is different from the circuit 10 of the embodiment shown in FIG. 1 in that a delay (DL) circuit 24 is provided in place of the sample hold circuit 18. In the following figures, similar components are designated by the same reference numerals. Further, FIG. 4 shows still another embodiment of the CCD signal reading circuit according to the present invention. The circuit 26 of this embodiment differs from the circuit 23 of FIG. 3 in that the delay circuit 24 in the circuit 23 of the embodiment of FIG. 3 is provided between the output 100 of the charge coupled device 11 and the gate 13. In the embodiments of both figures, the delay circuits 24 and 27 delay the feedthrough signal b of the CCD signal 100, make it in phase with the pixel signal c, and send it to the differential amplifier 21, as can be seen from FIG. Is used to cancel the correlation noise.

According to these embodiments, the input pixel signal is low-pass filtered to remove high-frequency noise, and then the sampling circuits 19 and 20 sample and hold it. Therefore, the SN due to the aliasing of high frequency noise
Little decrease in ratio. Further, the gate circuits 13 and 14 separate the feed-through signal and the pixel signal, and then perform low-pass filtering. Therefore, there is no reduction in the noise suppressing effect of the correlated double sampling circuit 17 due to the rounding of the waveform,
Reset noise and 1 / f noise of the CCD signal are suppressed and an image with a good SN ratio can be obtained.

FIG. 6 shows still another embodiment of the CCD signal read circuit according to the present invention. The CCD signal readout circuit 29 shown in the figure replaces the sample hold circuit 18 in the circuit 10 of the above-described embodiment with a peak detection circuit (PD) 30 at the output 202 of the low-pass filter 15 and another peak detection circuit 31. Are provided at the output 302 of the low-pass filter 16, respectively.
On the other hand, the peak detection circuit 30 is a circuit for converting the feed-through signal b output from the low pass filter 15 into a swept waveform 206, as shown in the time chart of FIG. The other peak detection circuit 31 is a circuit that converts the pixel signal c output from the low-pass filter 16 into a swept waveform 306 (FIG. 7). As can be seen from FIG. 7, these sweep waveforms 206 and 306 are waveforms that follow the peaks of the input signals 202 and 302, respectively, and then gradually attenuate. This makes it possible to obtain a substantial peak value of the pixel signal c output from the low-pass filter 16 or a signal corresponding thereto. Such waveform manipulations are referred to herein as "averaging," and such waveforms are referred to as "sweep waveforms." The two sample and hold circuits 19 and 20 in the latter stages of the two circuits 30 and 31, respectively, have sweep waveforms 206 and 206, respectively.
And 306 are simultaneously sampled in response to pulse 104 and held on them.

9 and 10 show examples of circuits applied to the peak detection circuits 30 and 31. The circuit shown in FIG. 9 has a transistor Q1 that receives and amplifies the input (IN) signal 202 or 302, and its emitter 520 outputs it.
Connected to (OUT) terminal 206 or 306. Emitter 520
Further, a constant current circuit I and a capacitor C are connected to. In addition, the circuit shown in FIG.
2 has a differential amplifier 530 that receives and differentially amplifies it, and its output 532 is output via a diode D (O terminal 2
Connected to 06 or 306. Output of differential amplifier 530 532
Is also connected to the constant current circuit I and the capacitor C via the diode D, and is also connected to the inverting input (-) of the differential amplifier 530. The peak detection circuit 30 or 31 shown in FIG. 9 amplifies the input signal IN with the transistor Q1 and thereby the capacitor C is rapidly charged. As the peak value of the input signal IN decreases, the capacitor C gradually discharges and outputs a sweep waveform 206 or 306 with a constant slope.
Output to OUT. Peak detection circuit 30 or 31 shown in Figure 10
Amplifies the input signal IN with the amplifier 530 to rapidly charge the capacitor C. The other points are the same as those of the circuit shown in FIG.

Details of these operations are shown in the time chart of FIG. In the figure, if the pulse width TW of the input signals 201 and 301 are identical to each other as shown in FIG. 7, each of which peak values VF _P and VS _P is the input signal as shown in Equation (1)
Since they are proportional to the average values of the crest values VF and VS of IN (indicated by ~), they are equivalent to the output signals b and c of the charge coupled device 11, respectively. At the time of actual sample and hold, the peak values are decreased by ΔVF and ΔVS, respectively.

[0021]

[Equation 1] From the equation (1), the voltage Vout at the output 308 of the differential amplifier 21
Is as shown in equation (2).

[0022]

[Equation 2] Since (ΔVF −ΔVS) in the equation (2) is a constant value, the output voltage Vout is proportional to the difference between the peak values VF and VS of the input signal IN. Therefore, the circuit 29 of the embodiment shown in FIG. 6 outputs the difference between the feedthrough signal b and the pixel signal c to the output 308, as in the embodiment circuit 10 of FIG.

FIG. 11 shows a further embodiment circuit 33 of the CCD signal reading circuit according to the present invention. This circuit 33 replaces the low pass filters 15 and 16 and the peak detection circuits 30 and 31 in the circuit 29 of FIG. 6 with an average value detection circuit (M
D) 34 and 35 are provided. The average value detection circuits 34 and 35 have a converter 540 that converts the input voltage 201 or 301 into a current, a limiter 40, and a capacitor C1 as in the circuit example shown in the functional block of FIG. Alternatively, it is a circuit that integrates 301 and converts it into a sweep signal with a constant slope. 15 and 17 show specific examples of such an integrating circuit with a limiter.

In the circuit shown in FIG. 15, the circuit including the transistors Q2 and Q3 constitutes a voltage-current conversion circuit 540, and the limiter 40 is arranged on the output side thereof. The limiter 40 is
This is a circuit that sets the charging start voltage of the capacitor C1 to a predetermined value. In this concrete circuit, constant current circuits 37, 38 and
Let 39's currents be I ₁ , I ₁ and I ₂ , respectively. The current I ₂ of the constant current circuit 39 is I ₂ = I ₁ + I ₀ . Referring to the time chart of FIG. 16, the input voltage V _S charges the capacitor C1 with the current I _C1 = V _S / RI ₀ in the period t ₁ . Capacitor C1
Discharges in the period t ₂ , and the discharge current becomes I _C1 = −I ₀ .
At the time period t ₃ , the limiter 40 is turned on and holds the constant voltage V ₀ .

A time chart of the CCD signal read circuit 33 shown in FIG. 11 is shown in FIG. As can be seen, the feedthrough signal b and the pixel signal c are converted into sweep signals 210 and 310 by the average value detection circuits 34 and 35, respectively, and sampled by the sample hold circuits 19 and 20 simultaneously in response to the sampling pulse 104. To be held. Outputs of sample and hold circuits 19 and 20 207 and
The difference between 307 is output from the output 308 of the differential amplifier 21. Referring to the detailed time chart of FIG. 14, the equation (3)
become that way.

[0026]

[Equation 3] However, k and K are constants.

Each potential VFS and VS at the time of sampling
S is VFS = VF ₀ + VF _P -ΔV _a ΔV _a = I ₀ T _a / c VSS = VS ₀ + VS _P -ΔV _b ΔV _b = I ₀ T _b / c where ΔV _a and ΔV _b are constant values Is. Therefore, the output voltage Vout of the output 308 of the differential amplifier 21 is expressed by the equation (4).

[0028]

[Equation 4] However, A = VF ₀ -VS ₀ -ΔV _a + ΔV _b is a constant value. Similar to the circuit 29 of the embodiment shown in FIG. 6, the output voltage of the output 308 of the differential amplifier 21 of the CCD signal read circuit 33 shown in FIG.
As shown in.

[0029]

[Equation 5] The same applies to specific examples of the average value detection circuits 34 and 35 shown in FIG.

A circuit 40 of yet another embodiment of a CCD signal readout circuit according to the present invention is partially shown in FIG. Portions not shown in the figure may have the same configurations as those of the other embodiments described above. This circuit 40 is the circuit 33 shown in FIG. 11 in which the output 210 of the average value detection circuit 34 is provided with the sample hold circuit 18, and its output 211 is connected to the sample hold circuit 19. A clamp pulse 103 is supplied from the pulse generation circuit 12 to the sample hold circuit 19. In this case, the average value detection circuits 34 and 35 may include a low pass filter and a peak value detection circuit.

The charge-coupled device 11 has a three-primary-color filter in the case of a color image pickup device. The CCD signal read circuit 33 of FIG. 11 corresponds to these three-primary-color signals R, G, and B.
You may provide three sets. An example of the configuration is shown in FIG. In this configuration example, the gates 12 and 14 in each readout circuit 33 are energized in synchronization with the readout timing of the three primary color signals R, G and B from the charge coupled device 11 and their respective outputs 3 are output.
In 08, the primary color signal with reset noise and 1 / f noise suppressed is output.

FIG. 20 shows that when the charge coupled device 11 is also a color image pickup device, the gates 13 and 14 and the low-pass filters 15 and 16 are commonly provided for the three primary color signals, for example, R, G and B. Pair of sample and hold circuits 50
Is a circuit configuration example dedicated to each of the three primary color signals R, G, and B. In this circuit example, the sample and hold circuits included in each sample and hold circuit 50 are
When 19 and 20 are driven at the timings of the corresponding three primary color signals R, G and B, their respective outputs 308
A primary color signal with reset noise and 1 / f noise suppressed is output to.

According to these embodiments, the input pixel signal is low-pass filtered or integrated, and then sampled and held. Therefore, the reduction of the SN ratio due to the return of high frequency noise is small. Also, the gate circuit 13 and
The feedthrough signal and the pixel signal are separated by 14 and then low-pass filtered or integrated. Therefore, there is no reduction in the noise suppression effect of correlated double sampling due to the rounding of the waveform. Furthermore, when using peak detection or integration, the timing accuracy of sampling is greatly relaxed. Further, the peak-detected or integrated feed-through signal and pixel signal can be sampled and held at the same timing, which simplifies the circuit configuration.

[0034]

As described above, according to the present invention, the feed-through signal and the pixel signal are separated, low-pass filtered to remove high-frequency noise, and the correlated double sampling circuit performs sampling. Therefore, there is no aliasing noise and the reset noise of the CCD signal and the noise suppression effect of the correlated double sampling circuit are not reduced.
It is possible to suppress 1 / f noise and obtain an image with a good SN ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a CCD signal read circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the CCD signal read circuit according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the CCD signal read circuit according to the present invention.

5 is a waveform chart for explaining the operation of the embodiment shown in FIGS. 3 and 4. FIG.

FIG. 6 is a block diagram showing another embodiment of the CCD signal read circuit according to the present invention.

FIG. 7 is a time chart for explaining the operation of the embodiment shown in FIG.

8 is a waveform chart for explaining the operation of the embodiment shown in FIG.

9 is a functional circuit diagram showing an example of a peak detection circuit in the embodiment shown in FIG.

10 is a functional circuit diagram showing another example of the peak detection circuit in the embodiment shown in FIG.

FIG. 11 is a block diagram showing still another embodiment of the CCD signal read circuit according to the present invention.

12 is an explanatory diagram showing a functional configuration of an average value detection circuit in the embodiment shown in FIG.

13 is a time chart for explaining the operation of the embodiment shown in FIG.

14 is a waveform chart for explaining the operation of the embodiment shown in FIG.

15 is a circuit diagram showing an example of an integrating circuit with a limiter shown in FIG.

16 is a time chart for explaining the operation of the circuit shown in FIG.

FIG. 17 is a circuit diagram showing another example of the limiter-integrated circuit shown in FIG.

FIG. 18 is a block diagram partially showing still another embodiment of the CCD signal read circuit according to the present invention.

FIG. 19 is a block diagram showing an example in which a CCD signal read circuit according to the present invention is applied to a circuit of a color image pickup device.

FIG. 20 is a block diagram showing another example in which the CCD signal readout circuit according to the present invention is applied to the circuit of a color imaging device.

[Explanation of symbols]

 10, 23, 26, 33, 40 CCD signal readout circuit 11 Charge coupled device 12 Pulse generation circuit 13, 14 Gate 15, 16 Low pass filter 17 Correlated double sampling circuit 18 to 20, 50 Sample hold circuit 21 Differential amplifier 24, 27 Delay circuit 30, 31 Peak detection circuit 34, 35 Average value detection circuit 37, 38, 39 Constant current circuit 40 Limiter

Claims (7)

[Claims] 1. A first signal output from a charge coupled device (CCD) is output, and a second signal from which reset noise is removed by correlated double sampling is output, and the first signal is a plurality of pixels. In the CCD signal readout circuit including a period, each of the plurality of pixel periods includes a reset period, a feed-through period following the reset period, and a pixel signal period following the feed-through period, the circuit comprises: A signal extracting means for receiving a signal and separating a feedthrough signal and a pixel signal in each of the plurality of pixel periods; a lowpass filtering means for lowpass filtering the feedthrough signal and the pixel signal respectively; and the filtered feed. Signal holding means for sampling and holding the through signal; and subtracting the filtered pixel signal from the sampled and held signal, CCD signal read circuit which comprises a differential amplifier means for outputting a signal. 2. A first signal output from the CCD,
A second signal from which reset noise has been removed by correlated double sampling is output, and the first signal includes a plurality of pixel periods, each of the plurality of pixel periods including a reset period and a feed following the reset period. In a CCD signal readout circuit including a through period and a pixel signal period following the feed through period, the circuit receives a first signal and separates the feed through signal and the pixel signal in each of the plurality of pixel periods. Extraction means, low-pass filtering means for low-pass filtering the feed-through signal and pixel signal, respectively, delay means for delaying the filtered feed-through signal to the pixel period, and filtering the delayed signal from the delayed signal. And a differential amplifier circuit for subtracting the pixel signal and outputting a second signal. 3. A first signal output from the CCD,
A second signal from which reset noise has been removed by correlated double sampling is output, and the first signal includes a plurality of pixel periods, each of the plurality of pixel periods including a reset period and a feed following the reset period. In a CCD signal readout circuit including a through period and a pixel signal period subsequent to the feed through period, the circuit is configured to delay a first signal to the pixel period, and a delay unit that receives the delayed signal. First signal extraction means for separating the feedthrough signal in each of the pixel periods, second signal extraction means for receiving the first signal and separating the pixel signal in each of the plurality of pixel periods, Low-pass filtering means for low-pass filtering the filtered feed-through signal and the pixel signal, respectively, and the filtered signal from the filtered feed-through signal. CCD signal read circuit which comprises a differential amplifier means for outputting a second signal by subtracting the pixel signal. 4. A first signal output from the CCD is received,
A second signal from which reset noise has been removed by correlated double sampling is output, and the first signal includes a plurality of pixel periods, each of the plurality of pixel periods including a reset period and a feed following the reset period. In a CCD signal readout circuit including a through period and a pixel signal period following the feed through period, the circuit receives a first signal and separates the feed through signal and the pixel signal in each of the plurality of pixel periods. An extracting means, an averaging means for averaging the feed-through signal and the pixel signal respectively to make them in phase, and a differential amplifier means for subtracting a signal output from the averaging means and outputting a second signal. CCD signal readout circuit characterized by the following. 5. The circuit according to claim 4, wherein the averaging means comprises low-pass filtering means for low-pass filtering the extracted feedthrough signal and pixel signal, respectively, and the filtered feedthrough signal and A CCD signal readout circuit comprising a peak detecting means for detecting a substantial peak value of a pixel signal. 6. The circuit according to claim 4, wherein the averaging means includes integrating means for integrating the extracted feedthrough signal and pixel signal.
D signal readout circuit. 7. The circuit according to claim 1, wherein the CCD is a color image pickup device that generates a plurality of color signals, and the CCD signal read circuit is provided for each of the plurality of color signals. A CCD signal reading circuit, which is provided.