JP3993251B2 - CCD signal readout circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a signal readout circuit of a solid-state imaging device, and more particularly to a signal readout circuit suitable for readout of a signal from a CCD (Charge Coupled Device).
[0002]
[Prior art]
The CCD solid-state imaging device sequentially reads out the signal charges stored in the charge-coupled device, temporarily stores them in the floating capacitor, and then outputs them through a floating diffusion amplifier (FDA). This output signal has a feedthrough period and a signal period for each pixel period, and has respective signal levels. The feedthrough level and signal level include reset noise (kTC noise) and fluctuation noise (1 / f noise). The reset noise is generated due to the resetting of the floating diffusion amplifier. Fluctuation noise is low-frequency noise generated by semiconductor devices included in the FDA. These noises are correlated. In order to remove the correlation noise from the signal level, a technique is known in which signals at both levels are clamped, sampled and extracted by a correlated double sampling circuit (CDS circuit), and a difference is obtained. The correlated double sampling circuit is effective for such correlation noise. For example, an integral-type correlated double sampling circuit described in Japanese Utility Model Publication No. 3-36138 is known.
[0003]
[Problems to be solved by the invention]
The output signal of the solid-state imaging device includes uncorrelated high frequency noise generated by the FDA. However, this cannot be removed by the correlated double sampling circuit. On the contrary, the signal is folded back to the signal due to the clamp and sample hold operations of the correlated double sampling circuit, so that the components in the band increase on the contrary, causing the S / N to deteriorate. In the conventional example, in order to remove the high-frequency noise, an integral type sample-and-hold circuit as described in the above publication is used. However, this circuit has a problem that the circuit configuration is complicated and a high-speed pulse is required.
[0004]
It is an object of the present invention to provide a CCD signal readout circuit that eliminates the disadvantages of the prior art and does not complicate the circuit configuration, reduces aliasing of high-frequency noise, and can cope with high-speed signal readout. To do.
[0005]
[Means for Solving the Problems]
According to the present invention, a first signal including a plurality of pixel periods and each of the plurality of pixel periods including a feedthrough period and a signal period is received from the charge coupled device (CCD), and the correlation noise included in the signal period is received. And a CCD signal readout circuit that outputs a second signal with reduced high-frequency noise, receives the first signal, extracts the feedthrough period and the level of the signal period in each of the plurality of pixel periods, Signal extraction means for making a pixel signal, signal inversion means for inverting one of the feedthrough signal and the pixel signal and outputting it as a serial signal, and averaging the serial signal, the correlated noise and high-frequency noise are thereby reduced. Averaging means for outputting a reduced signal.
[0006]
According to the present invention, the CCD signal readout circuit further advantageously includes a signal holding means for sampling and holding the signal output from the averaging means and outputting it as a second signal.
[0007]
According to the present invention, at least a part of at least a part of the signal extraction means, signal inversion means, averaging means, and signal holding means is prepared, and these means are operated in different pixel periods. Also good.
[0008]
Further, according to the present invention, when the first signal is a color image signal, at least a part of the signal extraction unit, the signal inversion unit, the averaging unit, and the signal holding unit forms a color image signal. It is preferable to prepare a plurality of systems corresponding to the color signals and operate these means in a pixel period corresponding to the color signals.
[0009]
[Action]
According to the present invention, when receiving the first signal from the CCD, the signal extraction means separates and extracts the feedthrough level and the signal level for each pixel period. The signal inversion means inverts one of the feedthrough level and the signal level, and both signals are averaged by the averaging means. Thereby, correlation noise is canceled and high frequency noise is also reduced. The signal holding means samples and holds the output signal of the averaging means and outputs the second signal. As described above, since the gate circuit is used for signal extraction for removing the correlation noise, the circuit configuration becomes simpler than the conventional method using the correlated double sampling circuit including the sample hold circuit.
[0010]
【Example】
Next, an embodiment of a CCD signal readout circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0011]
FIG. 1 shows a block configuration of an embodiment of a CCD signal readout circuit 10 of the present invention, and FIG. 2 is a timing chart thereof. The CCD signal readout circuit 10 of the embodiment is a noise reduction circuit that removes the aliasing of high-frequency noise from the image signal output from the solid-state imaging device 11 and outputs it to the output 101 thereof. The CCD signal readout circuit 10 extracts the level of the feed-through period and the level of the signal period by the gate circuits 13 and 14, respectively, obtains the difference between the two, and then performs low-pass filtering or integration to obtain CCD reset noise and CCD output. Reduce the low frequency noise of the amplifier. Also, by sampling and holding the signal resulting from filtering or integration, a good S / N ratio can be obtained without aliasing high-frequency noise. In the following description, a signal is designated by the reference number of the connecting line that appears.
[0012]
The solid-state imaging device 11 is a charge coupled device (CCD), has a plurality of CCD cells, images the object scene, sequentially reads out the signal charges stored in the CCD cells, and reads them into a floating capacitor (not shown) 1 and then sequentially outputs to its output 100 through a floating diffusion amplifier (FDA) (not shown). As shown in FIG. 2, the output signal 100 from the charge coupled device 11 includes a feedthrough level b and a signal level c on which a reset component a and noise Ni (i is a natural number corresponding to a pixel number) are superimposed for each pixel period T. There is. Noise Ni includes correlated reset noise, low-frequency fluctuation noise (1 / f noise) from FDA, and uncorrelated high-frequency noise. The output 100 of the charge coupled device 11 is connected to the amplifier 12. The amplifier 12 amplifies the output signal 100 of the charge coupled device 11 to a processing level, and its output 102 is connected to gate circuits (G) 13 and 14.
[0013]
The gate circuits 13 and 14 extract the signal levels b and c of the output signal 100 of the amplifier 12 by gate pulses 130 and 140, and separate them into a feed-through level signal 131 including noise Ni and a pixel signal 141 including noise Ni. And a signal extraction circuit for outputting to the differential amplifier 15. As shown in FIG. 2, the gate pulses (PG) 130 and 140 are gate pulses that are synchronized with the feedthrough period b and the signal period c, respectively, and have substantially the same width. The differential amplifier 15 receives a feedthrough level signal 131 and a pixel signal 141 at its input terminals (+, −), respectively, and inverts the latter to output a serial signal 150 to the noise removal circuit (NR) 16. It is. Of course, the signal 131 of the feedthrough level may be inverted to maintain the polarity of the pixel signal 141. The noise removal circuit 16 is a circuit that cancels out-of-phase noise (Ni, −Ni) in the output signal 150 of the differential amplifier 15 and reduces high-frequency noise. In this embodiment, the noise removal circuit 16 is realized by a low-pass filtering function or an integration function, as will be described later. An output 161 of the noise removal circuit 16 is connected to an input of a signal holding circuit (SH) 17. The signal holding circuit 17 is a sample and hold circuit that samples and holds the output signal of the noise removing circuit 16 and outputs the sampled signal to the output 101 thereof. Note that the signal holding circuit 17 may not be provided.
[0014]
Two configuration examples of the gate circuits 13 and 14 of FIG. 1 are shown in FIGS. 3 and 5, and signal waveforms thereof are shown in FIGS. 4 and 6, respectively. The upper half of FIG. 3 schematically shows the gate circuit 13 or 14, and the lower half shows a specific configuration example. The switch 200 is in a connection state in which the constant voltage VR is output to the output terminal (OUT) 201 in a normal state. When the gate pulse (PG) 202 is input, the switch 200 outputs the input signal of the input terminal (IN) 203 as the output signal 201 in response to the input. The configuration example shown in FIG. 5 has a relative emitter follower 210, and a gate pulse 214 and a signal 215 are applied to the bases 212 and 213, respectively. As shown in FIG. 6, the gate pulse 214 normally has a voltage VR higher than the signal 215, and the voltage of the output signal 211 is equal to VR-Vbe, where the base-emitter voltage is Vbe. When the gate pulse 214 is input and the potential of the base 212 falls below the potential of the base 213, a signal corresponding to the signal 215 appears at the output terminal 211. With the above method, the gate circuits (G) 13 and 14 in FIG. 1 extract the input signal.
[0015]
FIG. 7 shows a configuration example in which the noise removal circuit 16 of FIG. 1 is realized by an integration circuit, and the output 161 of the integration circuit 16 is connected to the signal holding circuit 17 in the next stage. The signal waveform diagram is shown in FIG. The upper half of FIG. 7 schematically shows the integrating circuit 16 and its subsequent stage, and the lower half shows a specific configuration example. In the integrating circuit 16, the amplifier 220 having an amplification factor gm receives the CCD signal 150 from the differential amplifier 15 of FIG. 1 and amplifies it, and supplies a current corresponding to it to the output-side capacitor 221. The capacitor 221 is charged by the CCD signal 150 while the reset switch 222 is open. At this time, the charge voltage signal 250 is integrated with the levels of the feedthrough period b and the signal period c to which the same amount of reset noise is added with opposite polarities, thereby removing the reset noise. Further, the high frequency noise is averaged by this integration operation, and the high frequency noise can be greatly reduced.
[0016]
In this way, a signal in which the anti-phase noise (Ni, −Ni) is canceled and the high frequency noise is reduced is input to the holding circuit 17. This signal conversion is referred to herein as “averaging”. Thus, according to the integration circuit, high frequency noise can be removed together with reset noise. In the signal holding circuit 17 in the next stage, the input signal 250 is amplified by the amplifier 260, and the capacitor 263 is charged by the switch 262 that is closed in response to the sample hold pulse (SHP) 261. The charging waveform signal 101 is output as a device output. Thereafter, when one pixel period T elapses, a reset pulse (RS) 265 is generated and the reset switch 222 is closed, whereby the capacitor 221 of the integrating circuit 16 is discharged and cleared. As described above, according to the integrating circuit 16, high frequency noise is removed from the output signal. Therefore, even if sample holding is performed by the signal holding circuit 17 in the subsequent stage, no aliasing noise is generated.
[0017]
The noise removal circuit 16 by the integrating circuit may also include an amplifier 220a having a differential input instead of the amplifier 220 shown in FIG. An example of this is shown in FIG. The amplifier 220a has a non-inverting input (+) and an inverting input (-) differential input, the non-inverting input (+) has the output 131 of one gate circuit 13 and the inverting input (-) has the other input. The output 141 of the gate circuit 14 is connected. By doing so, the differential amplifier 15 in the embodiment shown in FIG. 1 can be omitted.
[0018]
FIG. 9 shows signal waveforms when the noise removal circuit 16 is realized with a low-pass filter. The low-pass filter 16 can smooth the signal component and reduce the noise component by setting the band to 1/2 or less of the sampling frequency f _s = 1 / T of the signal holding circuit 17 . That is, the noise removal circuit 16 averages the CCD signal 150 by the low-pass filter and outputs the read signal 101 with a reduced noise component, as in the case where the noise removal circuit 16 is constituted by an integration circuit. When the noise removal circuit 16 includes such a low-pass filter, the signal holding circuit 17 may not be provided. Furthermore, a trap for removing the same frequency as the carrier component (f _s ) of the next sample and hold circuit 17 may be added to the filter 16.
[0019]
In the operating state of the CCD signal readout circuit 10 of FIG. 1, the output signal 100 of the solid-state image pickup device (CCD) 11 is amplified by the amplifier 12 and input to the gate circuits 13 and 14, and partly by the gate pulses 130 and 140. The two signals 131 and 141 are extracted and input to the input terminals + and − of the differential amplifier 15. The differential amplifier 15 receives the input signals 131 and 141, inverts the latter, converts it to the serial signal 150 shown in FIG. 2, and outputs it. The noise removal circuit 16 averages by a low-pass filter or integration, that is, in the case of an integration circuit, cancels out the anti-phase noise Ni of the input signal 150 and reduces the high-frequency noise and supplies it to the signal holding circuit 17. The signal holding circuit 17 samples and holds the output of the noise removing circuit 16 and outputs a read signal 101.
[0020]
In the correlated double sampling circuit according to the prior art, the sample hold circuit is provided in the gate circuits 13 and 14 in this embodiment. The gate circuits 13 and 14 in the present embodiment have a simple circuit configuration and no hold capacitance compared to the sample and hold circuit, and can operate at high speed.
[0021]
By the way, when the solid-state imaging device 11 is a type that outputs the three primary color signals red (R), green (G), and blue (B), for example, dot-sequentially, it is effective to provide a CCD signal readout circuit for each color system. It is. FIG. 10 shows an example of the readout circuit 30, and FIG. 12 shows a timing chart thereof. Here, when the solid-state imaging device 11 is a color imaging device, the color output signal is denoted by reference numeral 300 for convenience. The amplifier 12 amplifies the output signal 300. On the output side of the amplifier 12, read circuit blocks 31, 32 and 33 are provided for the color systems of the color signals R, G and B, respectively. Here, for the sake of simplification of the drawing, only the read circuit blocks 31 and 32 are shown, but the circuit 33 shows only the numbers and omits the block display. However, these circuit blocks 31, 32 and 33 have the same configuration and function, and in the following drawings, the same function as the element shown in FIG. In this embodiment, the noise removal circuit 16 is composed of an integration circuit. Of course, a low-pass filter may be used.
[0022]
Referring to the timing chart of FIG. 11, in the signal R of the CCD dot sequential color output signal 300, the noise N1 of the feedthrough level 301 is superimposed on the signal S1 of the signal level 302. The signal S2 has a feedthrough level 401 noise N2. This output signal 300 passes through the amplifier 12 and enters the gate circuits 13, 14 of each block 31, 32 and 33. In the R signal block 31, sampling pulses 303 and 304 generated at the R signal extraction timing are supplied to the gate circuits 13 and 14, whereby the R signals 303 R and 304 R extracted by the gate circuits 13 and 14 are differentially output. Input to the amplifier 15. The output signal 305 of the differential amplifier 15 passes through the integrating circuit 16 and becomes an R signal 306 from which noise N1 has been removed. The resulting signal 306 enters the signal holding circuit 17, which outputs an R color signal 307.
[0023]
Similarly, in the G signal block 32, sampling pulses 403 and 404 generated at the G signal extraction timing are supplied to the gate circuits 13 and 14, whereby the G signal 403 G extracted by the gate circuits 13 and 14 is supplied. 404G are input to the differential amplifier 15. The output signal 405 of the differential amplifier 15 passes through the integrating circuit 16, becomes a G signal 406 from which noise N2 has been removed, enters the signal holding circuit 17 and outputs a G color signal 407. The B signal block 33 (not shown) operates in the same manner for the B signal, and a B color signal from which the noise N3 has been removed is output to its output 507 (not shown). By paralleling the signal readout paths for the color signals R, G, and B in this way, it is possible to perform higher-speed readout than the one-system readout circuit shown in FIG. Conversely, if each of the readout circuit blocks 31, 32, and 33 is viewed individually, the requirements for the operation timing may be looser than the one-system circuit configuration shown in FIG. Can do.
[0024]
In this embodiment, the charge-coupled device 11 is a type that outputs a color image signal dot-sequentially. In such a case, it is advantageous to provide the circuit blocks 31, 32, 33 according to the system of the color signals R, G, B as described above. However, the present invention does not necessarily need to be based on such color signal blocking. For example, two blocks, for example, 31 and 32, may be provided, and the image signal may be distributed to both blocks 31 and 32 for every alternate pixel period. The image signal input from the charge coupled device 11 may not be a color image signal. Further, the charge coupled device 11 may not be a type that outputs a color image signal dot-sequentially, and may be a type that outputs line-sequentially, for example.
[0025]
FIG. 12 partially shows another embodiment of the present invention, and this CCD signal readout circuit 40 has a single system from the output side of the amplifier 12 to the differential amplifier 15 in the embodiment of FIG. The 15 outputs 308 and thereafter are divided into three systems for each color signal as in FIG. For this purpose, a selector switch 41 is connected to the output 308 of the differential amplifier 15, and the switch 41 is a selection circuit that selects three systems in synchronization with the color signal. As in the embodiment of FIG. 1, gate pulses 130 and 140 synchronized with the pixel period are input to the gate circuits 13 and 14, respectively. The outputs 306 and 406 and thereafter of the noise removal circuit 16 may be the same as in the embodiment shown in FIG.
[0026]
FIG. 13 is applicable to the embodiment shown in FIG. 10 or FIG. 12, and the outputs 306 and 406 of the noise removal circuit 16 in the three blocks 31, 32 and 33 are converted into dot sequential image signals. An example of the signal output circuit 42 for conversion is shown. In this circuit 42, a single capacitor 263 is connected to the output side 306 and 406 of the sample switch 262 (FIG. 7) of the three signal holding circuits 17, and the single capacitor 263 is connected to the device output 101 through the amplifier 410. It is connected. The switch 262 operates with a sample-and-hold pulse for each system, and the output is held by a single capacitor 263, whereby a dot sequential output signal 101 is output. In other words, the circuit 42 simultaneously realizes a sample hold function and a signal unification function.
[0027]
【The invention's effect】
As described above, according to the present invention, since the conventional correlated double sampling circuit including the sample hold circuit is not used, the circuit is simplified. Therefore, the processing at a higher speed than the conventional one is easy.
[0028]
The feedthrough level and the signal level in the pixel period of the CCD readout signal are extracted, one of them is inverted and added to the other, and correlation noise caused by CCD reset and low-frequency fluctuation noise caused by the CCD output amplifier (1 / f Noise) is canceled by averaging operation, and high frequency noise is removed. Therefore, since the high frequency noise has already been removed, even when the signal is held by the sample hold in the next stage, the high frequency noise aliasing due to the sampling frequency is compared with the conventional correlated double sampling circuit. It is possible to obtain a pixel signal with a small S / N ratio.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of an embodiment of a CCD signal read circuit according to the present invention.
FIG. 2 is a timing chart showing an operation example of the embodiment shown in FIG. 1;
FIG. 3 is a functional diagram showing a configuration example of a gate circuit in the embodiment of FIG. 1;
4 is a timing chart showing an operation example of the gate circuit shown in FIG. 3;
FIG. 5 is a functional diagram showing another configuration example of the gate circuit in the embodiment of FIG. 1;
6 is a timing chart showing an operation example of the gate circuit shown in FIG. 5. FIG.
7 is a functional diagram showing a configuration example of a noise removal circuit and a signal holding circuit in the embodiment of FIG. 1. FIG.
FIG. 8 is a timing chart showing an operation example of the embodiment shown in FIG.
FIG. 9 is a timing chart showing an operation example of another configuration example of the noise removal circuit in the embodiment of FIG. 1;
10 is a functional block diagram similar to FIG. 1, showing an embodiment of a CCD signal readout circuit in which the present invention is applied to each color signal system of three primary color signals. FIG.
FIG. 11 is a timing chart showing an operation example of the embodiment shown in FIG. 10;
12 is a block diagram showing a configuration example in which the CCD signal input unit is made into one system in the embodiment of FIG. 10;
13 is a circuit configuration diagram showing a circuit example in which the final output stage of the CCD signal readout circuit for each color signal system is made one line in the embodiment shown in FIG.
14 is a circuit configuration diagram showing a configuration example of a noise removal circuit in which the integration circuit shown in FIG. 7 is realized by a differential amplifier.
[Explanation of symbols]
10, 30, 40 CCD signal readout circuit
11 Solid-state imaging device
12 Amplifier
13, 14 Gate circuit
15 Differential amplifier
16 Noise reduction circuit
17 Signal holding circuit

Claims (8)

A first signal including a plurality of pixel periods and each of the plurality of pixel periods including a feedthrough period and a signal period is received from a charge coupled device (CCD), and correlation noise and high frequency noise included in the signal period are received. In a CCD signal readout circuit that outputs a reduced second signal, the circuit comprises:
Receiving the first signal, in each of the plurality of pixel period, the level between the feed-through phase, the first signal and the first gate pulse is input, in response to a constant voltage to the first gate pulse Instead, the signal is extracted by a first gate circuit that outputs a signal of the feedthrough period, and the level of the signal period is input by the first signal and the second gate pulse, and is responsive to the second gate pulse. A signal extracting means for extracting a signal of the signal period instead of a constant voltage by a second gate circuit to be a feedthrough signal and a pixel signal, respectively;
A signal inversion means for inverting one of the feedthrough signal and the pixel signal and outputting it as a serial signal;
Averaging means for averaging the serial signal, thereby outputting a signal with reduced correlated noise and high frequency noise ,
The CCD signal readout circuit , wherein the first and second gate pulses are synchronized with the extracted feedthrough period and signal period, respectively, and have the same pulse width .   2. The CCD signal readout circuit according to claim 1, further comprising signal holding means for sampling and holding the signal output from the averaging means and outputting the signal as a second signal. circuit.   3. The CCD signal readout circuit according to claim 1, wherein the averaging means includes an integration circuit for integrating the serial signal over one pixel period.   2. The CCD signal readout circuit according to claim 1, wherein the averaging means includes low-pass filtering means for low-pass filtering the serial signal. A first signal including a plurality of pixel periods and each of the plurality of pixel periods including a feedthrough period and a signal period is received from a charge coupled device (CCD), and correlation noise and high frequency noise included in the signal period are received. In a CCD signal readout circuit for outputting a reduced second signal, the circuit includes at least:
Receiving the first signal, in each of the plurality of pixel period, the level between the feed-through phase, the first signal and the first gate pulse is input, in response to a constant voltage to the first gate pulse Instead, the signal is extracted by a first gate circuit that outputs a signal of the feedthrough period, and the level of the signal period is input by the first signal and the second gate pulse, and is responsive to the second gate pulse. A signal extracting means for extracting a signal of the signal period instead of a constant voltage by a second gate circuit to be a feedthrough signal and a pixel signal, respectively;
A signal inversion means for inverting one of the feedthrough signal and the pixel signal and outputting it as a serial signal;
The serial signal is selected for the first pixel period of the plurality of pixel periods to be the first serial signal, and is selected for the second pixel period that is different from the first pixel period. Selection means to
First averaging means for averaging a first serial signal and thereby outputting a signal in which the correlated noise and high-frequency noise are reduced;
Second averaging means for averaging a second serial signal and thereby outputting a signal with reduced correlated noise and high frequency noise ;
The CCD signal readout circuit , wherein the first and second gate pulses are synchronized with the extracted feedthrough period and signal period, respectively, and have the same pulse width . A first signal including a plurality of pixel periods and each of the plurality of pixel periods including a feedthrough period and a signal period is received from a charge coupled device (CCD), and correlation noise and high frequency noise included in the signal period are received. In a CCD signal readout circuit for outputting a reduced second signal, the circuit includes at least:
Receiving the first signal, the first pixel period of the plurality of pixel period, the level between the feed-through phase, the first signal and the first gate pulse is inputted, the first gate pulse The signal is extracted by a first gate circuit that outputs a signal of the feedthrough period instead of a constant voltage, and the level of the signal period is input by the first signal and the second gate pulse. In response to the gate pulse, the second gate circuit that outputs the signal in the signal period instead of the constant voltage extracts the first signal as the first feedthrough signal and the first pixel signal, respectively. Means,
Receiving the first signals, the second pixel period different from the first pixel period of the plurality of pixel period, the level between the feed-through phase, the first signal and the third gate pulse is inputted In response to the third gate pulse, the signal is extracted by a third gate circuit that outputs the signal of the feedthrough period instead of the constant voltage, and the level of the signal period is determined by the first signal and the fourth gate pulse. Is extracted by a fourth gate circuit that outputs a signal in the signal period instead of a constant voltage in response to a fourth gate pulse, and a second feedthrough signal and a second pixel signal, respectively, Second signal extraction means for
First signal inverting means for inverting one of the first feedthrough signal and the first pixel signal and outputting the inverted signal as a first serial signal;
Second signal inverting means for inverting one of the second feedthrough signal and the second pixel signal and outputting the inverted signal as a second serial signal;
First averaging means for averaging a first serial signal and thereby outputting a signal in which the correlated noise and high-frequency noise are reduced;
A second serial signal averaged, thereby viewing including a second averaging means for outputting a signal noise and high noise reduced to the correlation,
The first and second gate pulses are synchronized with the extracted feedthrough period and the signal period, respectively, and have the same pulse width, and the third and fourth gate pulses are the extracted feedthrough period. A CCD signal readout circuit, characterized by being synchronized with a period and a signal period, and having the same pulse width . 7. The CCD signal readout circuit according to claim 5 or 6, further comprising at least:
First sampling means for sampling the signal output from the first averaging means at the timing of the first pixel period;
Second sampling means for sampling the signal output from the second averaging means at the timing of the second pixel period;
A CCD signal read circuit comprising: hold signal holding means for holding signals sampled by the first and second sampling means and serially outputting the signals as second signals.   8. The CCD signal readout circuit according to claim 5, wherein the first signal is a color image signal, and the first pixel period is a pixel period of a first color among colors of the color image signal. The CCD signal readout circuit is characterized in that the second pixel period is a pixel period of the second color among the colors of the color image signal.

Images