JPH0883906A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0883906A
JPH0883906A JP21896794A JP21896794A JPH0883906A JP H0883906 A JPH0883906 A JP H0883906A JP 21896794 A JP21896794 A JP 21896794A JP 21896794 A JP21896794 A JP 21896794A JP H0883906 A JPH0883906 A JP H0883906A
Authority
JP
Japan
Prior art keywords
igbt
voltage
source
gate
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21896794A
Other languages
Japanese (ja)
Inventor
Yoshihiro Yamaguchi
好広 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21896794A priority Critical patent/JPH0883906A/en
Publication of JPH0883906A publication Critical patent/JPH0883906A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: To prevent generation of latch-up even if gate voltage is heightened to drive IGBT by almost equalizing voltage to be impressed between a gate and a source of IGBT to a difference between gate voltage of IGBT to be impressed from outside and voltage between the in and output terminals of a nonlinear element. CONSTITUTION: High voltage is impressed on a gate 1 of IGBT so as to perform low loss drive. Further, MOSFET 2 as nonlinear elements are in series connected to a source of IGBT 1 so as to make the same current flow. When an overcurrent flow to IGBT 1, voltage between a drain and a source of MOSFET 2 increases suddenly. At this time, voltage between a drain and a source of IGBT 1 becomes that where voltage between a drain and a source of MOSFET 2 is substructed from gate voltage of IGBT 1. Accordingly, even if the overcurrent flows to IGBT 1, voltage between the gate and the source of IGBT 1 automatically lowers so as to prevent generation of latch-up.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、IGBTの過電流保護
を行なう半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for protecting an IGBT from overcurrent.

【0002】[0002]

【従来の技術】絶縁ゲート型の高耐圧半導素子の一つと
して、IGBT(Insulated Gate Bipolar Transistor
)がある。IGBTは、パワーMOSFETの高速ス
イッチング特性とバイポーラトランジスタの高出力特性
とを兼ね備えた新しい高耐圧半導体素子であり、近年、
インバータやスイッチング電源等のパワーエレクトロニ
クスの分野で多く利用されている。
2. Description of the Related Art An IGBT (Insulated Gate Bipolar Transistor) is one of the insulated gate high withstand voltage semiconductor elements.
). The IGBT is a new high breakdown voltage semiconductor device having both the high speed switching characteristics of a power MOSFET and the high output characteristics of a bipolar transistor.
It is widely used in the field of power electronics such as inverters and switching power supplies.

【0003】ところで、IGBTのドレイン・ソース間
電圧とドレイン・ソース間電流との間の特性(V−I特
性)は、ゲート電圧に大きく左右され、ゲート電圧が高
くなるとオン電圧は低くなる。このため、ゲート電圧を
高くしてIGBTを駆動とすると、低損失の駆動が可能
となる。
By the way, the characteristic (VI characteristic) between the drain-source voltage and the drain-source current of the IGBT is greatly influenced by the gate voltage, and the on-voltage decreases as the gate voltage increases. Therefore, when the IGBT is driven by increasing the gate voltage, low loss driving becomes possible.

【0004】しかし、この場合、IGBTの飽和電流が
高くなり、ラッチアップ電流を越える大きな電流(過電
流)が流れる。したがって、ゲート電圧を高くしてIG
BTを駆動すると、IGBTに過電流が流れた場合に、
IGBTがラッチアップし、最悪の場合にはIGBTが
破壊されるという問題が生じる。
However, in this case, the saturation current of the IGBT becomes high, and a large current (overcurrent) exceeding the latch-up current flows. Therefore, increase the gate voltage to increase the IG
When an overcurrent flows through the IGBT when the BT is driven,
There is a problem that the IGBT latches up and, in the worst case, the IGBT is destroyed.

【0005】[0005]

【発明が解決しようとする課題】上述の如く、ゲート電
圧を高くしてIGBTを低損失で駆動すると、IGBT
に過電流が流れた場合に、IGBTがラッチアップする
という問題があった。本発明は、上記事情を考慮してな
されたもので、その目的とするところは、ゲート電圧を
高くしてIGBTを駆動しても、ラッチアップの発生を
効果的に防止できるIGBTを備えた半導体装置を提供
することにある。
As described above, when the gate voltage is increased and the IGBT is driven with low loss, the IGBT is
There is a problem that the IGBT latches up when an overcurrent flows through the IGBT. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor provided with an IGBT that can effectively prevent latch-up even if the IGBT is driven by increasing the gate voltage. To provide a device.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、IGBTと、このIGB
Tのソースに入力端が接続されて前記IGBTに直列接
続された非線形素子とを備え、前記非線形素子が、入出
力端間に流れる電流の増加に伴って、入出力端間の電圧
が非線形に増加する素子であり、前記IGBTのゲート
・ソース間に印加される電圧が、外部より印加される前
記IGBTのゲート電圧と、前記非線形素子の入出力端
間の電圧との差に略等しくなるようにしたことを特徴と
する。
In order to achieve the above object, a semiconductor device of the present invention comprises an IGBT and an IGBT.
A non-linear element having an input terminal connected to the source of T and serially connected to the IGBT, wherein the non-linear element causes the voltage between the input and output terminals to become non-linear as the current flowing between the input and output terminals increases. It is an increasing element, and the voltage applied between the gate and the source of the IGBT is substantially equal to the difference between the gate voltage of the IGBT applied from the outside and the voltage between the input and output ends of the nonlinear element. It is characterized by having done.

【0007】[0007]

【作用】本発明によれば、IGBTに非線形素子が直列
に接続されているので、IGBTおよび非線形素子には
同じ電流が流れ、そして、このときのIGBTのゲート
・ソース間電圧は、IGBTのゲート電圧から非線形素
子の入出力端間の電圧を引いたものとなる。
According to the present invention, since the non-linear element is connected in series to the IGBT, the same current flows through the IGBT and the non-linear element, and the gate-source voltage of the IGBT at this time is the gate of the IGBT. It is the voltage minus the voltage between the input and output ends of the nonlinear element.

【0008】したがって、過電流が流れても、ゲート・
ソース間電圧は、非線形素子の入出力端間の電圧分だけ
小さくなるので、IGBTのラッチアップの発生は防止
される。
Therefore, even if an overcurrent flows, the gate
Since the source-to-source voltage is reduced by the voltage between the input and output ends of the non-linear element, the latch-up of the IGBT is prevented.

【0009】ここで、非線形素子として、過電流が流れ
ると、入出力端間の電圧が、急激に増加する特性を有す
るものを用いれば、IGBTのラッチアップの発生を効
果的に防止できる。
Here, if a non-linear element having a characteristic in which the voltage between the input and output ends sharply increases when an overcurrent flows, the occurrence of latch-up of the IGBT can be effectively prevented.

【0010】[0010]

【実施例】以下、図面を参照しながら実施例を説明す
る。図1は、本発明の第1の実施例に係る半導体装置を
示す図である。この半導体装置はIGBTを過電流から
保護するものである。
Embodiments will be described below with reference to the drawings. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. This semiconductor device protects the IGBT from overcurrent.

【0011】図中、1はIGBTを示しており、このI
GBTのゲートには高い電圧(例えば、20V)が印加
され、低損失の駆動が行なわれるようになっている。ま
た、IGBT1のソースには非線形素子としてのMOS
FET2が接続されており、IGBT1に対してMOS
FET2は直列に接続され、IGBT1とMOSFET
2とには同じ電流が流れるようになっている。
In the figure, reference numeral 1 denotes an IGBT.
A high voltage (for example, 20 V) is applied to the gate of the GBT to drive it with low loss. Further, the source of the IGBT 1 has a MOS as a non-linear element.
FET2 is connected, and MOS is connected to IGBT1.
FET2 is connected in series, IGBT1 and MOSFET
The same current as 2 flows.

【0012】また、MOSFET2のゲートには電源5
が設けられ、後述するように、ゲートには所定のゲート
電圧が印加されている。なお、MOSFET2は低耐圧
のものでも良い。なお、図中、3は電源、4は負荷を示
している。
A power supply 5 is connected to the gate of the MOSFET 2.
Is provided, and a predetermined gate voltage is applied to the gate, as described later. The MOSFET 2 may have a low breakdown voltage. In the figure, 3 indicates a power source and 4 indicates a load.

【0013】図2は、MOSFET2のドレイン・ソー
ス間電流IDSとドレイン・ソース間電圧VDSとの関係を
示す特性図である。図2から分かるように、ドレイン・
ソース間電流IDSの増加に伴って、ドレイン・ソース間
電圧VDSは非線形に増加する。すなわち、ドレイン・ソ
ース間電流IDSがある一定値(飽和電流)を越えると、
ドレイン・ソース間電圧VDSは急激に増加する。
FIG. 2 is a characteristic diagram showing the relationship between the drain-source current I DS and the drain-source voltage V DS of the MOSFET 2. As can be seen from FIG.
The drain-source voltage V DS increases non-linearly as the source current I DS increases. That is, when the drain-source current IDS exceeds a certain value (saturation current),
The drain-source voltage V DS rapidly increases.

【0014】この飽和電流は、MOSFET2のゲート
に印加される電圧(ゲート電圧)によって異なる。本実
施例では、飽和電流がIGBTの過電流となるように、
電源5によりゲート電圧(所定のゲート電圧)を設定し
ている。例えば、過電流が10Aであれば、飽和電流が
10Aとなるように、ゲート電圧を設定する。
This saturation current depends on the voltage (gate voltage) applied to the gate of the MOSFET 2. In this embodiment, the saturation current is an overcurrent of the IGBT,
A gate voltage (predetermined gate voltage) is set by the power supply 5. For example, if the overcurrent is 10 A, the gate voltage is set so that the saturation current is 10 A.

【0015】このように構成された半導体装置によれ
ば、IGBT1に過電流が流れると、MOSFET2の
ドレイン・ソース間電圧VDSが急激に増加する。このと
き、IGBT1とMOSFET2とが直列に接続されて
いるので、IGBT1のゲート・ソース間電圧は、IG
BT1のゲート電圧からMOSFET2のドレイン・ソ
ース間電圧VDSを引いたものとなる。
According to the semiconductor device having such a structure, when an overcurrent flows in the IGBT 1, the drain-source voltage V DS of the MOSFET 2 rapidly increases. At this time, since the IGBT1 and the MOSFET2 are connected in series, the gate-source voltage of the IGBT1 is IG
It is the gate voltage of BT1 minus the drain-source voltage V DS of MOSFET2.

【0016】したがって、IGBT1に過電流が流れて
も、IGBT1のゲート・ソース間の電圧が自動的に低
下し、IGBTの飽和電流が低くなるため、ラッチアッ
プの発生を防止できる。
Therefore, even if an overcurrent flows through the IGBT1, the voltage between the gate and the source of the IGBT1 automatically decreases and the saturation current of the IGBT decreases, so that latch-up can be prevented.

【0017】また、上記動作原理により、過電流が流れ
た場合、IGBTの飽和電流が小さくなるため、電源電
圧のほとんどは負荷とIGBTに分担され、非線形素子
のMOSFETに過電圧が印加されることはない。した
がって、非線形素子はIGBT1よりも耐圧の低い低耐
圧の素子で良い。
Further, according to the above operation principle, when an overcurrent flows, the saturation current of the IGBT becomes small, so that most of the power supply voltage is shared by the load and the IGBT, and the overvoltage is not applied to the MOSFET of the nonlinear element. Absent. Therefore, the non-linear element may be a low breakdown voltage element having a lower breakdown voltage than the IGBT 1.

【0018】図3は、本発明の第2の実施例に係る半導
体装置を示す図である。なお、図1の半導体装置と対応
する部分には図1と同一符号を付してあり、詳細な説明
は省略する。
FIG. 3 is a diagram showing a semiconductor device according to the second embodiment of the present invention. The parts corresponding to those of the semiconductor device of FIG. 1 are designated by the same reference numerals as those of FIG. 1, and detailed description thereof is omitted.

【0019】本実施例の半導体装置が先の実施例のそれ
と異なる点は、非線形素子として、バイポーラトランジ
スタ6を用いたことにある。本実施例によれば、コレク
タ・エミッタ間電流の飽和電流がIGBT2の過電流と
なるように、バイポーラトランジスタ6のベース電流を
設定することにより、先の実施例と同様な効果が得られ
る。
The semiconductor device of this embodiment is different from that of the previous embodiment in that a bipolar transistor 6 is used as a non-linear element. According to the present embodiment, by setting the base current of the bipolar transistor 6 so that the saturation current of the collector-emitter current becomes the overcurrent of the IGBT 2, the same effect as the previous embodiment can be obtained.

【0020】図4は、本発明の第3の実施例に係る半導
体装置(電圧形3相インバータ)を示す図である。本実
施例の電圧形3相インバータの特徴は、主スイッチング
素子としてIGBT1を用い、下段の3個のIGBTに
対し、一つの非線形素子を接続したことにある。なお、
図中、7はIGBT1と逆並列に接続された帰還ダイオ
ードを示している。
FIG. 4 is a diagram showing a semiconductor device (voltage type three-phase inverter) according to a third embodiment of the present invention. The voltage-type three-phase inverter of this embodiment is characterized in that the IGBT 1 is used as a main switching element and one nonlinear element is connected to the three IGBTs in the lower stage. In addition,
In the figure, 7 indicates a feedback diode connected in anti-parallel with the IGBT 1.

【0021】なお、本実施例では、非線形素子として、
MOSFETを用いたが、第2の実施例と同様に、バイ
ポーラトランジスタを用いても良い。また、全てのIG
BTに本発明を適用しても良い。上記第1〜第3の実施
例において、IGBTと非線形素子とは別基板に形成し
ても良いし、同一基板に形成して集積化しても良い。
In this embodiment, as the non-linear element,
Although the MOSFET is used, a bipolar transistor may be used as in the second embodiment. Also, all IG
The present invention may be applied to BT. In the first to third embodiments, the IGBT and the non-linear element may be formed on different substrates, or may be formed on the same substrate and integrated.

【0022】[0022]

【発明の効果】以上詳述したように本発明によれば、ゲ
ート電圧を高くしてIGBTを駆動しても、ラッチアッ
プの発生を効果的に防止できる半導体装置を実現できる
ようになる。
As described above in detail, according to the present invention, it is possible to realize a semiconductor device capable of effectively preventing the occurrence of latch-up even when the IGBT is driven by increasing the gate voltage.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例に係る半導体装置を示す
FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

【図2】MOSFET(非線形素子)のドレイン・ソー
ス間電流とドレイン・ソース間電圧との関係を示す特性
FIG. 2 is a characteristic diagram showing the relationship between the drain-source current and the drain-source voltage of a MOSFET (non-linear element).

【図3】本発明の第2の実施例に係る半導体装置を示す
FIG. 3 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

【図4】本発明の第3の実施例に係る半導体装置を示す
FIG. 4 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…IGBT 2…MOSFET(非線形素子) 3…電源 4…負荷 5…電源 6…バイポーラトランジスタ(非線形素子) 7…帰還ダイオード 1 ... IGBT 2 ... MOSFET (non-linear element) 3 ... Power source 4 ... Load 5 ... Power source 6 ... Bipolar transistor (non-linear element) 7 ... Feedback diode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】IGBTと、このIGBTのソースに入力
端が接続されて前記IGBTに直列接続された非線形素
子とを具備し、前記非線形素子は、入出力端間に流れる
電流の増加に伴って、入出力端間の電圧が非線形に増加
する素子であり、前記IGBTのゲート・ソース間に印
加される電圧が、外部より印加される前記IGBTのゲ
ート電圧と、前記非線形素子の入出力端間の電圧との差
に略等しくなるようにしたことを特徴とする半導体装
置。
1. An IGBT and a nonlinear element having an input end connected to a source of the IGBT and connected in series to the IGBT, wherein the nonlinear element increases with an increase in current flowing between input and output ends. An element in which the voltage between the input and output ends increases non-linearly, and the voltage applied between the gate and source of the IGBT is between the gate voltage of the IGBT applied from the outside and the input and output end of the non-linear element. The semiconductor device is characterized in that the difference between the voltage and the voltage is substantially equal.
【請求項2】前記非線形素子は、IGBTよりも耐圧の
低い素子であることを特徴とする請求項1に記載の半導
体装置。
2. The semiconductor device according to claim 1, wherein the non-linear element is an element having a lower breakdown voltage than an IGBT.
JP21896794A 1994-09-13 1994-09-13 Semiconductor device Pending JPH0883906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21896794A JPH0883906A (en) 1994-09-13 1994-09-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21896794A JPH0883906A (en) 1994-09-13 1994-09-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0883906A true JPH0883906A (en) 1996-03-26

Family

ID=16728167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21896794A Pending JPH0883906A (en) 1994-09-13 1994-09-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0883906A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108111004A (en) * 2017-12-29 2018-06-01 电子科技大学 A kind of hybrid device for realizing Si IGBT Sofe Switch characteristics

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108111004A (en) * 2017-12-29 2018-06-01 电子科技大学 A kind of hybrid device for realizing Si IGBT Sofe Switch characteristics
CN108111004B (en) * 2017-12-29 2019-10-29 电子科技大学 A kind of hybrid device for realizing Si IGBT Sofe Switch characteristic

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