JPH0883904A - Field effect transistor - Google Patents

Abstract

PURPOSE: To prevent a leakage current from flowing into a buffer layer by deciding In composition of the buffer layer to perform lattice matching with a substrate besides by making electronic affinity in the part coming in contact with the the substrate equal to that of the substrate and changing so as to gradually minimize an Al composition in the part coming in contact with a channel layer. CONSTITUTION: An InGaAlAs buffer layer 302, where a composition ratio of Ga and Al is gradually changed so that electronic affinity may be equal to InP in the interface with an InP substrate 301 and a band gap may be sufficiently wider than InGaAs in the interface with an InGaAs channel layer 303, is laminated on the InP substrate 301. Accordingly, the triangle well potential is not formed so that electrodes are hard to build up in the interface between the buffer layer 302 and the substrate 301. Thereby, a leakage current stops to flow to the interface between the buffer layer 302 and the substrate 301 so as to heighten an effect of carrier confinement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to an InP / InGaAs / InAlAs system field effect transistor.

[0002]

2. Description of the Related Art In a field effect transistor (FET),
A buffer layer is formed between the substrate and the channel layer in order to prevent a decrease in electron mobility in the channel layer due to defects on the surface of the semiconductor substrate. It is known to use a semiconductor having the same composition as that of the substrate for the buffer layer, but it is expected that a semiconductor having a smaller electron affinity than the semiconductor of the substrate is used for the buffer layer to confine carriers inside the channel layer.

The mobility of electrons in a field effect transistor is
It is determined by the mobility of electrons in the channel layer and the mobility of electrons flowing in the substrate side, but if the effect of confining carriers inside the channel layer is increased, the current component with low mobility flowing in the substrate side in the ON state is reduced. Therefore, the mobility of the entire device can be increased.

Further, when the buffer layer is grown by the MOCVD method suitable for mass production, it is difficult to sufficiently suppress the residual carrier concentration, and there is a problem that a leak current flows in this portion. In order to solve this, it is conventionally known that Fe that forms a deep acceptor level is doped into the buffer layer to trap residual carriers in this level and increase the resistance of the buffer layer.

[0005]

The present inventors expect a carrier confinement effect and further develop a MOC suitable for mass production in order to develop an FET having no leak current in the buffer layer.
The FET shown below was made by using the VD method.

(1) I, which has a smaller electron affinity than InP on the InP substrate, expecting a carrier confinement effect.
nAlAs was used as a buffer layer. (2) Fe was doped to increase the resistance of the buffer layer.

In this way, InP substrate / Fe-doped In
An FET having an AlAs buffer layer / InGaAs channel layer structure was prepared and the mobility of the device was measured. However, the residual carrier concentration in the buffer layer has a resistivity of 1
This time, we newly found the problem that a leak current flows in the buffer layer despite the decrease to E6 Ωcm.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a novel FET which prevents the above-mentioned leak current, has a sufficiently high carrier confinement effect, and has no leak current.

[0009]

In order to achieve the above object, a field effect transistor according to the present invention is a semiconductor substrate mainly containing InP and In formed on the semiconductor substrate.
and _{x (Ga y Al 1-y} ) buffer layer comprising mainly _1-x As, an InGaAs formed on the buffer layer a field effect transistor having a channel layer mainly, the buffer layer , The In composition x is determined so as to be lattice-matched with the substrate, the electron affinity at the portion in contact with the substrate is equal to the electron affinity at the substrate, and the band gap at the portion in contact with the channel layer is sufficiently larger than that at the channel layer. A field-effect transistor including a layer in which the Al composition y is changed so as to gradually become smaller.

[0010]

The operation of the present invention will be described below with reference to the drawings.
FIG. 1 is a band diagram of a FET in which an InAlAs buffer layer 103 having an electron affinity smaller than that of InP is laminated on an InP substrate 104 initially created by the present inventors. 1 in the figure
01 is an InAlAs electron supply layer, 102 is InGaAs
It is the channel layer.

In such a structure, the InAlAs buffer layer 103 and the InP substrate 104 have an electron affinity of 10
Since 5 and 106 are different, a triangular well potential 107 is formed between them. According to the research of the inventors,
In the InP / InAlAs system, it has been clarified that electrons are accumulated in the triangular well type potential 107 to cause a leak current.

Therefore, the present invention is based on the InAlAs buffer layer.
By making the electron affinity of the group III composition in contact with the InP substrate equal to that of InP, the triangular well potential 107 is eliminated, and InGaAs
The buffer layer is formed by mixing Ga as a group III composition and changing the composition ratio of Ga to Al so as to become gradually smaller toward the channel layer so that a band gap that is sufficiently wider than that of InGaAs is formed in a portion in contact with the channel layer. Formed.

FIG. 2 shows a band diagram of an FET provided with a buffer layer in which the composition ratio of Ga and Al is changed. I
On the nP substrate 204, the composition ratio of Ga and Al was gradually changed so that the electron affinity at the interface with the InP substrate 204 was equal to that of InP and the band gap at the interface with the InGaAs channel layer was sufficiently wider than that of InGaAs. The InGaAlAs buffer layer 203 is laminated.
In the figure, 201 is an InAlAs electron supply layer, and 202 is InG.
It is an aAs channel layer.

As shown, the buffer layer 203 and the substrate 204
Since the electron affinities at the interfaces are the same, the triangular well type potential is not formed. Therefore, since a portion having a low potential is not formed, electrons are less likely to accumulate at the interface between the buffer layer and the substrate. Due to the above actions, the leak current does not flow at the interface between the buffer layer and the substrate.

[0015]

EXAMPLES As an example of the field effect transistor according to the present invention, the buffer layer is made of In _x (Ga _y Al).
HEMT formed of _1-y ) _1-x As layer is shown as an example. This example is provided to facilitate understanding of the present invention, and is not intended to limit the present invention.

FIG. 3 shows a HEMT according to an embodiment of the present invention.
FIG. By the MOCVD method, semi-insulating In
Fe concentration of 5 as the buffer layer 302 on the P substrate 301
E 16 cm ^-3 Fe-doped In _0.5 (Ga _y Al _1-y )
_{A 0.5} As layer is laminated in a thickness of 300 nm while gradually changing the value of y from 0.7 to 0. The value of y can be changed by controlling the supply of trimethylaluminum (TMA) and trimethylgallium (TMG), which are raw materials, with a mass flow controller.

The Fe concentration is equal to or higher than the residual carrier concentration of InGaAlAs (typically about 1E15 cm ^-3 ).
It is preferable that the concentration is not more than the individual dissolution limit concentration (about 1E17 cm ⁻³ ).

Next, non-doped I is formed on the buffer layer 302.
An nGaAs channel layer 303 is grown to a thickness of 20 nm, a non-doped InAlAs spacer layer 304 is grown to a thickness of 3 nm, a donor concentration of 3E18 cm ⁻³ n-type InAlAs electron supply layer 305 is grown to a thickness of 20 nm, and a non-doped InAlAs Schottky contact layer 306 is grown to a lattice match in order of 20 nm.

Next, an n-type InGaAs layer serving as an ohmic contact layer having a donor concentration of 5E18 cm ^-3 is formed to a thickness of 20 nm.
After the growth is performed so as to be lattice-matched, the portion forming the gate electrode is removed by etching to form the n-type InGaAs ohmic contact layer 307.

Next, a gate electrode 308 is formed by vapor deposition of AuGe alloy on the Schottky contact layer 306,
A source electrode 309 and a drain electrode 310 are formed by vapor deposition of Pt on the ohmic contact layer 307.

The above growth was performed at a substrate temperature of 650 ° C. and a reaction tube pressure of 70 torr. Group III raw materials such as trimethylindium, trimethylaluminum (TMA),
Trimethylgermanium (TMG) was used, and phosphine and arsine were used as group V raw materials. Further, disilane was used as the n-type dopant and ferrocene was used as the Fe dopant.

In the present embodiment, since the buffer layer was doped with Fe, electrons as residual impurities were trapped in the deep acceptor level formed by Fe, and the residual carrier concentration was very low.

When the characteristics of the HEMT prepared as described above were examined, no leak current flowed in the buffer layer.
It was found that the breakdown voltage of the buffer layer was 5 V or more. It is speculated that this is because the buffer layer 302 has the same electron affinity as the substrate at the interface of the substrate 301, and thus there is no triangular well potential at the interface between the two.

As a comparative example, a HEMT having an InAlAs buffer layer in place of the buffer layer of this example was prepared and the mobilities were compared. Dual electron gas concentration 2.7E
The mobility at room temperature at 12 cm ⁻² is 7.5 in the comparative example.
E3 cmv ⁻¹ s ⁻¹ , whereas H according to the present embodiment
In EMT, it was found to be significantly improved to 1.0E4 cmv ^-1 s ^-1 .

[0025]

According to the present invention, an FET having a high carrier confinement effect and no leak current in the buffer layer can be provided.

[Brief description of drawings]

FIG. 1 is a band diagram of a HEMT with an InAlAs buffer layer.

FIG. 2 is a band diagram of a HEMT including a buffer layer according to the present invention.

FIG. 3 is a sectional view of an FET according to an embodiment of the present invention.

[Explanation of symbols]

 301 InP substrate 302 Buffer layer 303 Channel layer 304 Spacer layer 305 Electron supply layer 306 Schottky contact layer 307 Ohmic contact layer 308 Gate electrode 309 Source electrode 310 Drain electrode

Claims (1)

[Claims] 1. A semiconductor substrate mainly containing InP and In _x (Ga _y Al) formed on the semiconductor substrate.
_1-y ) A field effect transistor having a buffer layer mainly composed of _1-x As and a channel layer mainly composed of InGaAs formed on the buffer layer, wherein the buffer layer is composed of the substrate and a lattice. In to match
Al composition y is determined so that the composition x is determined and the electron affinity at the portion in contact with the substrate is equal to the electron affinity at the substrate and the band gap is sufficiently wider at the portion in contact with the channel layer than the channel layer. A field effect transistor comprising a layer that is gradually reduced.