JPH0879711A - Time base correction circuit - Google Patents

Abstract

PURPOSE: To provide a time base fluctuation correction circuit with less memory capacity for suppressing a product cost and eliminating defects such as the vertical movement of a TV screen due to memory address passing over or the like. CONSTITUTION: A synchronizing separator circuit 2 and a PLL circuit 3 use reference signals (synchronizing signals) in input video signals and prepare data write sequence signals to a memory. A reference frequency oscillator 5 and a frequency divider circuit 6 prepare memory read sequence signals and read cycle signals. A frequency comparator 8 counts the data write sequence signals in the period of the memory read cycle signals, compares the counted value with a prescribed comparison value and detects whether or not a memory address passing state is caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction circuit (hereinafter TBC circuit) for correcting a time axis fluctuation generated in a reproduction signal of a video signal processing device such as a video tape recorder (VTR) or a laser disk (LD) device. Regarding

[0002]

2. Description of the Related Art FIG. 22 shows a conventional TBC circuit.
Although the TBC circuit has various circuit configurations depending on the variable delay line used, the figure shows a general circuit configuration and a TBC circuit using a memory is shown.

First, an input video signal 100 is converted into digital data by an analog / digital (A / D) converter 101. This input digital signal is subjected to writing / reading processing in the storage device 102, and in this process, time axis fluctuation (hereinafter referred to as jitter) existing in the input video signal is removed. The digital signal from which the jitter is removed is the D / A converter 1
Converted to an analog signal at 03, and output analog signal 11
It becomes 0. In order to remove the time axis fluctuation, the memory writing process is performed with a writing clock (hereinafter WCK) that substantially matches the time axis fluctuation in the input video signal, and the reading process is performed with a stable time axis reading clock (hereinafter RCK). )
Done in. For example, reading is performed with a stable frequency RCK generated using a crystal oscillator. In this way, the jitter removal is realized in the process of writing / reading the signal to / from the memory.

Next, generation of these write / read clocks will be described. To generate the write clock (WCK), a clock (CK) that is phase-synchronized with the reference signal in the input video signal is created. Generally, a horizontal synchronizing signal is used as a reference signal in a video signal. The horizontal synchronizing signal is separated and waveform-shaped from the input signal 100 in the sync separation circuit 104, and is obtained as the HD signal 105. P
The LL circuit 106 multiplies the frequency of the HD signal 105 with the separated HD signal 105 as a reference, and phase-locks the W signal.
Create CK. In the write sequence circuit 107,
From the WCK and the reference signal such as the HD signal, the above-mentioned storage device 102
A write reset signal (hereinafter referred to as WRST) which is a signal for write timing of is generated. Further, for reading, the oscillation circuit 10 using a stable oscillation element such as a crystal oscillator is used.
At 8, an RCK whose frequency is stable is created. Then, the read sequence circuit 109 performs processing such as frequency division based on RCK to create a read reset signal (hereinafter, RRST) which is a read timing signal of the storage device 102.

As the storage device 102, there is a FIFO memory or the like that can be used with an asynchronous clock. Since the FIFO memory is commercially available as a single item, there is no problem in obtaining it. FIG. 23 shows a circuit configuration example of the memory device 102.

This is a general structure of a FIFO memory. The input digital data is once stored in the input buffer 111, and the output data of the input buffer 111 is written in the memory cell array 112 at the timing of being created by the write sequence circuit described below. The data in the memory cell array 112 is read out via the output buffer 113. The write start timing is write reset (WRST) input from the outside of this storage device.
This is performed by initializing the address of the write address counter 114 with a signal. The write timing master CK is a write clock (WCK). Similarly, the read operation is performed by initializing the address of the read address counter 115 with a read reset (RRST) signal.
Further, writing / reading CK can be performed asynchronously, and circuit means is provided for avoiding simultaneous start when the writing / reading timings match in the address decoder circuit 116. The general configuration of the storage device has been described above.

Next, the circuit operation of the system of FIG. 22 will be described. FIG. 24 is a diagram for explaining the circuit operation centering on the storage device. The input data is an input video digital signal digitized by the A / D converter 101. This is an N-fold data string in N units, where horizontal synchronization, which is a reference signal, is one unit. The leading data of the 0th data string is written to the initial address of the memory cell at the WRST timing. Thereafter, the address is continuously changed and the 0th data string is sequentially written in the memory cells. For reading, the data of the memory initial address cell is read at the timing indicated by RRST,
The data is read out sequentially. The read data is sequentially read from the 0th data sequence to the 1st data sequence and the 2nd data sequence. In this case, the memory cell address can be managed by WRST and RRST without inputting from the outside. Although WRST and RRST are used in the following description, the same operation can be obtained in a system in which a memory address is specified externally and a memory cell is selected.

Generally, a TBC circuit is a VTR or LD.
This device is used in a recording / reproducing device having a mechanical system such as a (laser disk) device, etc., and is a device for removing the time-axis fluctuation of the reproduced signal of these devices. The memory capacity of the storage device is determined by the amount of jitter of the reproduction signal of the reproduction device used. When a video movie is used by hand and shake occurs, the amount of jitter is large. In addition, a lower jitter frequency requires a larger memory capacity for time axis correction. Therefore, generally, the TBC circuit is created using a memory capacity larger than the field memory. Field memory prices are still high today. Therefore high price VT
The TBC circuit is used only in video equipment such as R and LD devices.

On the other hand, a memory capacity of several lines is sufficient for the amount of jitter when recording and reproducing a broadcast signal or the like in a stationary manner. However, if the memory capacity is low,
When an input signal with a large amount of jitter, such as the video movie, is input, a problem of memory address overtaking occurs in writing / reading.

This will be described in two cases with reference to FIG. In FIG. 25A, the WRST frequency is RRST.
This is the case below the frequency. The input data is written in the memory at the WRST timing. The written data is read at the RRST timing. However,
A second RRST may come before the next WRST comes. In this case, the (N + 2) th data string is read twice. On the TV screen, the following image positions are lowered from that moment. In the case of FIG. 25 (b), W
When the RST frequency is higher than the RRST frequency, conversely, the (N + 2) th data string is completely deleted. At this time, the position of the lower image rises from that moment on the television (TV) screen. That is, when the memory address is overtaken, the screen position on the TV screen display moves up and down, resulting in an unstable screen display.

[0011]

As described above, the TBC circuit having a sufficient time axis correction capability requires a memory having a larger capacity than the field memory, and has a drawback of increasing the product price. Also, if the amount of input jitter is large if the memory capacity is reduced to keep the price down,
There was an adverse effect that the memory address overtaking occurred and the screen position on the TV screen moved up and down.

Therefore, according to the present invention, the product price can be suppressed with a small memory capacity, and the T can be achieved by overtaking the memory address.
An object of the present invention is to provide a time axis fluctuation correction circuit that can eliminate the adverse effects of vertical movement of the V screen.

[0013]

SUMMARY OF THE INVENTION According to the present invention, a memory write sequence signal created by using a synchronizing signal in an input video signal is counted in a memory read cycle period, and the count value and a comparison value are compared with each other. It has frequency detection means for detecting whether an address overtaking condition has occurred.
Further, means for creating a memory write sequence signal and a memory read sequence signal created by using the synchronization signal in the input video signal, and means for counting the number of memory write sequence signals during the memory read period,
Frequency comparison means is provided for detecting whether or not a memory address overtaking state has occurred by comparing the count result with a comparison value. The counting means has means for stopping detection of the VTR head switching period.

Further, the present invention has means for shifting the phase of the memory write timing signal generated from the synchronization signal in the input video signal when the memory address overtaking is detected. Further, it has means for shifting the phase of the memory read timing signal generated from the independent reference signal oscillator when the memory address overtaking is detected. Furthermore, the present invention has frequency detecting means including a circuit for extending the memory address overtaking detection result by a predetermined time. It also has means for switching between the TBC operation mode and the through mode according to the memory address overtaking detection signal.

The present invention also has means for performing the mode switching during the V blanking period. It also has means for switching between the TBC operation mode and the fixed delay mode in response to the memory address overtaking detection signal. Further, there is provided means for switching from the fixed delay mode to the TBC operation mode by detecting the phase difference between the reference signal in the input video signal and the memory read timing signal, and when the phase difference substantially matches.

[0016]

The memory address overtaking can be determined by detecting the frequency difference between the memory write timing signal and the memory read timing signal which are phase-synchronized with the reference signal in the input video signal. Further, by performing various signal processing based on this determination result, it is possible to eliminate the adverse effect of vertical movement on the TV screen due to memory address overtaking, which is described in the problem, so that there is no practical problem.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is intended to achieve the object in the TBC circuit by obtaining a high-performance memory address overtaking detection means in order to prevent the memory address overtaking phenomenon.

(Memory Address Overtaking Detection Means 1) FIG. 1 shows a first embodiment of the memory address overtaking detection circuit. The input video signal 1 is input to the sync separation circuit 2. The sync separation circuit 2 separates the horizontal sync signal. This horizontal synchronizing signal is input to the PLL circuit 3. The PLL circuit 3 is phase-synchronized with the horizontal synchronizing signal and obtains a signal 4 having a frequency M times the horizontal frequency. On the other hand, the reference frequency oscillator 5 obtains a stable oscillation frequency. As the reference frequency oscillator 5, a crystal oscillator or the like is used. This stable frequency signal is divided by N by the frequency divider 6 and becomes the reference frequency of the frequency comparator 8.
The frequency comparator 8 frequency compares the output of the frequency divider 6 and the output of the PLL circuit 3. The comparison result 9 obtained from the frequency comparator 8 is the memory address overtaking detection result.

Next, a configuration example of the frequency comparator 8 will be described with reference to FIG. Further, FIG. 3 shows a signal waveform diagram of each part.
The alphabet in FIG. 2 corresponds to the alphabet in FIG. Input A is signal 4 in FIG. This input A
Is used as the CK of the counter 10. Signal 7 in FIG.
Is the signal B in FIG. A signal C is a signal obtained by differentiating the signal B by the differentiating circuit 11 and delaying it by the delay element 12. The signal C clears the counter 10. The output D of the counter 10 is latched by the latch circuit 13, and the comparator 14,
15. A window comparator composed of an AND circuit 16 compares with a reference value (high) (low) to obtain an output H within a predetermined condition range. The window comparator is comparator 1.
At 4, the comparison calculation is performed with the high level reference value. The comparator 15 performs a comparison calculation with a low level reference value. The AND circuit 16 logically ANDs the outputs of both comparators to obtain an output result. When the output of the AND circuit 16 changes to the low level, that is, when E is larger than the high reference value,
If it is smaller than the low reference value, it can be determined that the memory address is overtaken.

The signal waveform of each node is as shown in FIG. The above circuit operation is summarized. The signal 7 in FIG. 1 is changed to a periodic signal (RRST) corresponding to the memory capacity length,
When the signal 4 of is set to WCK, the number of write data in one memory read cycle can be measured. Therefore, the horizontal synchronizing frequency of the input video signal is being measured. If the number of measurements is larger than the high reference value or smaller than the low reference value, it can be determined that the memory is overtaken.

(Memory Address Overtaking Detection Unit 2) FIG. 4 shows a second embodiment of the memory overtaking detection circuit.
In the figure, the same numbers as those in FIG. 1 are the same circuit blocks, and a description thereof will be omitted. The separated horizontal synchronizing signal is input to the 1 × PLL circuit 20. The PLL circuit 20 creates a write reference signal that is phase-synchronized with the horizontal synchronizing signal. This write reference signal is divided by the N dividing circuit 21.
The cycle of the divided signal 22 may be the WRST cycle. The frequency of this signal 22 is compared with that of the reference signal 7 by the frequency comparator 23, and the comparison result 24 is obtained.

Assuming that the cycle of the reference signal 7 matches the cycle of RRST, the frequency comparator 23 has the configuration shown in FIG. In FIG. 5, the circuit blocks having the same numbers as those in FIG. 2 have the same functions and will not be described. Compared to the configuration of FIG.
No wind comparator is needed. The output of the latch circuit 13 is input to the comparator 30 and compared with "1". In the case of this detection circuit, if the count value is other than 1, it is detected that memory address overtaking has occurred. This detection circuit is based on the RRST cycle.
The ST cycle is being measured. The state in which one WRST timing is included in the RRST cycle is the normal state. In addition, 0, 2, 3 and more are in the memory address overtaking state. The equal comparator 30 compares the outputs of the counter 10 and detects other than 1.

Further, the frequency comparator 23 can be simplified as shown in FIG. 6 (a). In FIG. 6A, the D-type flip-flop circuit D1 corresponds to the counter 10, and the flip-flop circuit D2 corresponds to the latch circuit 13. The operation is shown in FIG. Input A is WRST
It is a periodic signal. This signal is flip-flop circuit D
Divide by 2 at 1. The output of the flip-flop circuit D1 is latched by the flip-flop circuit D2 at the RRST timing. After the latch, the flip-flop circuit D1 is cleared. The Q output of the flip-flop circuit D2 that obtains the detection output becomes L level at the next RRST timing when two CK input rising edges of D1 are input.
This is memory address overtaking detection. Further, the Q output of the detection output D2 becomes L level at the next RRST timing when the CK input of D1 does not rise.
This is also a memory address overtaking detection.

This circuit malfunctions when there are three or more rising edges in the CK input of D1, but there is no practical problem. This is because the WRST cycle is RRST in this circuit.
This is because it is possible to measure from half to twice the period.

(Memory Address Overtaking Detection Unit 3) The memory address overtaking detection units 1 and 2 described above detect only one memory write / read sequence at the moment when the memory overtaking occurs. Jitter can be detected by delaying this detection for a predetermined time. For example, if the time is extended for about 0.5 seconds, it is possible to detect that a jitter frequency of about 1 second is generated.

FIG. 7A shows the memory outpacing detection means 3. The frequency comparator 40 in the figure is the same as the above-mentioned frequency comparator (FIGS. 1 and 4 etc.), and the output of the frequency comparator 40 is time-expanded by the time-expanding circuit 41 to expand the predetermined time detection result.

FIG. 7B shows a concrete example of the time extension circuit 41. The predetermined time detection result is extended from the change timing of the output signal A of the frequency comparator 40. The signal A is supplied to the CK input terminal of the D-type flip-flop circuit 50. For example, if it is detected when the signal A is “L”, the flip-flop circuit 50 falls at the falling edge.
The Q output of is changed from "L" to "H". This Q output is supplied to the enable terminal of the counter 51. The counter 51 is a time-based C during operation.
K is counted and the counter output value is supplied to the equal comparator 52. The comparator 52 compares the counter output value with the extension time setting value, and clears the flip-flop circuit 50 and the counter 51 when the counter output reaches this setting value. The time extension result is output to the flip-flop circuit 50. The polarity inversion is Q output.

The memory address overtaking detection circuit has been described above. Next, a method of controlling the operation of the TBC circuit using this detection result will be described. (WRST Phase Control Circuit) FIG. 8 shows a WRST phase control circuit. The PLL circuit 60 multiplies the input horizontal synchronizing signal by N to obtain a signal. This signal is divided by N in the frequency dividing circuit 61. A signal divided by N from the frequency dividing circuit in the PLL circuit 60 may be used as another circuit. That is, it suffices to obtain signals of the same frequency that are phase-synchronized with the input horizontal synchronization. This signal is divided by P in the frequency dividing circuit 62. The value of P is set according to the memory capacity of the TBC memory (storage device) used. In this case, the memory capacity is P times one horizontal synchronization period. The P frequency-divided signal is phase-shifted by the phase shifter 63, differentiated by the differential circuit 64, and output as the WRST signal 65. If the amount of phase shift of the phase shifter 63 is controlled, W
The phase shift of the RST signal 65 can be controlled.

The configuration of the control signal generating circuit of the phase shifter 63 will be described. The oscillation output of the reference frequency oscillator 66 is input to the frequency dividing circuit 67 and frequency-divided by N, and the frequency dividing circuit 68 is further divided.
Is divided by P. Here, the output average frequencies of the two sets of the frequency dividing circuits 61 and 67 and the frequency dividing circuits 62 and 68 are the same. The RRST signal 70 is obtained by differentiating the output of the frequency dividing circuit 68 by the differentiating circuit 69. Frequency comparator 71
Then, the frequency of the output of the phase shifter 63 is compared with the frequency of the output of the frequency dividing circuit 68 to detect a case where the frequency is largely deviated, as in the memory outpacing circuit. The detection result is input to the counter 72 and counted. The count output is input to the remainder circuit 73 and the remainder for P is taken to be the control signal of the phase shifter 63 via the logic circuit 74. The frequency comparator 71 may have the circuit configuration as shown in FIGS. 2, 5, and 6 described above.

Next, a more specific description will be given with reference to FIG. The same numbers as those in FIG. 8 have the same functions and will not be described. When the frequency dividing circuit 62 and the phase shifter 63 are actually configured, as the frequency dividing circuit 75, each phase output of the frequency divided output of the frequency dividing circuit 75 is selected by the selection circuit 76 by the above-mentioned control signal.

When P of the P frequency dividing circuit is 2,
In particular, the circuit has a simple structure and can be realized by the specific circuit shown in FIG. In FIG. 10 (a), the same numbers as those in FIG. The difference from the circuit in Fig. 8 is that
The P frequency dividing circuit 62 is a frequency dividing circuit 80, and the phase shifter 63 is an exclusive OR circuit (hereinafter referred to as an EOR circuit) 81. Along with this, the P divider circuit 6 on the reference signal side
8 is also a frequency dividing circuit 83. Further, the counter 72, the remainder circuit 73, and the logic circuit 74 portion of FIG. 8 for processing the output of the frequency comparator 71 are replaced with the frequency dividing circuit 82 for simplification.

FIG. 10 (b) shows a waveform diagram for explaining the circuit operation of FIG. 10 (a). It is a waveform diagram of each part of the node of the alphabet symbol in FIG. Figure 10
In (b), the input data is a digitized input video signal. The lower case letters a, b, c, ... I are data in units of one line, and n, (n + 1), ... Are data strings corresponding to the memory length in units of two lines. In this case, the memory has a memory capacity capable of writing 2-line data. Signal A is WRST
The signal is a signal having a cycle, and the signal C is a signal having a RRST cycle. For example, the rising timing of the signal A is set to WRST.
At the timing, the 2-line data string of the input data string (n + 1) is written in the memory. In reading, data lines for two lines are sequentially read from the rising timing of the signal C. For example, if the rising edge of WRST does not occur in the RRST cycle at the (n + 2) th time in FIG. 10B, this is memory address overtaking. The output of the frequency comparator 71 becomes "L" at the next (n + 3) th and detects the memory address overtaking situation. When the trailing edge of the detection result is captured by the frequency divider 82 and the frequency is divided, the output of the frequency divider 82 changes from "L" to "H". This output is signal B. It can be seen that when the signal B and the signal A are processed by the EOR circuit 81, the rising edge of the WRST cycle signal is phase-shifted by the memory address overtaking detection. Therefore, the read data is at the bottom of FIG. 10B, and it can be seen that the phase shift of the read data is corrected as compared with the read data of the conventional diagram.

(RRST phase control circuit) FIG.
The structural example of a T phase control circuit is shown. This is the WRS of FIG.
It is a circuit similar to the T phase control circuit. However, the phase shifter 6
2 is only provided on the RRST signal processing side. The circuit operation is almost the same as the description of FIG. Hereinafter, the circuits corresponding to FIGS. 9 and 10 can be similarly configured.

(TBC Circuit Including WRST (or RRST) Phase Control Circuit) FIG. 12 shows a configuration example of a TBC circuit including a WRST phase control circuit. 8, 9, and 1
It is configured by including the circuit components such as the WRST phase control circuit described in 0 and the memory. Therefore, FIG. 12 shows the entire TBC circuit.

The input video signal 100 is converted into digital data by an analog / digital (A / D) converter 101. This input digital signal is subjected to writing / reading processing in the storage device 102, and in this process, time axis fluctuation (hereinafter referred to as jitter) existing in the input video signal is removed. The digital signal from which the jitter is removed is the D / A converter 1
Converted to an analog signal at 03, and output analog signal 11
It becomes 0.

In order to eliminate the time axis fluctuation, the PLL circuit and the frequency dividing circuit 6 are provided on the write side as described above.
The WCK signal and the WRTST signal are created using 0, 61, the frequency dividing circuit 62, the phase shifter 63, and the differentiating circuit 64. On the read side, the reference frequency oscillator 66, the frequency dividing circuits 67 and 68, the differentiating circuit 69, and the like are used, and the comparator 71 is used as the phase shift amount control signal creating means of the phase shifter 63. Similarly, a TBC including an RRST phase control circuit
The circuit is also shown in FIG. The same parts as those in the previous embodiment are designated by the same reference numerals, and the description thereof will be omitted.

(Through / TBC operation mode switching) VTR
In the case of the LD device or the LD device, the reproduced signal is disturbed when the mode of the device is changed, such as when the mode is changed from STOP (stop) to PLAY (reproduce), and the TBC process cannot be normally performed. Especially in the case of a TBC having a memory capacity of several lines, it is better to start the TBC operation only after the reproduction signal becomes stable.
That is, it is possible to prevent the screen from being disturbed by shifting to the TBC operation mode after detecting that the memory address has not passed.

In consideration of the above, it is better to use the above-mentioned memory address overtaking detection means and stop the TBC operation and output the input signal as it is when the memory address is overtaken.

FIG. 14 shows a configuration example 1 of the TBC circuit. The input video signal is converted into digital data by the A / D converter 200 and supplied to the storage device 201 and the selector 202. The selector 202 selects either the output of the storage device 201 or the output of the A / D converter 200 by a control signal described later. When selecting the output of the storage device 201, select T
The BC operation mode is the through mode when the output of the A / D converter 200 is selected. The output of the selector 202 is converted into an analog signal by the D / A converter 203.

The write sequence circuit has been described above, but will be described again. The horizontal separation signal is separated from the input video signal by the synchronization separation circuit 204. The PLL circuit 205 obtains an HD signal that is phase-synchronized with the horizontal synchronizing signal with reference to the horizontal synchronizing signal. Also, multiply by N and WC
Get K. The HD signal is frequency-divided by the frequency divider 207 to be a periodic signal having a time length corresponding to the memory length, and the periodic signal is differentiated by the differentiating circuit 208 to be a WRST signal.
On the other hand, an RCK signal is generated by the reference frequency oscillation circuit 209, and this signal is frequency-divided by the frequency dividing circuits 210 and 211.
The RRST signal is differentiated by the differentiating circuit 212. The result of frequency comparison of the outputs of the frequency dividing circuits 207 and 211 by the frequency comparator 213 is the memory address overtaking detection result as described above. The detection result is extended by the time extension circuit 214 for a predetermined period as described with reference to FIG. The expanded detection result is logically ANDed with the output of the standard / non-standard detection circuit 216, which will be described later, in the logic circuit 215 and becomes the control signal of the selection circuit 202 described above.

The standard / non-standard detection circuit 216 obtains an HD signal and a VD signal (vertical synchronization signal) from the PLL circuit 60,
The number of HD signals existing in the V section is counted, this count value is compared with a reference value, and the detection result is used as a detection output. For example, in the NTSC signal, the number of HD is 26 in the 1V period.
It is 2.5. If the value deviates from this, it is detected as a non-standard signal. In the case of a non-standard signal, the TBC is not applied, so the signal is through. However, it is not always necessary to use the standard / non-standard detection results when there is enough memory.

Next, a specific example 2 of the entire TBC circuit is shown in FIG.
Shown in Only the differences from FIG. 14 will be described. In FIG. 15, the frequency divider circuits 207 and 211 outputs are connected to the TBC.
The TBC ON detection circuit 217 that detects the start of the operation detects the result, and the holding circuit 218 holds the result and shifts to the TBC operation mode. The output of the logic circuit 215 changes the TBC operation mode flag held by the holding circuit 218 to the through mode flag. Holding circuit 218
Can be composed of, for example, an RS flip-flop. Then, the TBC ON detection result shows RS flip
The flop may be set and reset by the output of the logic circuit 215. The holding circuit 218 has only to have a similar function and is not limited to the RS flip-flop.

FIG. 16 shows a specific example 3 of the entire TBC circuit. Explaining only the difference from the circuit of FIG. 15, the phase shifter 21
8 is inserted in the output side of the frequency dividing circuit 207. The circuit operation by this insertion is as described in FIGS. 8, 9 and 10. Although not shown, a phase shifter may be inserted on the RRST signal side as described above.

An example of the configuration of the TBC ON detection circuit 217 will be described later, but the transition from the through mode to the TBC operation mode causes a delay time corresponding to the average delay of the storage device 201, so that an H skew may occur in some cases. Therefore, the output of the TBC ON detection circuit 217 is latched by a field pulse so as to change during the V blanking period. Then, even if the H skew occurs, the AFC completes the pull-in process during the V blanking period on the TV side, and the skew does not appear in the display screen.

(Fixed Delay / TBC Operation Mode Switching) Similarly to the above, it is also possible to stop the TBC operation and set a fixed delay when the memory address is overtaken. Fixed delay is TB
It is convenient to use the average delay amount of the C memory.

FIG. 17 shows a TBC circuit configuration example 1 having a fixed delay circuit, FIG. 18 shows the same configuration example 2 and FIG. 19 shows the same configuration example 3. These are obtained by replacing the through parts of FIGS. 14, 15 and 16 with the fixed delay circuit 300, which can be understood from the above description.

As a supplementary explanation, the transition from the fixed delay mode to the TBC operation mode may be performed in the V blanking cycle, but as shown in the TBC ON detection circuit described later, the phase of the WRST signal and the RRST signal match. You may detect by looking at. In this case, even if the mode is switched on the screen, H
This is because skew is unlikely to occur. That is, when the jitter is small, the delay time of the TBC storage device and the fixed delay circuit 3
This is because the delay times of 00 substantially match.

(TBC ON Detection Circuit) FIG. 20A shows a configuration example 1 of the TBC ON detection circuit 217. The phase detection circuit 301 performs phase detection of inputs A and B. Inputs A and B are WRS indicating the write reset cycle described above.
A T signal and an RRST signal indicating a read reset period. This phase detection output is compared with the reference value by the comparator 302, and if it matches the reference value, TBC may be turned on. For example, in the case of the circuits of FIG. 18 and FIG. 19, since the coincidence of the phases of the WRST and RRST signals is seen,
The reference value is 0. Further, if the comparator is a window comparator, it is detected that the phases substantially match. There is no problem if the H skew is in a range that cannot be perceived in the screen (several tens to several hundreds nsec).
Even if the detection result shows a match, if the output of the memory address overtaking detection circuit detects the overtaking, even if the phase matching information comes to the holding circuit 218, the TBC is detected.
It suffices not to shift to the operation mode.

FIG. 20B shows a second specific example. In addition to the phase detection circuit 301 and the comparator 302 of Specific Example 1,
A counter 303 is connected to the output of the comparator 302, and the counter 303 is used to count the number of times of phase matching during a period determined. By holding the counting result in the field cycle using the holding circuit 304, for example, it can be seen that the WRST signal and the RRST signal are substantially in phase during the current field period. The count value is compared with the reference value in the comparison circuit 305 to obtain the output result.

However, the reference value of the comparison circuit 305 is about 0, 1, or 2. In addition, the window comparator 302
The TBC ON condition can be relaxed by widening the window. These are determined by various specifications of the system.

FIG. 20C shows a configuration example of the phase detection circuit 301. It is composed of a sawtooth wave generation circuit 306 and a holding circuit (sample and hold circuit) 307 for its output.
This is a general phase detection circuit.

In the VTR, the reproducing head is switched by a head switching signal several lines before the V signal. Therefore, the phase discontinuity of the reproduced FM signal occurs at the head switching timing, and noise is generated. This noise may be mistakenly detected by the sync separation circuit and may be regarded as a horizontal sync signal. If the WRST signal created from this horizontal synchronization signal is out of phase, the memory address overtaking detection will operate. To prevent this, the memory address overtaking detection is stopped during the period including the head switching position.

FIG. 21 shows a configuration example of the head switching period stop circuit of the memory address overtaking detection circuit.
That is, the head switching section pulse generation circuit 401
Generates a head switching signal several lines before the vertical same signal (V signal) of the input video signal, and switches 403 so that the output of the memory address overtaking detection circuit 402 is cut off during the head switching period. Have control.

[0054]

The effects of the present invention will be summarized from the embodiments described above. It is possible to provide a practical system that suppresses the product price with a small memory capacity and eliminates the adverse effects such as immobility on the TV screen due to memory overtaking. Furthermore, by using the present invention, it is possible to provide a high-quality video device that suppresses fluctuations in the time axis in a reproduced image of a VTR or an LD device and is easy to see at a low price, which greatly contributes to a consumer video device. .

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a memory address overtaking detection circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of the frequency comparator of FIG.

FIG. 3 is a diagram showing an example of signal waveforms of respective parts of the frequency comparator of FIG.

FIG. 4 is a diagram showing a second embodiment of a memory address overtaking detection circuit according to the present invention.

FIG. 5 is a diagram showing another configuration example of the frequency comparator of the above embodiment.

FIG. 6 is a diagram showing still another configuration example of the frequency comparator of the above embodiment and its operation waveform example.

FIG. 7 is a diagram showing a third example of a memory address overtaking detection circuit and a concrete example of a time extension circuit according to the present invention.

FIG. 8 is a diagram showing an example 1 of a phase control circuit for WRST (write reset signal).

FIG. 9 is a diagram showing a specific configuration example 1 of a WRST phase control circuit.

FIG. 10 is a diagram showing a specific configuration example 2 of the WRST phase control circuit and an operation waveform example thereof.

FIG. 11 is a diagram showing an example 1 of a phase control circuit for RRST (readout reset signal).

FIG. 12 is a diagram showing a configuration example of a TBC circuit having a WRST phase control circuit.

FIG. 13 is a diagram showing a configuration example of a TBC circuit having an RRST phase control circuit.

FIG. 14 is a diagram showing a first example of the overall configuration of a TBC circuit according to the present invention.

FIG. 15 is a diagram showing an overall configuration example 2 of the TBC circuit of the present invention.

FIG. 16 is a diagram showing a third example of the overall configuration of the TBC circuit of the present invention.

FIG. 17 is a diagram showing an overall configuration example 4 of the TBC circuit of the present invention.

FIG. 18 is a diagram showing an overall configuration example 5 of the TBC circuit of the present invention.

FIG. 19 is a diagram showing an overall configuration example 6 of the TBC circuit of the present invention.

FIG. 20 is a diagram showing a configuration example of a TBC ON detection circuit and a configuration example of a phase detection circuit used in the circuit of the present invention.

FIG. 21 is a diagram showing an example of a stop circuit for a fixed period of memory address overtaking detection.

FIG. 22 is a diagram showing a configuration example of a conventional TBC circuit.

FIG. 23 is a diagram showing an outline of a storage device (memory) configuration.

FIG. 24 is a diagram shown for explaining the operation of the storage device.

FIG. 25 is a diagram shown for explaining an adverse effect when memory address overtaking occurs.

[Explanation of symbols]

2 ... Sync separation circuit, 3 ... PLL circuit, 5 ... Reference frequency oscillator, 6 ... Frequency divider, 8 ... Frequency comparator, 10 ... Counter, 11 ... Differentiation circuit, 13 ... Latch circuit, 14, 15 ...
Comparator, 16 ... AND circuit, 20 ... PLL circuit,
21 ... N divider circuit, 23 ... Frequency comparator, 30 ... Equal comparator, 40 ... Frequency comparator, 41 ... Time extension circuit, 50 ... D type flip-flop circuit, 51 ...
Counter, 52 ... Equal comparator, 60 ... PLL
Circuit, 61, 62, 67, 68 ... Frequency divider circuit, 63 ... Phase shifter, 64, 69 ... Differentiation circuit, 71 ... Frequency comparator, 72
... counter, 73 ... remainder circuit, 74 ... logic circuit, 75 ...
Frequency division circuit, 76 ... Selection circuit, 80, 82, 83 ... Frequency division circuit, 81 ... Excessive OR circuit, 101, 200
... Analog-to-digital (A / D) converter, 102, 201
... storage device, 103, 203 ... digital analog (D /
A) Converter, 104, 204 ... Sync separation circuit, 205 ...
PLL circuit, 207, 210, 211 ... Frequency divider circuit, 20
8, 212 ... Differentiation circuit, 209 ... Reference frequency oscillation circuit,
213 ... Frequency comparator, 214 ... Time extension circuit, 21
5 ... Logic circuit, 216 ... Standard / non-standard detection circuit, 217
... TBCON detection circuit, 218 ... Protection circuit, 219 ... Phase shifter, 300 ... Fixed delay circuit.

Claims (11)

[Claims] 1. The input signal is written in a memory by using a write clock signal and a write timing signal generated in phase synchronization with a synchronization signal included in the input signal,
In a time axis correction circuit for reading an output signal from the memory using a read clock signal and a read timing signal generated using a reference signal of an oscillating means, a first comparison signal phase-locked to the synchronization signal and the reference signal Based on the frequency comparison result with the phase-synchronized second comparison signal, detection means for detecting the read timing overtaking with respect to the write timing of the memory or the write timing overtaking with respect to the read timing, and the writing according to the detection result of this detecting means A time axis correction circuit having a phase shift means for controlling either the phase of the timing signal or the read timing signal. 2. The input signal is written in a memory by using a write clock signal and a write timing signal generated in phase with a synchronization signal included in the input signal,
In a time axis correction circuit for reading an output signal from the memory using a read clock signal and a read timing signal generated using a reference signal of an oscillating means, a first comparison signal phase-locked to the synchronization signal and the reference signal Based on the frequency comparison result with the phase-synchronized second comparison signal, detection means for detecting the read timing overtaking with respect to the memory write timing or the write timing overtaking with respect to the read timing, and the detection result of this detecting means are predetermined. A time stretching means for stretching the time by a given time, and a selecting means for selecting whether to derive the input signal as it is without passing through the memory or to derive the memory output according to the result of the stretching performed by the time stretching means. Time axis correction circuit characterized by having 3. The time axis according to claim 2, wherein the transition timing from the mode for deriving the input signal as it is to the mode for deriving the output of the memory is during the vertical blanking period of the input signal. Correction circuit. 4. The input signal is written into a memory by using a write clock signal and a write timing signal which are generated in phase with a synchronization signal included in the input signal,
In a time axis correction circuit for reading an output signal from the memory using a read clock signal and a read timing signal generated using a reference signal of an oscillating means, a first comparison signal phase-locked to the synchronization signal and the reference signal Based on the frequency comparison result with the phase-synchronized second comparison signal, detection means for detecting the read timing overtaking with respect to the write timing of the memory or the write timing overtaking with respect to the read timing, and the detection result of the detecting means in advance A time stretching means for stretching the time by a predetermined time, and according to the stretching result of the time stretching means, derives a signal obtained by delaying the input signal by a fixed delay means corresponding to the average delay time of the memory, or Selecting means for selecting whether to derive the memory output; Time base correction circuit, characterized in that it has. 5. A memory write timing is a transition timing from a mode for deriving a signal obtained by delaying the input signal by a fixed delay means by a delay time corresponding to an average delay time of the memory to a mode for deriving the memory output. A time axis correction circuit characterized in that when a difference in memory read timing falls within a predetermined phase range. 6. The detection means sets a signal obtained by multiplying a synchronization signal included in the input signal by M (M is a natural number) as the first comparison signal, and uses the first comparison signal as the second comparison signal. For two cycles, the count value is compared with the comparison value, and the result of this comparison is used to detect the passing of the read timing with respect to the write timing of the memory or the overtaking of the write timing with respect to the read timing. The time axis correction circuit according to claim 1. 7. The detection means uses a signal obtained by dividing the synchronization signal included in the input signal by N as the first comparison signal, and uses the first comparison signal as one cycle of the second comparison signal. 5. The time axis correction circuit according to claim 1, wherein the time axis is counted, and it is determined whether the counting result is 1 or not. 8. The input signal is written to a memory by using a write clock signal and a write timing signal which are generated in phase with a synchronization signal included in the input signal,
In a time axis correction circuit for reading an output signal from the memory using a read clock signal and a read timing signal generated using a reference signal of an oscillating means, a signal obtained by dividing the synchronization signal included in the input signal by N 1 comparison signal, the first comparison signal is counted for one cycle period of the second comparison signal phase-synchronized with the reference signal, and it is judged whether the count result is 1 or not, and this judgment is made. According to the result, a detection unit that detects the read timing overtaking with respect to the memory write timing or the write timing overtaking with respect to the read timing, and one of the write timing and the read timing is detected according to the detection result of the detecting unit. When it is provided with a phase control means for controlling Axis correction circuit. 9. The input signal is written to a memory by using a write clock signal and a write timing signal generated by being phase-synchronized with a synchronization signal included in the input signal,
In a time axis correction circuit for reading an output signal from the memory using a read clock signal and a read timing signal generated using a reference signal of an oscillating means, a signal obtained by dividing the synchronization signal included in the input signal by N 1 comparison signal, the first comparison signal is counted for one cycle period of the second comparison signal phase-synchronized with the reference signal, and it is judged whether the count result is 1 or not, and this judgment is made. According to the result, a detection unit that detects an overtaking of the read timing with respect to the write timing of the memory or an overtaking of the write timing with respect to the read timing, and a time extending unit that extends the detection result of the detecting unit by a predetermined time. The input signal is passed through the memory according to the result of the time stretching means. Accept derived, time base correction circuit, characterized in that it has a selection means for selecting whether to derive the memory output without. 10. A read clock signal generated by writing the input signal in a memory by using a write clock signal and a write timing signal which are generated in phase with a synchronizing signal included in the input signal and generated by using a reference signal of an oscillating means. And a time axis correction circuit for reading an output signal from the memory using a read timing signal, a signal obtained by dividing the synchronization signal included in the input signal by N is used as a first comparison signal, and the first comparison signal is One cycle period of the second comparison signal phase-synchronized with the reference signal is counted, and it is determined whether the count result is 1 or not 1, and the read result overtakes the read timing with respect to the write timing of the memory, Or a detection means for detecting the passing of the write timing with respect to the read timing, and A time stretching unit that stretches the detection result of the detection unit by a predetermined time, and the input signal is delayed by a fixed delay unit corresponding to the average delay time of the memory according to the stretching result of the time stretching unit. And a selecting means for selecting whether to derive the memory output or the memory output. 11. A means for disconnecting the output of the detecting means for detecting the passing of the read timing with respect to the write timing of the memory or the overtaking of the write timing with respect to the read timing in the vicinity of the head switching timing of the VTR. The time axis correction circuit according to any one of claims 1, 2, 4, 8, 9, and 10.