JPH07112190B2 - Synchronizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization type synchronizer for receiving equipment which receives a burst digital signal containing a clock component fo.

2. Description of the Related Art A conventional frame synchronization type synchronization device that detects a frame synchronization code from a digital signal that continuously contains a clock component fo, that is, a digital signal whose data changes at 1 / fo (time) and synchronizes reception equipment. Will be described with reference to the block diagram of FIG.

The sync code detection circuit 1 receives the digital signal 1a continuously containing the clock component fo, detects the match of the final bits of the frame sync code in this signal, and outputs the match signal 1b. It is composed of a PLL and receives a digital signal 1a continuously including a clock component fo and outputs a reproduction clock 2b which is phase-synchronized with the frequency of the clock component fo. The gate signal generation circuit 6 is composed of a synchronous counter, resets by the coincidence signal 1b of the synchronous code detection circuit 1, counts the reproduction clock 2b of the clock reproduction circuit 2, and outputs the gate signal at the output timing of the coincidence signal 1b.
6b is generated and output, and the synchronization determination circuit 4 inputs this gate signal 6b and the coincidence signal 1b of the synchronization code detection circuit 1, and one change point of the coincidence signal 1b is the gate period 1 / fo of the gate signal 6b.
If it is within the period, it is determined to be the synchronous state, and if it is not within the period, it is determined to be the asynchronous state and the determination signal 4b is output.

The operation will be described below with reference to the characteristic diagrams of FIG. 3 and FIG.

The digital signal 1a continuously including the clock component fo is input to the sync code detection circuit 1, and the coincidence signal 1b is output during the period 1 / fo at the final bit of the frame sync code. In the clock reproduction circuit 2, a PLL is configured with the digital signal 1a continuously including the clock component fo as a reference, and the reproduction clock 2b phase-synchronized with the frequency fo is output. In the gate signal generating circuit 6, the gate signal is generated by the synchronous counter, and the coincidence signal 1b is output at time T ₁ in FIG. 5 to reset the counter. The counter then counts according to the playback clock 2b, and the output timing of the match signal 1b
It continues to generate a gate signal 6b at _{T 2, T 3, T 4} . The synchronization determination circuit 4 compares the phases of the match signal 1b and the gate signal 6b, and there is one change point (the rising timing in FIG. 5) of the match signal 1b within the period of 1 / fo of the gate signal 6b. For example, it is determined to be in the synchronized state, and as shown in FIG. 5, the determination signal 4b becomes high level at time T ₂ and the receiving equipment is in the synchronized state.

Problems to be Solved by the Invention However, in the above configuration, when the input digital signal 1a becomes a burst digital signal, the time required from the asynchronous state to the synchronous state becomes long due to the following reasons. Had.

If the period containing the clock component fo becomes bursty in the clock reproduction circuit 2, the phase pull-in of the PLL circuit becomes particularly unstable in the process from the asynchronous state to the synchronous state. FIG. 4 shows a typical configuration example of the clock reproducing circuit. Burst digital signal 1a 'containing clock component fo
And the phase of the reproduction clock 2b, which is the output of the voltage controlled crystal oscillator 23, are compared by the phase comparator 21, and the control voltage 22b is output through the LPF (low pass filter) 22. FIG. 6 shows the change of the control voltage 22b from the asynchronous state and the operation timing of each part. Control voltage 22b is PLL in the first frame synchronization code period is increased to around the voltage to lock, the match signal 1b in the synchronization code detecting circuit 1 at time T ₁ is output. However, the subsequent period is a period in which the clock component information is not included, and since clock reproduction cannot be performed, this control voltage 22b must be held until the next clock component period. Further, if the period for which the voltage is held becomes long, the voltage will drop due to circuit leakage or the like, and the reproduction clock 2b will fluctuate, and the gate signal generation circuit 6
In the timing of the gate signal 6b which is generated by the synchronization counter, it would be output at the timing before and after not output at time t _2. It was but connexion, control voltage 22b is not determined that the synchronization state reception facility until the period of stable, again resets the synchronization counter gate signal generating circuit 6 at time T _3, the control voltage 22b at time T ₄ is where stable Become in sync. When the burst digital signal 1a ′ including the clock component fo is input in this way, the time required to detect the synchronous state from the asynchronous state is longer than that of the digital signal 1a in which the clock component fo is continuously included. There was a problem that it would be spoiled.

The present invention solves the above-mentioned problems, and even when a burst-shaped digital signal containing the clock component fo is input, the time required to reach the synchronization state is continuously input with the digital signal containing the clock component fo. It is an object of the present invention to provide a synchronizer capable of synchronizing the receiving equipment at the same time as the case.

Means for Solving the Problems In order to solve the above problems, the synchronization device of the present invention is a clock reproduction circuit which receives a burst digital signal including a clock component fo and reproduces a clock signal synchronized with the phase of the clock component fo, Detecting the coincidence of the frame sync code in the burst digital signal containing the clock component fo,
A sync code detecting circuit which outputs a coincidence signal and a coincidence signal which is an output of the sync code detecting circuit are reset, and the reproduction clock which is an output of the clock reproducing circuit is counted to obtain the first gate signal and the first gate signal. Before and after the gate signal of
A gate signal generation circuit that outputs a second gate signal in the range of N / fo (N is a natural number), a switching signal that uses the first gate signal as one input and the second gate signal as the other input Therefore, in the case of the asynchronous state, the second gate signal is selected, and in the case of the synchronous state, the first gate signal is selected and output, and the selection output signal which is the output of the selection means and the coincidence signal are input. If the change timing of one of the coincidence signals is within the range of the selection signal, it is determined to be in the synchronous state, and if it is out of the range, the determination signal is output and the determination signal is output, and this determination signal is output as the switching signal of the selection means. It is provided with a synchronization determination circuit for doing so.

With the above configuration, the first signal generated in the gate signal generation circuit is generated.
The phase of the coincidence signal of the synchronous code detection circuit is compared with the phase of the gate signal or the second gate signal of the synchronous judgment circuit. Immediately after the first match signal is detected, the operation of the clock regeneration circuit is unstable.Therefore, the gate signal generated by the gate signal generation circuit is reset by the coincidence signal and the reproduction clock is counted. Is not always output at the same timing. Therefore, by extending the gate period of the gate signal to N / fo, the phase shift of the output timing of the gate signal during the unstable period of the reproduction clock is canceled. By doing so, it becomes possible to put the receiving equipment in a synchronized state in the next frame after the first coincidence signal is detected. Therefore, even if a burst digital signal containing the clock component fo is input, the time required for the synchronization state is continuously changed by the clock component.
It is possible to do the same as when a digital signal including fo is input.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. The same components as those shown in FIGS. 3 and 4 of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a block diagram of a synchronizer showing an embodiment of the present invention.

The gate signal generating circuit 3 is composed of a synchronous counter, resets by the coincidence signal 1b of the synchronous code detecting circuit 1, counts the reproduced clock 2b of the clock reproducing circuit 2, and outputs the gate signal 3a of the gate period 1 / fo. The gate signal 3b is output, and further, the gate signal 3b is output in a range (gate period) of N / fo (N is a natural number) before and after the gate signal 3a. The selection means 5 is means for selecting the gate signal 3a and the gate signal 3b generated by the gate signal generation circuit 3 and outputting them to the synchronization determination circuit 4, and the determination signal 4b of the synchronization determination circuit 4 is at a low level, that is, the receiving equipment. When the signal is in the asynchronous state, the gate signal 3b is selected, and when the determination signal 4b is at the high level, that is, when the signal is in the synchronous state, the gate signal 3a is selected and output to the synchronization determination circuit 4 as the selected output signal 5b.

Regarding the synchronizer configured as described above, FIG.
The operation will be described with reference to FIGS. 2 and 4.

The burst digital signal 1a 'containing the clock component fo is input to the sync code detection circuit 1 and the coincidence detection of the frame sync code is performed. At times T _{1 to} T ₄ , the coincidence detection signal 1b is output during the 1 / fo period of the last bit of the sync code. The control voltage 22b in the PLL structure of the clock reproduction circuit 2 shown in FIG. 4 is reproduced in the clock during the period of the synchronous code, and the clock component information is not included in the other periods, so the control voltage 22b is held. There is. In the gate signal generating circuit 3, the reproduction clock is reproduced by the synchronous counter with reference to the coincidence signal 1b.
It counts 2b and outputs gate signals 3a and 3b, respectively. Gate signal 3a is counted by the counter to be output at time T _2, T _3, T ₄ is the output timing of the coincidence signal 1b. However, when the synchronous code is first detected in the asynchronous state, the control voltage 22b has not yet reached the voltage at which the PLL is locked, and if the voltage holding period becomes long, the control voltage fluctuates due to voltage leakage. The phase of the reproduction clock 2b becomes unstable. Was it even by generating gate signals 3a counts the number of the reproduction clock 2b until connexion time T _2,, which may time T _2, the coincidence signal 1b is output does not fall within the gate period. Therefore, the gate signal 3b is generated in the range of N / fo before and after the gate signal 3a (N = 3 in the embodiment, which will be described later). At the time T ₂ , when the phase is compared by the synchronization determination circuit 4, the determination signal is compared with the gate signal 3b in which the range of the gate period is widened.
4b goes high and the system is in sync. After the synchronization, the phases of the gate signal 3a and the coincidence signal 1b are compared to determine the synchronization.

Thus, even when the burst digital signal 1a 'including the clock component is input and the initial operation of the clock reproduction circuit 2 becomes unstable, the phases of the coincidence signal 1b and the gate signals 3a, 3b are compared to determine the synchronization. When you do the first match signal 1b
By performing the synchronization judgment with the signal 3b, which is the expanded gate period of the gate signal in the phase comparison after the detection of, the detection of the synchronization state can be performed in the same required time as when the digital signal including the continuous clock component is input. It can be carried out.

It goes without saying that the gate signal generating circuit 3 and the selecting means 5 may be realized by one block.

As described above, according to the present invention, the first gate signal that outputs the gate signal at the output timing of the coincidence signal and the gate signal in the range of N / fo (N is a natural number) before and after the first gate signal. A gate signal generation circuit for generating a second gate signal for outputting the first gate signal as one input and the second gate signal as the other input, and the second gate when the switching signal is in an asynchronous state When the signal is in the synchronous state, the selection means for selecting and outputting the first gate signal, the selection output signal which is the output of the selection means, and the coincidence signal are input, and the change timing of one of the coincidence signals is selectively output. By providing a synchronization determination circuit that determines that the signal is within the signal range is in the synchronous state, and if it is out of the range, the determination signal is output, and the determination signal is output as the switching signal of the selecting means. Even if a burst digital signal containing a clock component is input and the initial operation of the clock regeneration circuit becomes unstable, when comparing the phases of the match signal and the gate signal for synchronization determination, By performing the synchronization determination with the second gate signal in which the gate period in the phase comparison is widened, the synchronization state can be detected in the same required time as when the digital signal including the continuous clock component is input. .

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronizer showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of each part when a digital signal including a clock-like burst component is input to the synchronizer, and FIG. A block diagram of a conventional synchronizer, and FIG. 4 is a block diagram of a PLL circuit that constitutes a clock reproducing circuit.
FIG. 5 and FIG. 6 are operation waveform diagrams of respective parts when a signal continuously including a clock signal is input to a conventional synchronizer and when a digital signal including a clock component in a burst is input. is there. DESCRIPTION OF SYMBOLS 1 ... Sync code detection circuit, 2 ... Clock reproduction circuit, 3 ... Gate signal generation circuit, 4 ... Sync determination circuit, 5 ... Selection means,
1a '... digital signal, 1b ... coincidence signal, 2b ... reproduction clock, 3a ... first gate signal, 3b ... second gate signal, 4b
... discrimination signal (switching signal), 5b ... selection output signal.

Claims (1)

[Claims] 1. A clock reproducing circuit for inputting a burst digital signal containing a clock component fo and reproducing a clock signal synchronized with the position of the clock component fo, and a frame synchronization code in a burst digital signal containing the clock component fo. A sync code detecting circuit which detects a match and outputs a match signal, and a match signal which is an output of the sync code detecting circuit is set to count a reproduction clock which is an output of the clock reproducing circuit to count the first gate. Signal and this first
The second gate signal in the range of N / fo (N is a natural number) before and after the gate signal is output. A gate signal generation circuit and the first gate signal as one input, the second gate signal as the other input, and the switching signal causes the second gate signal to be input in the asynchronous state, and the second gate signal to be input in the synchronous state. If the selecting means for selecting and outputting the gate signal of No. 1 and the selecting output signal which is the output of the selecting means and the coincidence signal are inputted and the timing of one change of the coincidence signal is within the range of the selecting output signal A synchronization device, comprising: a synchronization state; and a synchronization determination circuit that outputs a determination signal when the state is out of the range and outputs the determination signal as an asynchronous state, and outputs the determination signal as a switching signal of the selecting means.