JPH0878434A - Heterojunction bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE: To reduce the base resistance while preventing external contamination and damage to a semiconductor layer in the course of film formation. CONSTITUTION: The title transistor is provided with the following; first compound semiconductor layers 15/16 of a first conductivity type whose sections are trapezoidal, second compound semiconductor layers 17a, 17b, 17c of the opposite conductivity type wherein the film on the slant parts 16a, 16b of the trapezoid is thinner than the film on the plane part 16a, third compound semiconductor layers 18d/19a, 18e/19b of a conductivity type formed on the second compound semiconductor layers 17b, 17c on the slant parts 16b, 16c of the trapezoid, and an electrode 21a connected with the second compound semiconductor layer 17a on the plane part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (HBT) and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, a bipolar transistor (hereinafter referred to as an HBT) using a heterojunction such as a compound semiconductor can increase the emitter injection efficiency and is therefore advantageous for high gain and high speed. Attention has been paid to the semiconductor device or the device for ultra-high speed computer.

In order to obtain the device characteristics sufficiently to achieve higher gain and higher speed, the maximum oscillation frequency f
It is necessary to further increase _max (= √ (f _T / 8πR _B C _BC )). In particular, HBTs using AlGaAs / GaAs compound semiconductor materials have been actively researched and developed using crystal growth technology and process technology accumulated in semiconductor lasers, etc., in order to improve the maximum oscillation frequency,
Base resistance R _B is reduced and base / collector capacitance C
Various measures have been taken to reduce _BC (Japanese Patent Laid-Open No. Hei 1)
-124257, JP-A-63-248167, JP-A-63-226962).

FIG. 11 is a sectional view showing a conventional HBT. A high-concentration subcollector layer 2 is formed on a semi-insulating substrate 1, and a collector layer 3, an intrinsic base layer 4a, and an emitter layer 5 are sequentially stacked in a narrow region on the subcollector layer 2. This reduces the junction area between the collector layer 3 and the intrinsic base layer 4a and lowers C _BC .

On the collector layers 3 on both sides of the intrinsic base layer 4a, the external base layers 4b and 4c are connected to the intrinsic base layer 4a and have a higher concentration than the intrinsic base layer 4a and a large layer thickness. Are formed. As a result, the base resistance R _B is reduced. The main part of the above HBT is created as follows, for example. After the collector layer 3 and the compound semiconductor layer to be the intrinsic base layer 5a are selectively grown on the sub-collector layer 2, etching is performed while leaving the central portion to be the intrinsic base layer 5a. Then, after etching, the surface of the thin collector layer 3 remaining in the peripheral portion is wet-treated to remove the surface layer, and then the external base layers 4b and 4c are selectively regrown on the thin collector layer 3 remaining in the peripheral portion. To do. As a result, the main part of the HBT is formed.

In another method for reducing the base resistance R _B , after forming the base layer on the collector layer, ions are selectively implanted into the peripheral base layer which will be the external base layer to reduce the resistance. There is a way to do it.

[0007]

However, in the method of regrowth of the external base layers 4b and 4c, although the surface to be grown is cleaned, as compared with the case of continuous formation, There is a risk that a natural oxide film may be formed at the interface between the external base layers 4b and 4c and the intrinsic base layer 4a, or that contamination with a contaminant may occur.

For this reason, there is a problem that the manufacturing yield is lowered due to an increase in resistance and an increase in leak current. In addition, the method of implanting ions into the base layer to be the external base layer has a problem that damage is introduced into the remaining semiconductor layer. The present invention was created in view of the problems of the conventional example, and a semiconductor device capable of reducing the base resistance while preventing external contamination during the film formation and introduction of damage to the semiconductor layer. And a method for manufacturing the same.

[0009]

The first object is to provide a first compound semiconductor layer having a trapezoidal cross section with one conductivity type and a trapezoidal slope formed on the first compound semiconductor layer. Part of the second compound semiconductor layer of opposite conductivity type having a smaller film thickness than that of the flat surface part, and the third compound of one conductivity type formed on the second compound semiconductor layer of the trapezoidal slope part. A second aspect of the present invention is achieved by a heterojunction bipolar transistor having a compound semiconductor layer and an electrode connected to the second compound semiconductor layer of the planar portion, and secondly, the second compound semiconductor layer is the trapezoidal planar portion. In the heterojunction bipolar transistor according to the first aspect of the present invention, the carrier concentration is higher than that in the slope portion.
Thirdly, the second compound semiconductor layer is laterally separated by the trapezoidal plane portion.
And a fourth one conductivity type trapezoidal cross section.
And a second compound semiconductor layer of the opposite conductivity type formed on the first compound semiconductor layer, the second compound semiconductor layer having an opposite conductivity type, the film thickness being thinner in the flat portion of the trapezoid than in the slope portion, Heterojunction bipolar transistor having a third compound semiconductor layer of one conductivity type formed on the second compound semiconductor layer in the plane part of the above and an electrode connected to the second compound semiconductor layer in the sloped part Achieved by the fifth
In the heterojunction bipolar transistor according to the fourth aspect of the invention, the second compound semiconductor layer has a higher carrier concentration in the inclined surface of the trapezoid than in the flat surface. According to a sixth aspect of the present invention, there is provided the heterojunction bipolar transistor according to the fourth or fifth aspect of the invention, wherein the second and third compound semiconductor layers are laterally separated by the trapezoidal planar portion. Seventh, the first compound semiconductor layer is a collector layer or an emitter layer, the second compound semiconductor layer is a base layer, and the third compound semiconductor layer is an emitter layer or a collector layer. And a step of forming a selective growth mask on a substrate of one conductivity type, and a crystal by the selective growth mask. Forming a first compound semiconductor layer of one conductivity type having a trapezoidal cross section on the substrate by utilizing anisotropy of growth based on the orientation, and a crystal plane orientation on the first compound semiconductor layer. Forming a second compound semiconductor layer of the opposite conductivity type in which the film thickness of the trapezoidal slope portion is smaller than the film thickness of the flat portion by utilizing the anisotropy of growth based on the above; Forming a third compound semiconductor layer having an opposite conductivity type on the compound semiconductor layer, and selectively etching the third compound semiconductor layer in the plane portion to expose the second compound semiconductor layer. And a step of forming electrodes on the exposed second compound semiconductor layer and on the third compound semiconductor layer remaining on the slope portion, respectively. Achieved, ninth, top The third compound semiconductor layer is formed, an etching resistant film is formed so that the top portion projects, and the third compound semiconductor layer is selectively etched from the projecting top portion to form the second compound semiconductor layer. Which is achieved by the method for producing a heterojunction bipolar transistor according to the eighth aspect of the present invention, and tenthly, by selectively etching the third compound semiconductor layer, On the second compound semiconductor layer, instead of exposing the second compound semiconductor layer and forming an electrode on the second compound semiconductor layer, the third compound semiconductor layer is selectively etched. And forming the electrode on the remaining third compound semiconductor layer, and then heating the electrode to penetrate the electrode to form the second compound semiconductor layer.
It is achieved by the method for manufacturing a heterojunction bipolar transistor according to the eighth or ninth invention, which is characterized in that the crystal plane orientation of the substrate is <100> direction or An eighth to a sixth aspect, which has a direction equivalent to the <100> direction and a crystal plane orientation of the trapezoidal slope portion is a <111> B direction or a direction equivalent to the <111> B direction. The present invention is achieved by the heterojunction bipolar transistor according to any one of the tenth invention, and twelfth, the crystal plane orientation of the substrate has a <100> direction or a direction equivalent to the <100> direction, and the slope portion The crystal plane orientation of the <311> A direction is <311> A, and the impurity imparting the other conductivity type to the second compound semiconductor layer is beryllium. It is achieved by the heterojunction bipolar transistor according according to any one, 13
A step of forming a selective growth mask on a substrate of one conductivity type, and a first compound of one conductivity type having a trapezoidal cross section by utilizing the anisotropy of growth based on the crystal plane orientation by the selective growth mask. Forming a semiconductor layer on the substrate;
On the compound semiconductor layer, the film thickness of the trapezoidal slope portion is thinner than the film thickness of the flat surface portion by utilizing the anisotropy of growth based on the crystal plane orientation. A step of forming a third compound semiconductor layer of opposite conductivity type on the second compound semiconductor layer, and a step of forming an electrode on the third compound semiconductor layer of the planar portion. A step of selectively removing the third compound semiconductor layer on the slope portion to expose the second compound semiconductor layer; and a step of forming an electrode on the exposed second compound semiconductor layer. 14th step of forming an electrode on the third compound semiconductor layer of the plane portion is performed by exposing the plane portion of the third compound semiconductor layer. Form an etching resistant film and expose A method for manufacturing a heterojunction bipolar transistor according to the thirteenth invention, which comprises the step of forming an electrode on the flat surface of the third compound semiconductor layer and removing the etching resistant film. Fifteenth, the crystal plane orientation of the substrate is <100
> Direction or a direction equivalent to the <100> direction,
15. The heterostructure according to any one of the tenth, thirteenth and fourteenth inventions, wherein the crystal plane of the trapezoidal slope has a <111> A direction or a direction equivalent to the <111> A direction. This is achieved by a method for manufacturing a junction bipolar transistor.

[0010]

In the semiconductor device of the present invention, the first compound semiconductor layer of one conductivity type having a trapezoidal cross section has the trapezoidal slope surface portion of which the film thickness is smaller than that of the flat surface portion of the opposite conductivity type. Two
And the third compound semiconductor layer of one conductivity type is provided on the second compound semiconductor layer of the slope portion.

In order to form such a multi-layered compound semiconductor layer, in the method of manufacturing a semiconductor device of the present invention, the <111> B plane orientation and
Second on the first compound semiconductor layer having a 100> plane orientation
The compound semiconductor layer of is formed. At this time, the formed second compound semiconductor layer has a thick portion in the <100> direction and a thin portion in the <111> B direction.

In this case, for example, when the first compound semiconductor layer is the collector layer or the emitter layer, the second compound semiconductor layer is the base layer, and the third compound semiconductor layer is the emitter layer or the collector layer, the sloped portion is formed. Of the second compound semiconductor layer becomes an intrinsic base layer, and the second compound semiconductor layer of the plane portion becomes an external base layer. Therefore, the slope portion becomes the main portion of the transistor through which the collector current flows.

According to the above, since the thickness of the external base layer is large, the resistance of the external base layer can be reduced, and therefore the overall base resistance can be reduced. Furthermore,
By utilizing the crystal plane anisotropy of the carrier concentration, the carrier concentration is more selectively selected in the second compound semiconductor layer having the <100> plane orientation than in the second compound semiconductor layer having the <111> B plane orientation. Can be higher. As a result, an intrinsic base layer having a low carrier concentration and an external base layer having a high carrier concentration can be formed at the same time, and the base resistance can be further reduced.

Further, by utilizing the crystal plane anisotropy of growth on the trapezoidal first compound semiconductor layer having the <111> A plane orientation in the slope portion and the <100> plane orientation in the plane portion. Second
When the compound semiconductor layer is formed, the film thickness at the slope and the plane is opposite to the above case, and the second compound semiconductor layer having a larger thickness at the slope than at the plane is formed at the same time. You can In this case, on the contrary to the above,
Of the compound semiconductor layer as the external base layer,
The compound semiconductor layer of (1) serves as an intrinsic base layer, and the overall base resistance can be reduced in the same manner as above.

Further, according to the method of manufacturing a semiconductor device of the present invention, the first to third compound semiconductor layers forming the transistor are continuously formed without interposing other steps such as surface treatment and ion implantation. be able to. Therefore, it is possible to prevent external contamination and introduction of damage to the semiconductor layer during film formation. Further, since the top is formed on the uppermost third compound semiconductor layer and the resist film is formed so that the top projects, the patterning of the resist film is not necessary.

Further, when the second compound semiconductor layer is formed by utilizing the crystal plane anisotropy of the growth on the trapezoidal first compound semiconductor layer crystal having the plane orientation of <311> A direction in the slope portion. The second compound semiconductor layer on the slope has a plane orientation of <311> A direction. When Be is doped in such a second compound semiconductor layer, it is possible to prevent Be from migrating toward the first and third compound semiconductor layers due to an electric field and a current applied during the operation of the transistor. This makes it possible to prevent the transistor characteristics from varying due to the decrease in the concentration of the second compound semiconductor layer.

Further, since the third compound semiconductor layer is separated and an electrode is formed on the second compound semiconductor layer, when removing the third compound semiconductor layer on the second compound semiconductor layer,
I did not remove everything, but left it thin. Therefore, the entire second compound semiconductor layer is covered with the third compound semiconductor layer. Therefore, when the second compound semiconductor layer is used as the base layer, the thin third compound semiconductor layer functions as a guard ring that covers the external base layer, and the characteristics and reliability of the HBT can be improved. .

Further, when the external base layer is formed on the flat surface portion, the collector layer is formed on the upper layer, and the emitter layer is formed on the substrate side, when the external base layer on the flat surface portion is separated, the base and the collector are separated to separate the emitter. It is possible to create a differential amplifier in which two common transistors are connected in parallel. In this case, both transistors can be formed in the immediate vicinity of each other, so that the manufacturing variation of the two transistors can be reduced and a transistor having uniform characteristics can be manufactured.

Further, in the case where the external base layer is formed on the sloped portion, contrary to the above, by separating the collector layer and the intrinsic base layer in the planar portion, a differential transistor composed of two transistors having the same characteristics as the above is formed. An amplifier can be created.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (1) Description of the manufacturing method of HBT which concerns on the 1st Example of this invention FIG.1 (a)-(c), FIG.2, FIG.3 (a), (b), FIG.
(A)-(c) and FIG. 5 (a)-(c) are the 1st of this invention.
FIG. 6 is a cross-sectional view showing the method of manufacturing the HBT according to the example of FIG.

First, as shown in FIG. 1A, the MBE method (molecular beam epitaxy method), the GSMBE method (gas source molecular beam epitaxy method), the MONBE method (organic metal molecular beam epitaxy method), the CBE method or the MOCVD method. N ⁺ -GaAs having a film thickness of about 400 nm, which is obtained by doping the (001) plane of the semi-insulating GaAs substrate 11 with Si at a concentration of about 5 × 10 ¹⁸ cm ⁻³ by a method such as metal organic chemical vapor deposition. The layer (first subcollector layer) 12 is formed.

Next, as shown in FIG. 1B, after forming a SiON film (selective growth mask) 12 having a film thickness of about 100 nm, patterning is performed and an opening 1 of 10 μm × 10 μm is formed.
The selective growth mask 12 having No. 4 is formed. At this time, as shown in FIG. 2, the patterns are arranged such that the longitudinal direction is the <110> direction. Next, MONBE method, CBE
A collector layer, a base layer and an emitter layer are sequentially formed on the GaAs substrate 11 at the bottom of the opening 14 by using an epitaxial growth method such as a MOCVD method or a MOCVD method. Hereinafter, a method of forming each layer will be described with reference to FIGS. 1C, 2, and 3A and 3B. The crystal plane orientation of growth is used in film formation.

That is, as shown in FIG. 1C, a Ga molecular beam, an As molecular beam and Si as an n-type dopant are used.
2μm, Si concentration 5 × 10 ¹⁸ c
An n ⁺ -GaAs layer (second subcollector layer) 15 having m ⁻³ is formed. At this time, it is formed under the condition that the growth rate in the <111> B direction is lower than the growth rate in the <001> direction. For example, in the GSMBE method, TEGa, AsH ₃ , and Si ₂ H ₆ are used and grown at a growth temperature (Ts) of 580 ° C. and a V / III ratio of about 5. As a result, the n ⁺ -GaAs layer (second subcollector layer) 15 has a trapezoidal shape as shown in FIG. The plane orientation of the trapezoidal upper flat portion 15a is in the <001> direction, and the plane orientations of the inclined surfaces 15b and 15c along the longitudinal direction are in the <111> B direction. The plane orientations of the slope portions 15d and 15e facing in the longitudinal direction are the <111> A direction.

Next, as shown in FIG. 2, n having a Si concentration of 3 × 10 ¹⁶ cm ^-3 is used by using a Ga molecular beam, an As molecular beam and a Si molecular beam as an n-type dopant.
-A GaAs layer (collector layer) 16 is formed. At this time, it is formed under the condition that the growth rate in the <111> B direction is almost the same as or slightly smaller than the growth rate in the <001> direction. For example, using TEGa, As ₄ gas, T
The condition of s = 580 ° C. is used. This gives <111>
The film thickness on the slopes 15b and 15c having the B-plane orientation is about 400.
nm, and the film thickness on the plane portion 15a having the <001> plane orientation is about 600 nm. n ⁺ -GaAs layer (second subcollector layer) 15 and n-GaAs layer (collector layer)
16 constitutes the first compound semiconductor layer.

Next, as shown in FIGS. 3 (a) and 3 (b),
Using a Ga molecular beam, an As molecular beam and a Be molecular beam as a p-type dopant, the Be concentration is 4 × 10 ¹⁹ cm ^−3.
Forming a p-GaAs layer (base layer; second compound semiconductor layer) 17 having At this time, it is formed under the condition that the growth rate in the <111> B direction is lower than the growth rate in the <001> direction. For example, TMGa, As
_{Using 4} gases, the conditions of Ts = 580 ° C. and V / III ratio <1 are used. Thereby, the slope portion of the n-GaAs layer 16
16b, 16c The intrinsic base layers 17b, 17c having a film thickness of about 70 nm in the <111> B direction are the plane portions 16a of the n-GaAs layer 16.
External base layer 17a having a film thickness of about 150 nm in the <001> direction
Is formed.

By appropriately selecting the growth conditions,
The impurity concentration in the base layer grown in the <001> direction is set to <
It can be made higher than the impurity concentration in the base layer grown in the 111> B direction. Therefore, the base layer 17 of the slope portion
For the carrier concentration of about 4 × 10 ¹⁹ cm ⁻³ for b and 17c, the carrier concentration of the base layer 17a in the flat portion is 1 × 10 ²⁰ to
It can be increased to about ²¹ cm ⁻³ , and the base resistance can be further reduced.

Then, Al molecular beam, Ga molecular beam, A
Using the molecular beam of s and the molecular beam of Si as an n-type dopant, the layer 18 including the three compound semiconductor layers 18a, 18b, and 18c is formed. At this time, it is formed under the condition that the growth rate in the <111> B direction is almost the same as or slightly smaller than the growth rate in the <001> direction. For example, T
MAAl (trimethylamine alane), TEGa, As
Using H ₃ and Si ₂ H ₆ gases, Ts = 580 ° C. and V
The condition of / III ratio = 20 is used. As a result, the first layer has a Si concentration of 3 × 10 ¹⁷ cm ⁻³ and slopes 15b and 15c <11.
Al composition ratio having a film thickness of about 30 nm in the 1> B direction of 0.
The n-AlGaAs layer 18a of No. 3 has a Si concentration of 3 in the second layer.
An n-AlGaAs layer having a thickness of about 10 nm at 10 ¹⁷ cm ^-3 , slopes 15b and 15c in the <111> B direction, and an Al composition ratio gradually decreasing from 0.3 to 0, and a Si concentration following this layer. An n-AlGaAs layer / n-GaAs layer 18b composed of an n-GaAs layer having a thickness of 3 × 10 ¹⁷ cm ⁻³ and a thickness of about 100 nm in the inclined surface portions 15b and 15c <111> B is formed as the third layer. Si concentration 5 × 10 ¹⁸ cm ^-3 , slopes 15b, 15c <1
N ⁺ -Ga having a film thickness of about 100 nm in the 11> B direction
As layers 18c are respectively formed.

Next, the In molecular beam, Ga molecular beam, As
And the molecular beam of Si as an n-type dopant
Use, Si concentration 5 × 10¹⁹cm^-3, Film thickness about 100nm
N with⁺-GaAs layer (emitter contact layer) 1
9 is formed. At this time, n ⁺-Above the GaAs layer 19
A tip is formed at the tip. The overall cross-sectional shape is triangular
Become.

Next, as shown in FIG. 4A, a resist film or a polyimide film (etching resistant film) 20 is formed by spin coating. At this time, the resist film or the polyimide film 20 is formed so that the top of the n ⁺ -GaAs layer 19 is projected. Next, as shown in FIG.
Using a mixed solution of H ₃ PO ₄ + H ₂ O ₂ + H ₂ O and using the etching resistant film 20 as a mask, the n ⁺ -GaAs layer 1
The nine and three compound semiconductor layers 18 are etched and removed. As a result, p-GaAs above the trapezoidal flat portion 16a is formed.
The layer 17a is exposed. N layers and n remaining on the slopes 16b and 16c
⁺ Layer is emitter layer 18d, 18e and emitter contact layer
19a and 19b. The emitter layers 18d and 18e and the emitter contact layers 19a and 19b form a third compound semiconductor layer.

Next, as shown in FIG. 4C, AuBe or Ti / P is used with the etching resistant film 20 as a mask.
After depositing the conductive film 21 made of t / Au or the like, the etching resistant film 20 is removed. Lift off p-GaA
A base electrode 21a is selectively formed on the s layer 17a. Next, as shown in FIG. 5A, a film thickness of 100 to 20 is formed on the entire surface.
An insulating film 22 such as a 0 nm polyimide film or a SiO ₂ film or a SiON film is formed.

Next, as shown in FIG. 5B, a resist film 23 is formed on the insulating film 22 above the trapezoidal flat surface portion 16a and in the region where the collector electrode is to be formed, and then T is formed on the entire surface.
Conductive film 2 made of i / Pt / Au and having a total film thickness of 100 nm
4 is formed. Next, the resist film 23 is lifted off.
The upper metal film 24 is removed, and the emitter electrode 24 is connected to the emitter contact layers 19a and 19b on the slope portions 16b and 16c.
a and 24b are formed.

Next, as shown in FIG. 5C, an insulating film 25 made of SiO ₂ or the like is formed on the entire surface. Then, the insulating film 1 on the subcollector layer 12 on both sides of the transistor
After forming openings 26a and 26b in 3 and 25, collector electrodes 27a and 27b connected to the sub-collector layer 12 are formed.
This completes the HBT. In the HBT produced as described above, the collector layers 16b, 16
Intrinsic base layers 17b and 17c having a small film thickness and low carrier concentration are formed on c, and the emitter layers 18d and 18e and the emitter contact layers 19a and 19c are formed on the intrinsic base layers 17b and 17c.
19b is formed, and the slope portion becomes the main portion of the transistor.

The collector current flows vertically through this slope,
If the emitter is grounded, the collector current is 26
a, 26b / sub-collector layer 12, 15 / collector layer 16
/ Intrinsic base layers 17b, 17c / emitter layers 18d, 18e / emitter electrodes 24a, 24b. On the other hand, the external base layer 17a having a large film thickness and a high carrier concentration is formed on the flat collector layer 16a.
A base electrode 21a is formed on the top. In the case of grounded emitter, the main base current is the base electrode 21a / external base layer
17a / intrinsic base layer 17b, 17c / emitter layer 18d, 18e
/ Emitter electrodes 24a and 24b flow.

As described above, according to the first embodiment of the present invention, by utilizing the crystal plane anisotropy of growth, on the collector layer 16 having the <111> B plane orientation and the <001> plane orientation. Since the base layer is formed on the substrate, the external base layer 17a having a thick portion in the <111> B direction and the intrinsic base layers 17b and 17c having a thin portion in the <001> direction are simultaneously formed. can do.

The external base layer having such a large film thickness
By forming the base electrode 21a on 17a, the resistance of the external base layer 17a can be reduced, and thus the overall base resistance can be reduced. Further, since the crystal plane anisotropy of the carrier concentration can be utilized to selectively increase the carrier concentration of the external base layer 17a having the <111> B plane orientation, the base resistance can be further reduced. .

Further, the collector layer 16 and the emitter layer 18d / constituting the transistor including the base layers 17a to 17c.
19a and 18e / 19b are continuously formed without interposing other steps such as surface treatment and ion implantation. Therefore, it is possible to prevent external contamination and introduction of damage to the semiconductor layer during film formation. Further, since the top of the emitter contact layer 19 is formed and the resist film 20 is formed so that this top projects, the patterning of the resist film 20 is unnecessary.

The crystal plane orientation of the slope portion is <111> B.
Although the crystal layer having the crystal orientation is grown, it is possible to form the crystal layer having the crystal plane orientation of the slope portion in the <311> A direction by setting Ts <550 ° C. In this case, the base layer of the inclined surface portion also has a plane orientation of <311> A direction. Thereby, Be doped in the base layer can be prevented from migrating to the emitter layer or the collector layer due to the electric field and the current applied during the operation of the transistor, and the characteristic variation due to the concentration decrease of the base layer can be prevented. be able to.

In the above, the crystal plane orientation is <111> B.
Although the directions are specified as the <001> direction, the first embodiment is also effective for the crystal plane orientation equivalent to this. For example, as an example of the crystal plane orientation equivalent to the <001> direction, <
There is a 100> direction. (2) Description of Configuration of HBT According to Second Embodiment of the Present Invention FIGS. 6A to 6C and FIG. 7 are main parts of a method for manufacturing an HBT according to a second embodiment of the present invention. It is sectional drawing shown about a process.

As shown in FIG. 6A after FIG. 4A, when the emitter contact layer 19 and the emitter layer 18 are etched, the emitter layer 18 is not removed and the base layer of the trapezoidal flat portion 16a is removed. A thin layer 18f is left on 17a.
Next, as shown in FIG. 6B, the etching resistant film 2
An AuBe film 21 is deposited on the entire surface using 0 as a mask, and a conductive film 21a is formed on the thin layer 18f.

Next, as shown in FIG. 6C, after the etching resistant film 20 is removed, a heat treatment is performed. As a result, the conductive film 21a penetrates the thin layer 18f, and the base layer
It is connected to 17a. Then, the HBT shown in FIG. 7 is created through the same steps as those in FIGS.

As described above, in the HBT produced as described above, not only the intrinsic base layers 17b and 17c are covered with the emitter layers 18d and 18e, but also the external base layer 17a is formed by the thin layer 18f. It is covered. Therefore, this coating layer 18f functions as a guard ring, and H
It is possible to improve the characteristics and reliability of BT. (3) Description of Configuration of HBT according to Third Embodiment of Present Invention Next, a configuration of an HBT according to the third embodiment will be described with reference to FIG. FIG. 8 is a sectional view and an equivalent circuit diagram of the HBT.

The difference from the HBT described in the first and second embodiments is that, as shown in FIG. 8, a semi-insulating GaA is used.
the emitter contact layers 12 and 15 on the s substrate 11 side,
The emitter layer 16 is formed, the intrinsic base layers 17f and 17g are formed on the sloped emitter layer 16, and the external base layers 17d and 17e are formed on the planar emitter layer 16.
Collector layers 18g, 18h on the emitter layer 16 on the sloped surface,
That is, the subcollector layers 19c and 19d are formed.

Further, the planar external base layers 17d and 17e are separated into two, and the base electrodes 21b and 21c are formed on the external base layers 17d and 17e, respectively.
The other reference numerals 24c and 24d are collector electrodes, and 26c and 26d.
Is an emitter electrode connected to the emitter contact layer 12 through the openings 27c and 27d. According to the third embodiment, as shown in the lower diagram of FIG. 8, the bases B1 and B2 and the collectors C1 and C2 are separated, and two npn transistors having the emitter E in common are connected in parallel. A differential amplifier can be created. In this case, both transistors can be formed in close proximity to each other, which reduces the manufacturing variation of the two transistors.
A pair of transistors with uniform characteristics can be manufactured. (4) Description of Configuration of HBT According to Fourth Embodiment of Present Invention FIG. 9 is a sectional view showing a configuration of an HBT according to a fourth embodiment of the present invention. FIG. 10 shows an opening 34 using the selective growth mask 33 as a mask in the above HBT forming process.
3 is a perspective view showing a state after a second subcollector layer 35 is selectively formed on the first subcollector layer 32 at the bottom of FIG.

The difference from the first to third embodiments is that
The 01 (-1)> direction is the longitudinal direction. Therefore, when the second sub-collector layer 35 is formed by utilizing the crystal plane anisotropy of growth, a platform having a <001> plane orientation in a plane portion and a <111> A plane orientation in a slope portion is used. It becomes a shape. Therefore, when the base layer is formed on the base layer 37a by utilizing the crystal plane anisotropy of the growth, the base layer 37a having a small thickness in the flat surface portion and the base layers 37b and 37c having a large thickness in the slope portion are formed. To be done.

In the figure, the other reference numeral 31 is semi-insulating GaAs.
The first sub-collector layer 32 is formed on the substrate. 40a and 40b are base electrodes formed on the base layers 37b and 37c of the inclined surface portion, 41 is an emitter electrode formed on the emitter contact layer 39, 42 is a covering insulating film, and 44a and 44b are openings 43a and 43b. It is a collector electrode connected to the sub-collector layer 32 through.

In this case, the base layer 37a in the plane portion is the intrinsic base layer, the base layers 37b and 37c in the slope portion are external base layers, and the emitter layer 38 is formed on the base layer 37a in the plane portion.
And by forming the emitter contact layer 39,
It is possible to obtain the same action and effect as those of the first to third embodiments. Also in the fourth embodiment, it is possible to form the collector layer on the upper side and the emitter layer on the semi-insulating GaAs substrate side as in the third embodiment.

Further, in this case, by separating the collector layer in the plane portion, the base layer and the collector layer are separated as in the third embodiment, and the differential amplifier is composed of two transistors having a common emitter. Can be created.

[0048]

As described above, in the semiconductor device of the present invention, the trapezoidal slope portion has a thinner film thickness than the flat surface portion on the first compound semiconductor layer of one conductivity type having a trapezoidal cross section. The second compound semiconductor layer of opposite conductivity type is provided, and the third compound semiconductor layer of one conductivity type is provided on the second compound semiconductor layer of the inclined surface portion.

In order to form such a multi-layered compound semiconductor layer, in the semiconductor device manufacturing method of the present invention, the <111> B plane orientation and <111> B plane orientation are utilized by utilizing the crystal plane anisotropy of growth.
Second on the first compound semiconductor layer having a 100> plane orientation
A second compound semiconductor layer having a thick portion in the <100> direction, and a <111> B
And a second compound semiconductor layer having a thin portion in the direction.

In this case, by using the second compound semiconductor layer as the base layer, it is possible to simultaneously form the intrinsic base layer on the inclined surface portion and the external base layer on the flat surface portion. Also,
Since the external base layer has a large film thickness, the resistance of the external base layer can be reduced, and thus the overall base resistance can be reduced. In addition, the crystal plane anisotropy of growth on the trapezoidal first compound semiconductor layer having the <111> A plane orientation in the slope portion and the <100> plane orientation in the plane portion is utilized to obtain the second orientation. When the compound semiconductor layer is formed, the film thickness at the slope and the plane is opposite to the above case, and the second compound semiconductor layer having a larger thickness at the slope is formed at the same time than the plane. be able to. In this case, conversely to the above, the second compound semiconductor layer in the sloped portion serves as the external base layer, and the second compound semiconductor layer in the planar portion serves as the intrinsic base layer, reducing the overall base resistance in the same manner as above. can do.

Furthermore, by using the method for manufacturing a semiconductor device of the present invention, the first to third compound semiconductor layers forming a transistor are continuously formed without introducing other steps such as surface treatment and ion implantation. can do. Therefore,
It is possible to prevent external contamination and introduction of damage to the semiconductor layer during film formation.

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing a method for manufacturing an HBT according to a first embodiment of the present invention.

FIG. 2 is a perspective view (No. 2) showing the method for manufacturing the HBT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view (3) showing the method for manufacturing the HBT according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view (4) showing the method for manufacturing the HBT according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view (5) showing the method for manufacturing the HBT according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view (No. 1) showing the method for manufacturing the HBT according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view (No. 2) showing the method for manufacturing the HBT according to the second embodiment of the present invention.

FIG. 8 is a sectional view and an equivalent circuit diagram showing the configuration of an HBT according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing the structure of an HBT according to a fourth embodiment of the present invention.

FIG. 10 is a perspective view showing a condition of a manufacturing process of the HBT according to the fourth embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a configuration of an HBT according to a conventional example.

[Explanation of symbols]

11,31 GaAs substrate, 12,32 first subcollector layer (emitter contact layer), 13,33 selective growth mask, 14,26a, 26b, 34,43a, 43b opening, 15,35 second subcollector layer (Emitter contact layer), 15a, 16a Plane part, 15b, 15c, 16b, 16c Slope surface part, 16,36 Collector layer (emitter layer), 17 Base layer, 17a, 37a Intrinsic base layer, 17b, 17c, 37b, 37c External base layer, 18, 18d, 18e, 38 Emitter layer (collector layer), 18a n-AlGaAs layer, 18b n-AlGaAs layer / n-GaAs layer, 18c n ⁺ -GaAs layer, 18f coating layer (thin layer), 18g, 18h collector layer, 19, 19a, 19b, 39 emitter contact layer (subcollector layer), 19c, 19d subcollector layer, 20 etching resistant film, 21, 24 WSi film, 21a, 40a, 40b base electrode, 22,25 SiO ₂ film, 23 resist film, 24a, 24b, 41 emitter electrode, 27a, 27b, 44a, 44b collector electrode, 44 coating insulating film.

Claims (15)

[Claims] 1. A first compound semiconductor layer of one conductivity type having a trapezoidal cross section, and a film formed on the first compound semiconductor layer and having a trapezoidal slope portion having a thinner film thickness than a plane portion. A second compound semiconductor layer of opposite conductivity type, a third compound semiconductor layer of one conductivity type formed on the second compound semiconductor layer of the trapezoidal slope portion, and the second portion of the planar portion. Heterojunction bipolar transistor having a compound semiconductor layer and an electrode connected thereto. 2. The heterojunction bipolar transistor according to claim 1, wherein the second compound semiconductor layer has a higher carrier concentration in the flat portion of the trapezoid than in the inclined portion. 3. The heterojunction bipolar transistor according to claim 1, wherein the second compound semiconductor layer is separated into right and left sides by the trapezoidal plane portion. 4. A first compound semiconductor layer of one conductivity type having a trapezoidal cross section, and a film formed on the first compound semiconductor layer and having a trapezoidal flat portion having a thinner film thickness than an inclined surface portion. A second compound semiconductor layer of opposite conductivity type, a third compound semiconductor layer of one conductivity type formed on the second compound semiconductor layer of the trapezoidal plane portion, and the second compound semiconductor layer of the inclined surface portion. Heterojunction bipolar transistor having a compound semiconductor layer and an electrode connected thereto. 5. The heterojunction bipolar transistor according to claim 4, wherein the second compound semiconductor layer has a higher carrier concentration in the sloped portion of the trapezoid than in the flat portion. 6. The second compound semiconductor layer and the third compound semiconductor layer
6. The heterojunction bipolar transistor according to claim 4, wherein the compound semiconductor layer is separated into right and left at the trapezoidal plane portion. 7. The first compound semiconductor layer is a collector layer or an emitter layer, the second compound semiconductor layer is a base layer, and the third compound semiconductor layer is an emitter layer or a collector layer. The heterojunction bipolar transistor according to any one of claims 1 to 6. 8. A step of forming a selective growth mask on a substrate of one conductivity type and a step of one conductivity type of trapezoidal cross section utilizing the growth anisotropy based on the crystal plane orientation by the selective growth mask. Forming a compound semiconductor layer on the substrate, and utilizing the anisotropy of growth based on the crystal plane orientation on the first compound semiconductor layer, the trapezoidal slope has a flat film thickness. Forming a second compound semiconductor layer of opposite conductivity type that is thinner than the film thickness of, and forming a third compound semiconductor layer of opposite conductivity type on the second compound semiconductor layer, A step of selectively etching the third compound semiconductor layer in the plane portion to expose the second compound semiconductor layer; and a third step left on the exposed second compound semiconductor layer and on the slope portion. And forming electrodes on the compound semiconductor layer of Method of manufacturing a heterojunction bipolar transistor according to claim Rukoto. 9. The third compound semiconductor layer having a top portion is formed, an etching resistant film is formed so that the top portion protrudes, and the third compound semiconductor layer is selectively formed from the protruding top portion. 9. The method for manufacturing a heterojunction bipolar transistor according to claim 8, wherein the second compound semiconductor layer is exposed by etching. 10. The third compound semiconductor layer is selectively etched to expose the second compound semiconductor layer,
Instead of forming an electrode on the second compound semiconductor layer, the third compound semiconductor layer is selectively etched,
After leaving a thin layer on the second compound semiconductor layer and forming the electrode on the remaining third compound semiconductor layer, the electrode may be penetrated by heating to be connected to the second compound semiconductor layer. The method for manufacturing a heterojunction bipolar transistor according to claim 8 or 9, characterized in that. 11. The crystal plane orientation of the substrate is <100>
Direction or a direction equivalent to the <100> direction, and the crystal plane orientation of the trapezoidal slope portion has a <111> B direction or a direction equivalent to the <111> B direction. The heterojunction bipolar transistor according to any one of claims 8 to 10. 12. The crystal plane orientation of the substrate has a <100> direction or a direction equivalent to the <100> direction, and the crystal plane orientation of the inclined surface portion has a <311> A direction. 11. The heterojunction bipolar transistor according to claim 8, wherein the impurity imparting the other conductivity type to the compound semiconductor layer is beryllium. 13. A step of forming a selective growth mask on a substrate of one conductivity type, and a step of forming a first conductivity type mask having a trapezoidal cross section by utilizing anisotropy of growth based on a crystal plane orientation by the selective growth mask. A step of forming a compound semiconductor layer of No. 1 on the substrate; and utilizing the anisotropy of growth based on the crystal plane orientation on the first compound semiconductor layer, the film thickness of the trapezoidal slope portion is Forming a second compound semiconductor layer of opposite conductivity type that is thinner than the film thickness; forming a third compound semiconductor layer of opposite conductivity type on the second compound semiconductor layer; A step of forming an electrode on the third compound semiconductor layer of the flat surface portion, and selectively removing the third compound semiconductor layer of the inclined surface portion,
A method of manufacturing a heterojunction bipolar transistor, comprising: exposing the second compound semiconductor layer; and forming an electrode on the exposed second compound semiconductor layer. 14. The step of forming an electrode on the third compound semiconductor layer of the flat surface portion comprises forming an etching resistant film so as to expose the flat surface portion of the third compound semiconductor layer, and exposing the exposed portion. 14. The method of manufacturing a heterojunction bipolar transistor according to claim 13, comprising the step of forming an electrode on the flat surface portion of the third compound semiconductor layer and removing the etching resistant film. 15. The crystal plane orientation of the substrate is <100>.
Direction or a direction equivalent to the <100> direction, and the crystal plane of the trapezoidal slope portion has a <111> A direction or a direction equivalent to the <111> A direction. 15. The method for manufacturing a heterojunction bipolar transistor according to claim 10, claim 13, or claim 14.