JP2615657B2 - Heterojunction bipolar transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a heterojunction bipolar transistor.

[Summary of the Invention]

The present invention relates to a heterojunction bipolar transistor having an emitter region, a base region and a collector region,
A band-shaped semiconductor layer forming an emitter region or a collector region intersects a band-shaped semiconductor layer forming a base region thereon, and a collector region or an emitter region is formed on the crossed region, and the crossed region is defined as an intrinsic region. By forming the external base region in a portion other than the intersection region of the base region, the area of the intrinsic region does not fluctuate even when there is a mask overlay error at the time of manufacturing, and the parasitic capacitance is small and the speed is excellent. Thus, a micro transistor is obtained.

[Conventional technology]

Heterojunction bipolar transistors are transistors that can overcome the disadvantages of homojunction bipolar transistors such as silicon. Emitter (E)
Taking an example of a heterojunction bipolar transistor using AlGaAs and GaAs as the base (B) and collector (C), the points that are excellent in principle are as follows. Holes, which are majority carriers in the base, cannot diffuse into the emitter due to the energy barrier of the band gap difference (ΔEg) between the emitter and the base, the base current decreases, and the electron from the emitter to the base decreases. Injection efficiency increases. Therefore, even if the base concentration is increased and the emitter concentration is decreased, the amplification degree (β = I _C / I _B ) can be increased. This means that the base resistance and the emitter-base junction capacitance related to high-speed operation can be reduced. It is theoretically and experimentally shown that the speed is higher than that of the silicon bipolar element.

FIG. 9 shows the structure of a planar heterojunction bipolar transistor utilizing an ion implantation technique and a metal embedding technique. An example of a method for manufacturing a transistor having this structure will be briefly described.

On a semi-insulating GaAs substrate (1), an n ⁺ -GaAs layer serving as a collector electrode extraction layer (2) and an n serving as a collector region (3) are sequentially formed.
A GaAs layer, a p-GaAs layer serving as a base region (that is, an intrinsic base region) (4), and N-AlGaAs serving as an emitter region (5).
After epitaxially growing the n-GaAs layer serving as the layer and the cap layer (6), first, the n ⁺ -Ga layer is left so as to leave the emitter region.
After removing the cap layer (6) of As by etching and injecting Mg using SiO ₂ as a mask, an external base region (7) is formed by annealing. Next, an element isolation region (8) and a base / collector isolation region (9) are formed by ion implantation of boron or H ⁺ . Next, a so-called emitter-top heterostructure is formed by opening a window in the SiO ₂ layer (10) in the collector electrode formation region, forming a trench (groove) (11), and embedding a metal (12) in the trench (11). A junction bipolar transistor (13) is manufactured. (14) is the base electrode,
(15) is an emitter electrode, and (16) is a collector electrode.

On the other hand, a so-called collector-top type heterojunction bipolar transistor (17) having a collector region on the surface side as shown in FIG. 10 has also been considered. The procedure for fabricating this collector-top type heterojunction bipolar transistor is almost the same as that of the ninth embodiment except that the order of epitaxy is changed.
This is the same as the emitter-top type heterojunction bipolar transistor (13) in the figure. In FIG. 10, portions corresponding to those in FIG. 9 are denoted by the same reference numerals, (18) is an n ⁺ -GaAs layer serving as an emitter electrode extraction layer, (5) is an N-AlGaAs layer serving as an emitter region, and (4) ) Is n-GaAs to be the collector region
Layer, (19) an n ⁺ -GaAs layer serving as a collector cap layer,
(7) is an external base area.

Generally, it is considered that the collector-top type heterojunction bipolar transistor has higher speed than the emitter-top type heterojunction bipolar transistor. The reason is as follows. Since the collector area is small, the junction capacitance between the collector and the base is small. One of the factors limiting the high-speed operation of the heterojunction bipolar transistor when the injection level is high is the collector capacitance, which is a great advantage. On the other hand, since the emitter area increases, the emitter-base junction capacitance also increases. This is a disadvantage. However, between the emitter and the base is a hetero junction, which is smaller than a homo junction. Also, since the emitter concentration is low, the emitter junction capacitance can be originally reduced,
Not a big problem. The advantages due to the reduced collector capacitance are much greater, and the published simulations show that contact-top heterojunction bipolar transistors are faster.

[Problems to be solved by the invention]

The disadvantages of the conventional heterojunction bipolar transistor shown in FIGS. 9 and 10 are as follows.

(I) The external base region is formed by ion implantation of Mg into the N-AlGaAs layer or the N-GaAs layer and annealing. Since these layers have a low carrier concentration, high-concentration Mg implantation (~
10 ¹⁹ or more) and annealing causes lateral diffusion and the area of the intrinsic region becomes unstable.

(Ii) The activation rate of Mg for activating the N-AlGaAs ion implantation layer is poor, and the recovery of the crystal is also poor. Therefore, a large number of recombination centers of electrons and holes are formed, and a large amount of reactive current flows through the base, which significantly lowers the current amplification factor. In the technology up to 1987, the emitter width in the intrinsic region is 2.5 μm. If the width is reduced to less than 2.5 μm, the characteristics are significantly deteriorated.

(Iii) On the other hand, assuming that the above-described structure can be formed as in lithography assuming that the technical level has been improved, let's calculate a little how much unnecessary capacitance the small heterojunction bipolar transistor has. As the area of the device decreases, the capacitance of the periphery of the active region, ie, between the emitter and the external base and between the collector and the external base, increases. For example, in the collector top type structure shown in FIG. 10, the collector area is 1 × 1
μm ² and 0.4 μm depletion layer thickness
The capacity between bases is (Where w is the area and d is the width). On the other hand, the area around the intrinsic region, that is, the area constituting the external parasitic collector capacitance is 4 planes × 1 μm × 0.5 μm = 2 μm ² = 2 × 1
0 ^-8 cm ² , which is twice the area of the intrinsic region, and the external parasitic collector capacitance Cbc 'is twice as large as the capacitance Cbc of the intrinsic region.

By the way, in order to eliminate the above-mentioned two drawbacks (difficulty in miniaturization, parasitic capacitance), the present applicant has firstly developed a novel structure in which the external base region, the intrinsic base region and the collector region are formed by independent epitaxy. Heterojunction bipolar transistor was proposed. FIGS. 7A and 7B show the basic structure of this heterojunction bipolar transistor. The manufacturing process of this transistor will be briefly described with reference to FIG. 8. First, an N-AlGaAs layer serving as an emitter region is epitaxially grown on a semi-insulating GaAs substrate (21), and a silicon nitride (SiN) layer (23) is formed. The N-AlGaAs layer is selectively etched using the mask as a mask to form an emitter region (22E) (the eighth region).
Figure A). Next, using the silicon nitride layer (23) as a selection mask, a p ⁺ -GaAs layer (24) serving as an external base region is selectively epitaxially grown to the same height as the silicon nitride layer (23) (FIG. 8B). Next, the silicon nitride layer (23) is removed,
A p ⁺ -GaAs layer (25) serving as an intrinsic base region and an n-GaAs layer (26) serving as a collector region are sequentially epitaxially grown (FIG. 8C). Next, the n-GaAs layer (26) and the p ⁺ -Ga
The As layers (25) and (24) are selectively removed by etching. As a result, an external base region (24b) is formed (FIG. 8D). Next, the n-GaAs layer (2) on the external base region (24b)
6) is selectively etched away and the external base region (24
The surface of b) is exposed, and a collector region (26C) and an intrinsic base region (25B) are formed (FIG. 8E). Next, after forming a base electrode (27) and an emitter electrode (28), a silicon oxide (SiO ₂ ) layer (30) is formed, flattened, and a collector electrode (29) is formed (FIG. 8). F).
In the heterojunction bipolar transistor (31), an intrinsic base region (24B) and a collector region (26C) are created by the last epitaxial growth, and since the ion implantation or thermal process has not been performed thereafter, the destruction of the intrinsic region is prevented. I have. Further, as can be seen from FIGS. 7A and 7B, the external parasitic capacitance is significantly reduced.

However, a drawback of this transistor (31) is that the area of the intrinsic region is not determined by the window of one mask as in the prior art, but by the overlapping region of two mask patterns. For example, the intrinsic emitter region is formed by an overlapping portion of the mask of FIG. 8A and the mask of FIG. 8D, and the collector region (26C) is formed by the mask of FIG. 8D and the mask of FIG. Is formed by the overlap with the mask in the step (2). According to this manufacturing method, a small area can be formed as an advantage, but a pattern overlay error directly becomes an error of the area of the intrinsic area. Currently available technology is 0.
An error of 2 to 0.3 μm may occur. In order to achieve ultra-high speed, it is necessary to reduce the base resistance and the emitter resistance as much as possible. For this purpose, it is necessary to make the electrodes as close as possible to the intrinsic region, that is, to make the electrodes self-aligned, but this is not considered in this manufacturing. .

The present invention has been made in view of the above circumstances, and provides a heterojunction bipolar transistor that is particularly excellent in high-speed operation and that can form a small transistor without causing a change in the area of an intrinsic region.

[Means for solving the problem]

According to the present invention, in a heterojunction bipolar transistor having an emitter region, a base region and a collector region, a band-shaped semiconductor layer forming an emitter region or a band-shaped semiconductor layer forming a collector region and a base region formed thereon are formed. A heterojunction bipolar transistor which crosses a band-shaped semiconductor layer, forms a collector region or an emitter region on the crossing region, sets the crossing region as an intrinsic region, and forms an external base region in a portion other than the crossing region of the base region. Is configured.

In manufacturing, a band-shaped emitter region (or collector region) is formed, and a semiconductor layer serving as an external base region is formed on the band-shaped emitter region (or collector region) by using a selection mask on the band-shaped emitter region (or collector region). After being formed thicker than the thickness, the selection mask is removed and a semiconductor layer serving as an intrinsic base and a semiconductor layer serving as a collector region (or an emitter region) are entirely laminated. Next, the semiconductor layer laminated including the semiconductor layer serving as the external base region is selectively etched so as to intersect with the band-shaped emitter region (or the collector region) and remain in the band shape. Next, after forming a resist layer on the entire surface, the resist layer remains at the intersection region of the band-shaped semiconductor layers, and the semiconductor layer is planarized so that the semiconductor layer is exposed at a portion corresponding to the external base region, and the resist layer is used as a mask. Selective etching so that the surface of the external base region faces,
The collector region (or emitter region) and thus the intrinsic region is formed only on the intersection region.

[Function] The intersection region between the semiconductor layers in both bands becomes the intrinsic region. For this reason, even if the positions of the two masks are displaced during manufacturing, the shape and area of the intersection region do not change. Therefore, for example, when a submicron device is formed, the area of the intrinsic region is reduced due to a mask overlay error. Does not fluctuate.

Since the collector region (or the emitter region) on the intersection region is hardly in contact with the external base region, the collector (or the emitter) capacitance becomes only the capacitance of the intrinsic portion and becomes small. Further, since the emitter region (or the collector region) and the external base region are only in contact on the two side surfaces, the capacitance of the emitter (or the collector) is reduced. Therefore, even if the device area is reduced, the external parasitic capacitance at the peripheral becomes small.

〔Example〕

An embodiment of a collector-top type heterojunction bipolar transistor according to the present invention will be described with reference to FIG.

First, a semi-insulating GaAs substrate as shown in FIG. 1 A ₁ (41)
On top of this, a high-resistance wide band gap layer serving as a barrier layer (42) for the emitter, that is, undoped Al _{0.4 having a} thickness of 0.3 μm.
Ga _0.6 As layer and N-AlGaAs layer to be the emitter region (46)
That is, NA having a thickness of 0.3 μm and an impurity concentration of about 3 × 10 ¹⁸ cm ^−3.
l _0.3 Ga _0.7 As layer (43), thickness 0.05μm, impurity concentration 3 × 1
The N-Al _0.3 Ga _0.7 As layer (44) of about ¹⁷ cm ⁻³ and the N-Alx-Ga
_A gradient composition layer (45) in which the Al composition ratio x of _1- xAs is sequentially changed from 0.3 to 0 is sequentially grown by MOCVD (metal organic chemical vapor deposition). The gradient composition layer (45) has a thickness of 0.03 μm and an impurity concentration of about 3 × 10 ¹⁷ cm ⁻³ , and is formed such that x gradually changes from 0.3 to 0 from below to above. Further, a silicon nitride (SiN) layer (47) is laminated on the gradient composition layer (45) by a CVD (chemical vapor deposition) method.

Then, after the selective etching Figure 1 B _1, B ₂ and the silicon nitride layer as shown in B ₃ (47) to leave a portion corresponding to the emitter region, the remaining silicon nitride layer (47) Mask The N-AlGaAs layer (46) is selectively etched by wet etching so as to leave the N-AlGaAs layer (46) in a band shape.
Form E). The graded composition layer (45) is for increasing the injection current from the emitter.

Next, an impurity concentration of 5 × serving as an external base region as a selective mask silicon nitride layer (47) as shown in FIG. 1 C ₁
A p ⁺ -GaAs layer (48) of about 10 ¹⁹ cm ^{-3 is} selectively grown to a thickness of 1.0 μm. That is, the p ⁺ -GaAs layer (48) is
It is formed thicker than the thickness of E). The growth temperature at this time is 7
The temperature was set to 00 ° C., and DMZn (ヂ methylzinc) was used as a p-type impurity.

Then, thickness of 0.03μm which as shown in FIG. 1 D ₁ and D ₂ is removed silicon nitride layer (47), an intrinsic base region,
A p ⁺ -GaAs layer (49) with an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ , a thickness of 0.3 μm serving as a collector region, an n-GaAs layer (50) with an impurity concentration of about 10 ¹⁷ cm ⁻³ and a thickness of 0.1 μm , Impurities about 10 ¹⁹ c
An n ⁺ -GaAs layer (51) of about m ⁻³ is sequentially grown. And n ⁺
-Electrode metal (5) made of AuGe / Ni / Au on the GaAs layer (51).
2) Evaporate. The n ⁺ -GaAs layer (51) is for facilitating the formation of an ohmic electrode.

Next, as shown in FIG. 1 E ₁ and E ₂ , a resist layer (53)
The band-shaped emitter region (46) formed by the first epitaxy by RIE (Reactive Ion Etching) using
The electrode metal (52) and the n ⁺ -GaAs layer (5
1), n-GaAs layer (50) and p ⁺ -GaAs layer (49), (48)
Is selectively etched and left in a strip shape. At this time, N-GaAs
The emitter region (46E) remains as it is because the etching selectivity with GaAs is large. Fig. 1 for easy understanding
It shows a three-dimensional view to E _3. As a result, a band-like base region (48b) of p ⁺ -GaAs is formed.

Then, as it is to the silicon oxide resist layer (53) used as a mask for RIE as shown to FIG. 1 F ₁ (Si
O ₂ ) layer is laminated 0.2 μm, and the emitter region (46
A side wall (54) made of silicon oxide is formed on the side wall of the GaAs band orthogonal to E). An AuGe / Ni / Au metal is vapor-deposited thereon, and an emitter electrode (55) is formed in a self-aligned manner on the N-AlGaAs emitter region (46E).

Next, the resist layer on the strip portion of the GaAs, as shown in FIG. 1 G ₁ and G ₂ (53) and the silicon oxide sidewall portion (54) is removed and deposited again formed resist layer (56). Next is the RI of O ₂
E, AuGe / Ni / Au electrode metal (5
The n-GaAs layer (50) with 2) is exposed. Then N
-N-GaAs layer (50) on AlGaAs emitter region (46E)
Is low covered with the resist layer (56).

Next, AuGe / Ni surface as shown in FIG. 1 H _1, H ₂ and H ₃
The / Au electrode metal (52) is removed by wet etching, and the n ⁺ -GaAs layer (51) and the n-GaAs layer (50) are removed by RIE. At this time, the n ⁺ -GaAs layer (51) and the n-GaAs layer (50) on the N-AlGaAs emitter region (46E) serve as a mask with the resist layer (56) and the AuGe / Ni / Au electrode metal (52) as a mask.
Are not etched. The etching amount at this time is set to be substantially the same as the height of the emitter region (46E) of N-AlGaAs (substantially 0.35 μm). As a result, the surface of the p ⁺ -GaAs external base region (48b) of the base region (57) is exposed, and p ⁺ --is added to the intersection region between the band-shaped base region (57) and the band-shaped emitter region (46E). An intrinsic base region (49B) composed of a GaAs layer (49) and an n-GaAs collector region (5
0C) is formed. Thereafter, the resist layer (56) is removed by O ₂ RIE.

Next, as shown in FIG. ₁ , I ₁ , I ₂ and I ₃ , silicon oxide (S
iO ₂ ) layer (58) is stacked at a thickness of 1.5 μm and flattened using
Exposing the AuGe / Ni / Au metal or collector electrode (52),
Next, an emitter region (46E) of N-AlGaAs and p ⁺ -GaAs
Window (5) for taking out the electrode to the external base area (48b) of the
Form 9) and (60). Thereafter, the AuGe / Ni / Au emitter electrode (5) is passed through window holes (59) and (60), not shown.
5) Emitter electrode and external base region connected to (48b)
A base electrode for ohmic connection is formed.

Thus, the intended collector top is formed by forming the intrinsic base region (49B) and the collector region (50C) at the intersection of the band-shaped emitter region (48b) and the band-shaped base region (57). Type heterojunction bipolar transistor (61) is obtained.

The collector-top type heterojunction bipolar transistor having such a configuration has the following advantages.

In forming this transistor, there are only two main masks for forming band-shaped semiconductor layers orthogonal to each other. Then, the intersection region becomes an intrinsic region. Therefore 2
Even if the positions of the masks are shifted, the shape and area of the intersecting region are unchanged. Since the band-shaped semiconductor layer can be formed more accurately than in the case of opening a window, the area of the ultimate collector region (50C) of the lithography technique can be formed. For example, with the optical lithography technology of 1987, about 0.8 μm is easy.

The emitter electrode (55) is formed in a self-aligned manner and is formed as close as possible to the intrinsic region. Therefore, the emitter resistance is reduced. In this example, the base electrode that is ohmic-connected to the external base region (48b) is not self-aligned, but the external base region (48b) has an impurity concentration of 5 × 10 ¹⁹ cm ^−3.
If the mobility is 60 cm ² / VS and the thickness is 0.3 μm, the sheet resistance is as low as about 70Ω / □, and the external base resistance does not particularly increase. That is, the base resistance is very small as compared with the case where the external base region is formed by the conventional ion implantation technique. In order to form a self-aligned manner base electrode can be easily formed by using the side wall forming technique after the first FIG H ₁ to H ₂ steps.

Since the collector region (50C) is formed in a mesa shape and the side surface is covered with the silicon oxide layer (58), no collector capacitance occurs at the peripheral, and the collector capacitance includes only the intrinsic collector capacitance. Therefore, the collector capacitance becomes extremely small. The contact between the emitter region (46E) and the external base region (48b) is only on two side surfaces,
The emitter capacitance is also reduced. In this configuration, the emitter-external base and the collector-
Since the capacitance of the peripheral generated between the external bases does not become relatively large and the base resistance and the emitter resistance can be reduced, a heterojunction bipolar transistor excellent in high-speed operation can be obtained.

Emitter region (46E) and external base region (48b) are 2
Since the structure is such that only the sides are in contact, the diffusion of electrons injected from the emitter region (46E) into the intrinsic base region (49B) to the external base region (48b) is small. This means that the electron loss in the peripheral is reduced (that is, the peripheral effect is reduced in principle), and a high current amplification factor can be obtained even in a small active region or in a low current region.

Since the semi-insulating GaAs substrate (41) and an undoped AlGaAs barrier layers of wide bandgap between emitter region (46E) and an external base region (48b) (42) is provided, outside the p ⁺ -GaAs Leakage current through the substrate (41) between the base region (48b) and the N-AlGaAs emitter region (46E) can be prevented. On the side of the emitter region (46E) in contact with the intrinsic base region (49B), N-AlxGa1 _- xAs
By providing the graded composition layer (45), the flow of electrons is improved, and so-called emitter current flows more easily.

On the other hand, in manufacturing, after forming the external base region (48b), the intrinsic base region (49B) is epitaxially grown.
Is formed, the thickness of the intrinsic base region (49B) can be made as thin as possible. In addition, since the intrinsic base region (49B) is formed by the last epitaxial growth, there is no displacement of the junction.

FIG. 3 shows the heterojunction bipolar transistor described above.
FIG. 2 shows one unit cell when integrated as a CML circuit. Two invented heterojunction bipolar transistors (Tr ₁ ) (Tr ₂ ) have a common band emitter (46E)
Are formed at both ends. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals. The load resistance (R) is p ⁺ −
It is formed of a GaAs layer. It is about 350Ω. FIG. 4 shows the symbols of this unit cell. FIG. 5 shows each example of the connection in the case where a gate is formed by this unit cell. NOT circuit (see FIG. 5A), 3-input NOR / OR circuit (see FIG. 5B), 5-input NOR / OR circuit (see FIG. 5C), EX NOR / EX
It can be seen that an OR (see FIG. 5D), an emitter-follower circuit (see FIG. 5E) and the like can be formed extremely easily.
FIG. 6 shows an example of a preferred layout when a three-input NOR / OR gate is used as a unit cell. If it is composed of 1 × 1 μm ² collector, one gate is very small at 25 × 14 μm ² , ~ 2.
8K gate / 1mm ² density.

Although the above example is applied to a collector-top type heterojunction bipolar transistor, it is also possible to configure an emitter-top type heterojunction bipolar transistor (not shown). In this case, the band-shaped collector region and the band-shaped base region intersect, an emitter region is formed on the intersection region, and the intersection region is configured as an intrinsic region.

In the heterojunction bipolar transistor (31) formed by three epitaxies shown in FIG. 8 described above, the collector area was determined by the superposition of three masks in the steps of FIGS. 8A, 8D and 8E. Although the overlay accuracy has improved in recent years, the variation in area cannot be ignored when the overlay dimension becomes submicron. FIG. 2 shows an example of a manufacturing method in which the superposition is performed only once in order to manufacture the structure of the heterojunction bipolar transistor shown in FIG.

First, the up first Figure A ₁ through the same process as D ₁ of the above, as shown in Figure 2 A _1. That is, an undoped Al _0.4 Ga _0.6 As layer (72) having a thickness of 0.3 μm and an N-AlGaAs layer serving as an emitter region (73E) (that is, a thickness of 0.3 μm, an impurity concentration of 3 ×) are formed on a semi-insulating GaAs substrate (71). N-Al _0.3 Ga of about 10 ¹⁸ cm ^-3
_0.7 As layer (74), thickness 0.05μm, impurity concentration 3 × 10 ¹⁷ cm
An N-Al _0.3 Ga _0.7 As layer (75) and a graded composition layer (76) of N-Al x Ga ₁ -x As (about ⁻³ ) are grown by MOCVD. Next, using a silicon nitride layer (not shown) as a mask, an N-AlGaAs layer (73)
Is selectively etched to form an emitter region (73E). Next, using the silicon nitride layer as a selection mask, the p ⁺ -GaAs layer (77) having an impurity concentration of about 5 × 10 ¹⁹ cm ^{−3 serving} as an external base region is made thicker than the emitter region (73E).
Selectively grow with a thickness of 1.0 μm. Next, p ⁺ having a thickness of 0.03 μm to be an intrinsic base region and an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³
A GaAs layer (78), an n-GaAs layer (79) with a thickness of 0.3 μm serving as a collector region, an impurity concentration of about 10 ¹⁷ cm ⁻³ and a thickness of 0.1
An n ⁺ -GaAs layer (80) having a thickness of about μm and an impurity concentration of about 10 ¹⁹ cm ⁻³ is sequentially grown, and an AuGu / Ni / Au electrode metal (81) is further deposited.

Next, as shown in Figure 2 B ₁ and B _2, to cover the portions corresponding to the collector region and the external base region so as to straddle a part of the emitter region (73E) in the resist layer (82) RIE
The electrode metal (81), the n ⁺ -GaAs layer (80), the n-GaAs layer (79), and the p ⁺ -GaAs layers (78) (77) are selectively etched away. As a result, an external base region (77b) is formed.

Next, FIG. 2 C ₁ in the resist layer as shown (82) as it is to to a silicon oxide (SiO ₂₎ layer was 0.2μm laminated, R
A side wall (83) made of silicon oxide is formed on the side wall including the collector region and the base region by IE. AuGe / Ni / Au metal is deposited thereon, and an emitter electrode (84) is formed in a self-aligned manner on the emitter region (73E).

Next, the resist layer (82) and the side wall (8
3) is removed (second reference Figure D _1).

Next, the resist layer as shown in FIG. 2 E ₁ (85) was deposited and formed, by performing some RIE by O ₂ electrode metal (81) on the large external base region of the thickness (77b) Exposed.

Then, RIE after the resist layer as shown in FIG. 2 F ₁ (85) selectively removing the metal electrode (81) as a mask, a resist layer (85) and the electrode metal (81) as a mask
GaAs so that the surface of the external base region (77b) is exposed
Etch the s layer. This allows the collector area (79
C) and an intrinsic base region (80B) are formed.

Next, after removing the resist layer (85), a silicon oxide layer (86) is stacked 1.5 μm thick, and the electrode metal on the collector region (79C), that is, the collector electrode (81) is exposed by flattening. After annealing for 1 minute to form an ohmic electrode, base and emitter electrode windows (87)
And (88) are completed. Thus to obtain a heterojunction bipolar transistor collector-top type of interest shown in FIG. 2 G ₁ (89).

In this process, FIG. 2 A ₁及外portion base region overlapping of the mask for forming the emitter region (73E) (77b)
Is only one overlapping the second two masks of FIG. B ₁ to form a, the area of a self-aligned manner collector region (79C) determined. Therefore, the area of the intrinsic region does not change. The emitter electrode (84) is also formed in a self-aligned manner, and is formed as close as possible to the intrinsic region. Therefore, the emitter resistance is reduced. In addition, the base resistance is reduced, the collector capacitance is reduced only in the intrinsic region, the emitter capacitance is reduced, the periphery effect is reduced, and a high current amplification factor is obtained even when the intrinsic region is reduced. The same effect as that of FIG. 1 is obtained, for example, the thickness of the intrinsic base region can be reduced to the limit. In addition,
Although this configuration has been described for a collector-top type heterojunction bipolar transistor, it can be applied to an emitter-top type heterojunction bipolar transistor. In this case, the collector electrode is formed in a self-aligned manner.

〔The invention's effect〕

According to the present invention, the emitter region (or the collector region)
Are formed so as to intersect the band-shaped semiconductor layer forming the base region and the band-shaped semiconductor layer forming the base region, and to have an intrinsic region in the intersection region. Does not vary.
Further, since the emitter region (or the collector region) and the external base region are in contact only on two sides, the emitter (or the collector) capacitance is reduced. Since the collector region (or the emitter region) is formed on the intersection region and hardly contacts the external base region, the capacitance of the collector (or the emitter) is only the capacitance of the intrinsic region and is extremely small. Thus, the external parasitic capacitance is reduced, and the collector capacitance and the emitter capacitance can be reduced. Since the external base region is formed in a portion other than the intersection region of the external base region, the base resistance can be reduced. Therefore, a fine heterojunction bipolar transistor having excellent high-speed performance and high reliability can be obtained.

Further, for example, when applied to a collector-top type heterojunction bipolar transistor, the emitter region and the external base region have a structure in which only two sides are in contact with each other.
The diffusion of electrons injected from the emitter region into the intrinsic base region into the external base region is reduced. This reduces the loss of electrons in the periphery, so that a high current amplification factor can be obtained even in a small intrinsic region or in a low current region.

[Brief description of the drawings]

FIG. 1 A ₁ -I ₁ is a manufacturing process diagram showing an example of the heterojunction bipolar transistor of the present invention, FIGS. 1 B ₂ and B ₃ are FIG.
Cross-sectional view and y ₁ -y ₁ line of a cross-sectional view of x ₁ -x ₁ line of B _1, first
Figure D ₂ is a cross-sectional view of a first y ₂ -y ₂ line of FIG. D _1, Figure 1 E ₂ and E ₃
Sectional view and a perspective view of a first x ₃ -x ₃ line in FIG. E ₁ is Figure 1 G ₂
The cross-sectional view of the first y ₃ -y ₃ line in FIG. G _1, the Figure 1 H ₂ and H ₃ cross sectional view and a y ₄ -y ₄ line of the first x ₄ -x ₄ line of Fig. H ₁ Figure,
Sectional view of Figure 1 I ₂ and I ₃ are first Figure I ₁ x ₅ -x ₅ lines and y ₅
-Y ₅ line of cross section, process diagrams showing another process example of the heterojunction bipolar transistor according to Fig. 2 A ₁ -C ₁ the present invention, FIG. 2 B ₂ is a plan view of FIG. 2 B _1, the 3 is a schematic layout diagram showing a unit cell when the transistor of the present invention is integrated as a CML circuit, FIG. 4 is a diagram showing a symbol of the unit cell, and FIGS. FIG. 6 is a diagram showing an example of connection when forming a gate, and FIG.
Layout diagram showing unit cells of input NOR / OR gate, FIG.
7A and 7B are a plan view and a sectional view of a heterojunction bipolar transistor for comparison, FIGS. 8A to 8F are manufacturing process diagrams, and FIG. 9 is a diagram of a conventional emitter-top type heterojunction bipolar transistor. FIG. 10 is a sectional view of a conventional collector-top type heterojunction bipolar transistor. (46E) is the emitter region, (48b) is the external base region,
(49B) is the intrinsic base region, (57) is the base region, (50
C) is a collector region, (52) is a collector electrode, and (55) is an emitter electrode.

Claims (1)

(57) [Claims] 1. A heterojunction bipolar transistor having an emitter region, a base region, and a collector region, wherein a band-shaped semiconductor layer forming the emitter region or a band-shaped semiconductor layer forming the collector region, and the base layer formed thereon. The collector region or the emitter region is formed on the intersection region with the band-shaped semiconductor layer forming the region, the intersection region is defined as an intrinsic region, and an external base is formed on a portion of the base region other than the intersection region. A heterojunction bipolar transistor, wherein a region is formed.