JPH0875825A - Test circuit, its test method, and test method using the test circuit - Google Patents

Abstract

PURPOSE: To detect whether of a comparator, which compares a test signal for testing a module with a predicted signal which predicted an output signal of the module, is normally operated or not without need of many outside input/ output terminals for module testing. CONSTITUTION: A signal generator 6 resets an inside counter according to a reset signal supplied from the outside, synchronizes with a first clock signal supplied from the outside to count, and supplies a test signal for testing a module and a predicted signal which predicted a supply signal of the module based on the test signal. A signal delay circuit 8 is synchronized with a second clock signal supplied from the outside, and supplies a module signal supplied by the module and the predicted signal supplied by the signal generator after delaying by a specified time. A comparator 10 supplies a comparison signal after deciding whether a module signal supplied from a signal delay circuit coincides with the predicted signal or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, a test method therefor, and a test method using the test circuit, and more particularly to a logic circuit constructed by a plurality of cells in a semiconductor integrated circuit. A build-in self-test circuit that performs self-diagnosis for the built-in self-test circuit, and a build-in self-test circuit that diagnoses the build-in self-test circuit itself, a test method therefor, and a build-in test. The present invention relates to a test method using a self-test circuit.

In recent years, a logic circuit (hereinafter referred to as "module") constructed by a plurality of cells has been present in a semiconductor integrated circuit (hereinafter referred to as "IC"). As an example of this module, an arithmetic unit (ALU), a sum-of-products unit, etc. are mentioned. As described above, in the process of producing an IC in which a module is built inside, performing a function test or the like on a module built in the IC causes a problem that the higher the integration degree of the IC, the longer the time required for the test. was there. Therefore, with the increase in the degree of integration of ICs, it has been desired to establish a technique that allows the module test to be performed more easily.

[0003]

2. Description of the Related Art Conventionally, when performing a functional test on a module built in a semiconductor integrated circuit, a signal required for the test is input from the outside, and a tester or the like is contacted to output the output signal. Many input / output terminals were required for detection.

FIG. 8 shows the configuration of a conventional product-sum tester. The conventional accumulator tester includes a tester 26 that supplies various signals for the accumulator 21 to perform various calculations, and an accumulator 2.
1 is provided with a tester 27 that outputs calculation results of various calculations. The tester 26 controls the product-sum adder 21 with 17-bit equivalent multiplication data TEST1, 17-bit equivalent multiplied data TEST2, 40-bit equivalent addition data TEST3, and 3-bit equivalent control for controlling the product-adder. Data CTL for supply. The subscript above "/" in the figure indicates the number of signal lines corresponding to the number of bits of the subscript. The tester 27 supplies the operation result data RESULT corresponding to 41 bits from the sum of products unit.

As described above, the conventional accumulator tester has one
An external input / output terminal corresponding to 18 bits (an input terminal corresponding to 77 bits and an output terminal corresponding to 41 bits) was required. Further, according to the conventional accumulator tester, the tester 26
Supplies a signal necessary for the signal processing of the product-sum adder 21, and the product-sum adder 21 supplies the result of the calculation to the tester 27 to perform the functional test of the product-sum adder 21.

[0006]

However, as described above, the conventional product-sum device tester requires a large number of input / output terminals for testing the product-sum device 21, which is not suitable for actual products. There was a problem of not having.

Further, in the conventional product-sum adder test apparatus, a comparator for comparing a test signal for testing the product-sum adder 21 and a prediction signal for predicting the output signal of the module corresponding to the test signal is provided. There was a problem that it was not possible to know whether or not it was operating normally.

Therefore, an object of the present invention is to provide a test circuit, a test method therefor, and a test method using the test circuit, which solve the above problems.

[0009]

In order to solve the above problems, the invention according to claim 1 provides a reset signal supplied from the outside in a test circuit for testing a module built in a semiconductor integrated circuit. A test signal for resetting an internal counter based on the above, counting in synchronization with a first clock signal supplied from the outside, and a test signal for testing the module based on the count, and an output signal of the module corresponding to the test signal. , A signal generator that supplies a prediction signal that predicts, a signal delay circuit that delays and supplies a module signal and a prediction signal supplied by the module for a predetermined time in synchronization with a second clock signal that is externally supplied, And a comparator which supplies a comparison signal by judging whether or not the module signal and the test signal supplied from the delay circuit match each other. That.

According to a second aspect of the present invention, in a test circuit for testing a module built in a semiconductor integrated circuit, an internal counter is reset based on a reset signal supplied from the outside, and the counter is supplied from the outside. A signal generator that counts in synchronization with the first clock signal and supplies a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module corresponding to the test signal, and from the outside In synchronization with the supplied second clock signal, the module signal and the prediction signal supplied from the signal delay circuit coincide with the signal delay circuit that delays the module signal and the prediction signal supplied by the module for a predetermined time. The comparator, which supplies a comparison signal based on whether or not there is an error, and the error generation signal supplied from the outside. And an error generating circuit supplies the converted to an error signal differs from the predicted signal module signal supplied from the delay circuit.

According to a third aspect of the present invention, in a test method for testing a module built in a semiconductor integrated circuit, an internal counter is reset based on a reset signal supplied from the outside, and is supplied from the outside. Counting in synchronization with the first clock signal, supplying a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module corresponding to the test signal, and a step of supplying the prediction signal from the outside. In synchronization with the second clock signal, the step of delaying and supplying the module signal and the prediction signal supplied by the module for a predetermined time, and whether or not the module signal and the test signal supplied from the signal delay circuit match. Determining and supplying a comparison signal.

According to a fourth aspect of the present invention, in the test method for performing the AC characteristic test of the module using the test circuit according to the first aspect, at least the measurement timing is the timing at which the comparison signals match from the mismatched state to the next. Up to the step of changing the phase of the second clock signal, and the step of detecting the phase difference between the first clock signal and the second clock signal at the measurement timing.

According to a fifth aspect of the present invention, in a test circuit test method for testing a module built in a semiconductor integrated circuit, an internal counter is reset based on a reset signal supplied from the outside, and an external counter is reset from the outside. Counting in synchronization with the supplied first clock signal, supplying a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module based on the test signal; A step of delaying and supplying a module signal and a prediction signal supplied by the module for a predetermined time in synchronization with the supplied second clock signal;
The step of supplying a comparison signal by judging whether the module signal and the prediction signal supplied from the signal delay circuit match, and the step of supplying from the signal delay circuit based on the error occurrence signal supplied from the outside. Converting the module signal into an error signal different from the prediction signal and supplying the error signal;
Is provided.

[0014]

According to the first aspect of the invention, the signal generator resets the internal counter on the basis of the reset signal supplied from the outside, and counts in synchronization with the first clock signal supplied from the outside. And a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module corresponding to the test signal. The signal delay circuit delays and supplies the module signal and the prediction signal supplied by the module for a predetermined time in synchronization with the second clock signal supplied from the outside. The comparator determines whether or not the module signal and the test signal supplied from the signal delay circuit match and supplies the comparison signal.

As a result, the comparator can judge whether the module is functioning normally by observing the signal level of the comparison signal obtained by comparing the prediction signal and the module signal. Therefore, the test circuit can perform a functional test of the module without requiring a large number of external input / output terminals.

According to the invention of claim 2, claim 1
In addition to the configuration of the invention described in (1), the error generation circuit converts the module signal supplied from the signal delay circuit into an error signal different from the prediction signal based on the error generation signal supplied from the outside, and supplies the error signal.

As a result, the comparator will compare the prediction signal and the error signal, and as a result of the comparison, the comparison signal which is determined as not matching the prediction signal and the error signal is supplied. Therefore, when the error occurrence signal is supplied from the outside, the comparison signal that is determined that the prediction signal and the error signal do not match if the comparator is normal is supplied.
It is possible to know whether the comparator is functioning normally.

According to the third aspect of the invention, the internal counter is reset based on the reset signal supplied from the outside, the counting is performed in synchronization with the first clock signal supplied from the outside, and the count is performed. A test signal for testing the module based on the above and a prediction signal for predicting the output signal of the module corresponding to the test signal are supplied. In synchronization with the second clock signal supplied from the outside,
The module signal and the prediction signal supplied by the module are delayed by a predetermined time and then supplied. It is determined whether or not the module signal and the test signal supplied from the signal delay circuit match, and the comparison signal is supplied.

As a result, by observing the signal level of the comparison signal obtained by comparing the prediction signal and the module signal, it is possible to judge whether or not the module is functioning normally. Therefore, the test circuit can perform a functional test of the module without requiring a large number of external input / output terminals.

According to the fourth aspect of the present invention, the phase of the second clock signal is changed at least from the state where the comparison signals do not match to the measurement timing when the comparison signals are next matched, and the phase of the second clock signal is changed to the first timing at the measurement timing. The phase difference between the clock signal and the second clock signal is detected.

As a result, the test circuit has the phase of the first clock signal corresponding to the timing when the test signal is supplied to the module and the phase of the second clock signal corresponding to the timing when the module signal is supplied from the module. Will be compared. Therefore, it is possible to know the actual phase difference between the first clock signal and the second clock signal, which corresponds to the processing time of the module, and it is possible to perform an AC characteristic test for measuring the processing time of the module.

According to the fifth aspect of the invention, the internal counter is reset based on the reset signal supplied from the outside, the counting is performed in synchronization with the first clock signal supplied from the outside, and the count is performed. A test signal for testing the module based on the above and a prediction signal for predicting the output signal of the module corresponding to the test signal are supplied. In synchronization with the second clock signal supplied from the outside,
The module signal and the prediction signal supplied by the module are delayed by a predetermined time and then supplied. It is determined whether or not the module signal and the test signal supplied from the signal delay circuit match, and the comparison signal is supplied. The module signal supplied from the signal delay circuit is converted into an error signal different from the prediction signal and supplied based on the error generation signal supplied from the outside.

As a result, the comparator compares the prediction signal and the error signal, and supplies the comparison signal which is judged as the result of the comparison that the prediction signal and the error signal do not match. Therefore, when the error occurrence signal is supplied from the outside, the comparator supplies the comparison signal determined that the prediction signal and the error signal do not match each other, so that it is possible to know whether the comparator is functioning normally. be able to.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. Principle FIG. 1 shows the principle of the present invention.

As shown in FIG. 1, the module test build-in self-test circuit 100 includes a reset input terminal 1, a first clock input terminal 2, a second clock input terminal 3, and an error occurrence signal input terminal. 4, a comparator output terminal 5, a signal generator 6, a signal delay circuit 8, an error generating circuit 9, and a comparator 10.

Reference numeral 7 is a module of the device under test. The module 7 is built in the module test build-in self-test circuit 100. In addition, the module test build-in self-test circuit 10 is actually used.
When operating 0, the reset signal output unit 11 for supplying the reset signal Rst for resetting the counter existing inside the signal generator 6 and the first clock signal C
a first clock signal output section 12 for supplying lk1, and a second clock signal Clk2 having the same cycle as the first clock signal.
A second clock signal output section 13 for supplying the error generation signal Err, an error generation signal output section 14 for supplying the error generation signal Err, and a comparison signal detection section 1 for detecting the signal level of the comparison signal Cmp.
5 and are connected and used.

The signal generator 6 resets the internal counter based on the supplied reset signal Rst, increments the internal counter in synchronization with the supplied first clock signal Clk1, and based on the internal count value. A test signal T having a test pattern for testing the module 7 according to the present invention and a prediction signal E that predicts the output signal of the module 7 based on the test signal T are supplied. The module 7, which is the object of the test, supplies the module signal M based on the test signal T.

For example, if the module 7 is a 2-input 1-output OR circuit having input terminals A and B and an output terminal O, then the signal generator 6 outputs the test signal T as the input terminal A of the module 7. Is supplied to the input terminal B and an "H" level signal to the input terminal B, and an "H" level signal is supplied as the prediction signal E. Module 7
If normal, a "H" level signal is supplied to the output terminal O as a module signal M based on the test signal T.

The signal delay circuit 8 synchronizes with the second clock signal Clk2 supplied to the second clock signal input terminal 3 and delays the module signal M and the prediction signal E by a predetermined time. The signals DM are supplied simultaneously.

The comparator 10 determines whether or not the prediction signal DE and the module signal DM supplied from the signal delay circuit 8 match and supplies the comparison signal C. As a result of the comparison, when it is recognized that the prediction signal D-E and the module signal D-M do not match, the comparison signal C having a high signal level is obtained.
Is supplied to the comparator output terminal 5, and when it is recognized that the predicted signal DE and the module signal DM match, the comparison signal C having a low signal level is supplied to the comparator output terminal 5.

The error generation circuit 9 receives the error generation signal Er.
The module signal DM supplied from the signal delay circuit 8 based on r is the prediction signal D supplied from the signal delay circuit 8.
The error signal ES that never matches -E is supplied by switching.

As described above, the module 7 is internally provided.
Build-in self-test circuit 1 of the present invention for building
00 can detect whether or not the module 7 is functioning normally by detecting the signal level of the comparison signal C, and a functional test can be performed by providing a small number of external input / output terminals.

Further, in the built-in self-test circuit 100 of the present invention in which the module 7 is built inside, the error generation circuit 9 is supplied from the signal delay circuit 8 based on the error generation signal Err supplied from the outside. The module signal D-M to be converted into an error generation signal ES different from the prediction signal D-E is supplied. As a result, the comparator 10 makes a D-E comparison of the error generation signal ES and the prediction signal, and if the comparator 10 is normal, it supplies the comparison signal C of a high signal level. Therefore, the observer observes whether or not the signal level of the comparison signal C becomes a high signal level based on the error generation signal supplied from the outside, and thereby the comparator 1
It is possible to know whether 0 is functioning normally. First Embodiment FIGS. 2 and 3 show a first embodiment of the present invention.

The first embodiment discloses a build-in self-test circuit 101 for performing a functional test of the product-sum device 21.
FIG. 2 is a configuration diagram of a build-in self-test circuit 101 for a sum-of-products test according to the first embodiment of the present invention.
3 is a timing chart of the first embodiment of the present invention.

As shown in FIG. 2, the build-in self-test circuit 101 includes a reset input terminal 1, a first clock input terminal 2, a second clock input terminal 3, a comparator output terminal 5, and an address. The signal generation circuit 16, the signal generation unit 17, the signal inverter 18, the 41-bit equivalent flip-flops 20, 22, and 23, the 74-bit equivalent flip-flop 19, and the comparator 25 are included. ing. The signal generator 17 includes a ROM 17a and a ROM 1
7b and the memory size is 64 bits × 64 words. The sum-of-products device 21 has a data input terminal corresponding to 74 bits, a data output terminal corresponding to 41 bits, and a control terminal Ctrl corresponding to 3 bits, of which the data input terminal is for multiplication data corresponding to 17 bits. Input terminal, input terminal for multiplicative data equivalent to 17 bits, 4
An input terminal for added data corresponding to 0 bit is used.

Further, when the build-in self-test circuit 101 is actually operated, the reset signal output section 11 which supplies the reset signal Rst for resetting the counter existing inside the address signal generation circuit 16
And a first clock signal output section 12 for supplying the first clock signal Clk1 and a second clock signal output section 13 for supplying a second clock signal Clk2 having the same cycle as the first clock signal Clk1. To use.

The address signal generation circuit 16 sets the internal counter to "0" based on the supplied reset signal Rst.
Is reset to, the internal counter is incremented in synchronization with the rising edge of the supplied first clock signal Clk1, and the signal generator 17 is based on the internal count value.
8-bit address signal A to specify the output signal of
supply dr. The signal generation unit 17 synchronizes the supplied address signal Adr with the rising edge of the inverted first clock signal / Clk1 and operates the sum-of-products device 21 to be tested.
A test signal ROMa corresponding to a total of 74 bits, which has a test pattern for testing, a prediction signal ROMb corresponding to 41 bits, which predicts the output signal of the product-sum device 21 based on the test signal ROMa, and a product-sum operation Control signal C
and trl. Here, the ROM 17a stores the data of the prediction signal ROMa, and the ROM 17b stores the data of the test signal ROMb. Flip flop 19
Is a test signal T delayed from the supplied test signal ROMb until the next rise of the first clock signal Clk1.
The flip-flop 20 supplies est, and supplies the prediction signal Expt obtained by delaying the supplied prediction signal ROMa by the time until the next rise of the first clock signal Clk1.

The sum-of-products device 21 is supplied with the test signal Tes.
The product-sum operation is performed based on t and the supplied control signal Ctrl, and the product-sum output signal Mod is supplied. In synchronization with the rising edge of the second clock signal Clk2, the flip-flop 22 is supplied with the product-sum output signal Mo.
d supplies the sum-of-products output signal D-Mod delayed by a predetermined time, and the flip-flop 23 supplies the supplied prediction signal E.
The prediction signal D-Expt, in which xpt is delayed by a predetermined time, is supplied.

The comparator 25 determines whether or not the product-sum output signal D-Mod supplied from the flip-flop 22 and the prediction signal D-Test supplied from the flip-flop 23 match. If they match, a low signal level comparison signal Cmp is supplied, and if they do not match, a high signal level comparison signal Cmp is supplied.

As a result, the observer can know whether or not the module is functioning normally by detecting the signal level of the comparison signal. Next, using the timing chart shown in FIG. 3, the build-in self-test circuit 1
The operation of 01 will be described.

First, at time "T0", since the reset signal Rst is at a high signal level, the counter in the address signal generation circuit 16 is reset to "0", and the address signal generation circuit 16 receives the address based on the counter. The signal Adr is supplied.

At time "T1", the reset signal Rs
t changed to a low signal level. Therefore, the counter in the address signal generation circuit 16 is operated by the first clock signal Clk.
Counting starts in synchronization with the next rising edge of 1.

At time "T2", the address signal generation circuit 16 supplies a new address signal Adr based on the counter in synchronization with the rising edge of the first clock signal Clk1.

At time "T3", the signal generator 17 supplies the test signal ROMb and the prediction signal ROMa in synchronization with the rising edge of the inverted first clock signal / Clk1.

At time "T4", the flip-flop 19 supplies the test signal ROMb supplied thereto with the test signal Test delayed by the time until the next rise of the first clock signal Clk1, and the flip-flop 20 is supplied. The prediction signal ROMa is then input to the first clock signal Clk1.
The prediction signal Expt delayed by the time until rises is supplied. At this time, the address signal generator 16
A new address signal Adr is generated.

At time "T5", the product-sum unit 21 supplies the product-sum unit output signal Mod with a delay of the processing time from the supplied test signal Test. At time “T6”,
In synchronization with the rising edge of the second clock signal Clk2, the flip-flop 22 supplies the product-sum output signal D-Mod delayed by a predetermined time, and the flip-flop 23 supplies the prediction signal D-Expt delayed by a predetermined time. To do.
Further, the comparator 25 outputs the product-sum output signal D-Mod,
Since it is determined that the prediction signal D-Expt and the prediction signal D-Expt match, the comparison signal Cmp having a low signal level is supplied.

At time "T7", the product-sum output signal D
The case where -Mod and the prediction signal D-Expt do not match is shown. The comparator 25 receives the product-sum output signal D-Mod supplied via the flip-flop 22 and the product-sum output signal D supplied via the flip-flops 20 and 23.
Since it is determined that −Expt does not match, the comparison signal Cmp having a high signal level is supplied.

As a result, the observer can know whether or not the product-sum unit 21 is functioning normally by detecting the signal level of the comparison signal Cmp. As described above, according to the first embodiment, the build-in self-test circuit 101 of the first embodiment in which the product-sum unit 21 is built inside.
Is the reset signal Rst and the first clock signal Clk1.
The test signal Test for testing the product-sum adder 21 and the prediction signal Expt that predicts the output of the product-sum adder 21 corresponding to the test signal Test are generated. Flip flop 2
2 and 23 are the product-sum output signal D-Mod at the timing when the rising edge of the second clock signal Clk2 occurs.
And the prediction signal D-Expt to the comparator. The comparator 25 determines whether or not the delayed product-sum output signal D-Mod and the predicted signal D-Expt match, and supplies the comparison signal Cmp. As a result, the build-in self-test circuit 101 of the first embodiment has three input terminals for connecting at least the first clock signal Clk1, the second clock signal Clk2, and the reset signal Rst, and the comparison signal C.
Since it has a total of four test signal input / output terminals including one output terminal to which mp is connected, it becomes possible to perform a functional test of the product-sum device 21 without requiring a large number of external input / output terminals. Second Embodiment FIGS. 2, 4, and 5 show a second embodiment of the present invention.

FIG. 2 is a block diagram of the build-in self-test circuit 101 for the sum-of-products test in the second embodiment. FIG. 4 is a timing chart of the second embodiment, and FIG. 4A shows a case where the prediction signal D-Expt and the product-sum output signal D-Mod are supplied to the comparator 25 in synchronization. 4B shows the case where the prediction signal D-Expt and the product-sum output signal D-Mod are supplied to the comparator 25 without being synchronized. FIG. 5 is a timing chart for explaining the processing time of the product-sum adder 21 of the second embodiment.

In FIG. 2, the build-in self-test circuit 101 in the second embodiment has the same structure as the build-in self-test circuit 101 shown in the first embodiment.

In addition, the build-in
When operating the self-test circuit 101, the signal level of the comparison signal Cmp is detected in addition to the reset signal output unit 11, the first clock signal output unit 12, and the second clock signal output unit 13 of the first embodiment. Comparison signal detector 15
And a first clock signal Clk1 and a second clock signal C
The phase difference detector 26 detects the phase difference of lk2 and adjusts the phase of the second clock signal Clk2 to be delayed (or advanced) while the comparison signal detector 15 detects a high signal level signal. The phase adjuster 27 is used by being connected.

Next, the operation of the second embodiment will be described with reference to FIGS. 4 and 5. FIG. 4A shows a prediction signal D-
7 is a timing chart when the phases of the Expt and the product-sum output signal D-Mod are supplied to the comparator 25 in synchronization with each other.

At time "T11", in synchronization with the rising edge of the second clock signal Clk2, the flip-flop 23 supplies the prediction signal D-Expt obtained by delaying the supplied prediction signal Expt by a predetermined time, and the flip-flop 23. 22 supplies a product-sum output signal D-Mod obtained by delaying the supplied product-sum output signal Mod by a predetermined time.
The comparator 25 determines that the prediction signal D-Expt supplied by the flip-flop 23 and the sum-of-products output signal D-Mod supplied by the flip-flop 22 match each other, and the comparison signal Cmp of the low signal level. To supply.

As a result, the observer has the comparison signal detecting means 1
By recognizing that the comparison signal Cmp detected by 5 is at a low signal level, it can be known that the prediction signal D-Expt and the module signal D-Mod are synchronously input to the comparator 25. .

FIG. 4B shows the prediction signal D-Expt,
7 is a timing chart in the case where the phase of the sum of product output signal D-Mod is supplied to the comparator 25 without being synchronized in phase.
Comparing FIG. 4A and FIG. 4B, the prediction signal Ex
The phase difference between pt and the product-sum output signal Mod is the same, but the phase of the second clock signal Clk2 is changing.
The flip-flops 22 and 23 have the second clock signal Cl.
Prediction signal D-Exp in synchronization with the rising edge of k2
t and the product-sum output signal D-Mod. Therefore, the comparator 25 outputs the prediction signal D-Expt and the product-sum output signal D- which is delayed by one cycle from the prediction signal D-Expt.
Since Mod and will be compared, the prediction signal DE
It is determined that xpt does not match the sum-of-products output signal D-Mod, and the high signal level comparison signal Cmp is supplied.

The above timing will be specifically described below. At time “T12”, in synchronization with the rising edge of the second clock signal Clk2, the flip-flop 23 supplies the prediction signal D-Mod obtained by delaying the supplied prediction signal Mod by a predetermined time. However, at this timing, the product-sum adder 21 outputs the product-sum adder output signal Mo.
Since d is not supplied, the product-sum output signal D-Mod is not supplied from the flip-flop 22. The comparator 25 has a prediction signal D- supplied by the flip-flop 23.
It is determined that the Expt does not match the sum-of-products output signal D-Mod supplied by the flip-flop 22, and the comparison signal Cmp having a high signal level is supplied.

As a result, the observer is informed that the comparison signal detector 15
It is possible to know that the prediction signal D-Expt and the module signal D-Mod are input to the comparator 25 without being synchronized with each other, by recognizing that the comparison signal Cmp detected by is high signal level. .

At time "T13", in synchronization with the rising edge of the second clock signal Clk2, the flip-flop 23 supplies the prediction signal D-Expt, and the flip-flop 22 outputs 1 to the prediction signal D-Expt. A product-adder output signal D-Mod that is cyclically delayed is supplied.

Here, the phase adjuster 27 delays (or advances) the phase of the second clock signal Clk2 until the comparison signal detecting means 15 detects the change of the comparison signal Cmp from the high signal level to the low signal level. The phase difference detector 26 adjusts the first clock signal Clk1 when the comparison signal Cmp changes from the high signal level to the low signal level.
And the second clock signal Clk2 are detected. This phase difference corresponds to the processing time of the product-sum device 21.

The method of inspecting the processing time of the product-sum unit 21 will be described in more detail with reference to FIG. Time "T2
At 1 ″, the rising edge of the second clock signal Clk2 indicates that the prediction signal Expt and the product-sum output signal Mod are synchronized. At this point, the comparison signal C
It can be seen that mp is a low signal level.

At time “T22”, the phase adjuster 13
Delays the phase of the second clock signal Clk2, a deviation occurs in the synchronization between the prediction signal Expt and the product-sum output signal Mod, and the product-sum output signal D-Mod changes the prediction signal D-E.
It is supplied to the comparator 25 with a delay of one cycle from xpt. Therefore, the comparator 25 supplies the high signal level comparison signal Cmp.

At time "T24", the phase adjuster 27
Further delays the phase of the second clock signal Clk2,
The phase of the prediction signal Expt and the phase of the product-sum output signal Mod are synchronized, and the comparison signal C supplied by the comparator 25 is obtained.
mp changes from high signal level to low signal level.

Therefore, the phase difference detector 26 has the time "T24" when the second clock signal Clk2 rises and the time "T23" when the first clock signal Clk1 rises.
And the phase difference "t" between Here, time “T2
3 "is the time when the flip-flop 20 supplies the prediction signal Expt, and the time" T24 "is the time when the output of the product-sum device 21 (product-sum device output signal Mod) is determined.

That is, time "T23" and time "T2"
The phase difference "t" from 4 "corresponds to the processing time of the product-sum adder 21. As described above, according to the second embodiment, the product-sum adder 21 is internally constructed in the second embodiment. Build of
The in-self test circuit 101 uses the second clock signal C
By adjusting the phase of lk2 and detecting the phase difference between the first clock signal Clk1 and the second clock signal Clk2 when the comparison signal Cmp changes from the high signal level to the low signal level, It becomes possible to know the processing time of 21. Third Embodiment FIGS. 6 and 7 show a third embodiment of the present invention.

FIG. 6 shows a build / execution of the third embodiment of the present invention.
FIG. 7 is a configuration diagram of the in-self test circuit 102, and FIG. 7 is a timing chart of the third embodiment of the present invention. Figure 6
In addition to the configuration of the build-in self-test circuit 101 according to the first embodiment, the build-in self-test circuit 102 according to the third embodiment of the present invention includes an error occurrence signal input terminal 4 and An error generation circuit that switches the supplied product-sum output signal D-Mod to an error signal ErSig different from the prediction signal D-Expt based on the comparison signal output terminal 5 and the error signal Err and supplies the error signal ErSig to the comparator 25. 24, and is comprised.

When the build-in self-test circuit 102 is actually operated, the reset signal output section 11, the first clock signal output section 12, and the first clock signal output section 12 of the build-in self-test circuit 101 of the first embodiment. In addition to the second clock signal output unit 13, an error occurrence signal output unit 14,
The comparison signal detection unit 15 that detects the signal level of the comparison signal Cmp is connected and used.

Next, the operation of the third embodiment will be described with reference to FIG. At time “T31”, the flip-flop 22 supplies the product-sum output signal D-Mod obtained by delaying the product-sum output signal Mod by a predetermined time in synchronization with the second clock signal Clk2, and the flip-flop 23 outputs the prediction signal. Prediction signal D-Expt delayed from Expt by a predetermined time
To supply. The error generation circuit 24 uses the error generation signal E
Since rr is a low signal level, the flip-flop 22
The sum-of-products output signal D-Mod supplied from the device is directly supplied as the error signal ErSig without conversion. The comparator 25 determines that the supplied error signal ErSig and the supplied expected signal D-Expt match each other, and supplies the low signal level comparison signal Cmp.

Since the comparison signal Cmp detected by the comparison signal detecting means 15 has a low signal level, the observer
It can be known that the accumulator 21 is operating normally. At time "T32", the observer supplies the error generation signal Err from the error generation signal generation means 14 in order to test whether the comparator 25 is operating normally. Since the error generation signal Err is at a high signal level, the error generation circuit 24 converts the sum-of-products signal D-Mod supplied from the flip-flop 22 into an error signal ErSig containing error information and supplies the error signal ErSig to the comparator 25. .

At time "T33", the comparator 25
It is determined that the supplied error signal ErSig and the supplied expected signal D-Expt do not match, and the comparison signal Cmp having a high signal level is supplied.

The observer knows that the comparator 25 is operating normally because the comparison signal Cmp detected by the comparison signal detecting means 15 has become a high signal level based on the error occurrence signal Err. You can

As described above, according to the third embodiment, the build / accumulator of the third embodiment in which the product-sum unit 21 is built is constructed.
The in-self-test circuit 102 delays the signal based on the error generation signal Err supplied from the outside by the error generation circuit 24 while the comparator 25 continuously supplies the comparison signal Cmp of the normal low signal level. The module signal D-Mod supplied from the circuits 22 and 23 is set to the error signal ErS.
Since it is converted into ig, the prediction signal D-Expt supplied from the signal delay circuits 22 and 23 and the error signal ErSig do not always match, and if the comparator 25 is normal, the comparison signal Cmp of high signal level is output. Will be supplied.

As a result, the comparator 25 determines that the supplied module signal D-Mod and predicted signal D-Expt match each other, and when the comparison signal Cmp of low signal level is continuously supplied. In addition, an error signal ErSig in which the module signal D-Mod is different from the prediction signal D-Expt based on the error occurrence signal Err supplied from the outside.
Will be converted to. Therefore, by observing whether or not the comparison signal Cmp is inverted to a high signal level when the error occurrence signal Err is supplied from the outside,
It is possible to know whether or not the comparator 25 is operating normally.

[0073]

As described above, according to the first aspect of the invention, the signal generator resets the internal counter based on the reset signal supplied from the outside, and the first clock supplied from the outside. Counting is performed in synchronization with the signal, and a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module corresponding to the test signal are supplied. The signal delay circuit delays and supplies the module signal and the prediction signal supplied by the module for a predetermined time in synchronization with the second clock signal supplied from the outside. The comparator determines whether or not the module signal and the test signal supplied from the signal delay circuit match and supplies the comparison signal. As a result, the comparator can determine whether the module is functioning normally by observing the signal level of the comparison signal obtained by comparing the prediction signal and the module signal. Therefore,
The test circuit enables functional testing of the module without requiring a large number of external input / output terminals, and is suitable as an actual product.

According to the invention of claim 2, claim 1
In addition to the configuration of the invention described in (1), the error generation circuit converts the module signal supplied from the signal delay circuit into an error signal different from the prediction signal based on the error generation signal supplied from the outside, and supplies the error signal.

As a result, the comparator compares the prediction signal and the error signal, and supplies the comparison signal judged that the prediction signal and the error signal do not match as a result of the comparison. Therefore, when the error generation signal is supplied from the outside, if the comparator is normal, it always supplies the comparison signal judged that the prediction signal and the error signal do not match, so that the comparator functions normally. You can easily know whether or not there is.

According to the third aspect of the present invention, the internal counter is reset based on the reset signal supplied from the outside, counting is performed in synchronization with the first clock signal supplied from the outside, and the count is performed. A test signal for testing the module based on the above and a prediction signal for predicting the output signal of the module corresponding to the test signal are supplied. In synchronization with the second clock signal supplied from the outside,
The module signal and the prediction signal supplied by the module are delayed by a predetermined time and then supplied. It is determined whether or not the module signal and the test signal supplied from the signal delay circuit match, and the comparison signal is supplied.

As a result, it is possible to judge whether or not the module is functioning normally by observing the signal level of the comparison signal obtained by comparing the prediction signal and the module signal with the comparator. Therefore, the test circuit can perform a functional test of the module without requiring a large number of external input / output terminals, and is suitable as an actual product.

According to the invention described in claim 4, the phase of the second clock signal is changed at least from the state where the comparison signals do not match to the measurement timing which is the timing when the comparison signals next match. The phase difference between the clock signal and the second clock signal is detected.

As a result, the test circuit detects the phase of the first clock signal corresponding to the timing when the test signal is supplied to the module and the phase of the second clock signal corresponding to the timing when the module signal is supplied from the module. Will be compared. Therefore, the actual phase difference between the first clock signal and the second clock signal, which corresponds to the processing time of the module, can be known, and the actual processing time of the module can be measured.

According to the fifth aspect of the invention, the internal counter is reset based on the reset signal supplied from the outside, the counting is performed in synchronization with the first clock signal supplied from the outside, and the count is performed. A test signal for testing the module based on the above and a prediction signal for predicting the output signal of the module corresponding to the test signal are supplied. In synchronization with the second clock signal supplied from the outside,
The module signal and the prediction signal supplied by the module are delayed by a predetermined time and then supplied. It is determined whether or not the module signal and the test signal supplied from the signal delay circuit match, and the comparison signal is supplied. The module signal supplied from the signal delay circuit is converted into an error signal different from the prediction signal and supplied based on the error generation signal supplied from the outside.

As a result, the comparator compares the prediction signal and the error signal, and supplies the comparison signal judged that the prediction signal and the error signal do not match as a result of the comparison. Therefore, when the error generation signal is supplied from the outside, if the comparator is normal, it always supplies the comparison signal judged that the prediction signal and the error signal do not match, so that the comparator functions normally. You can easily know whether or not there is.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a build-in self-test circuit showing a first embodiment and a second embodiment of the present invention.

FIG. 3 is a timing chart of the first embodiment of the present invention.

FIG. 4 is a timing chart of the second embodiment of the present invention, in which (a) the prediction signal D-Expt and the product-sum output signal D-Mod are supplied to the comparator 25 in synchronization. In the case (b), the prediction signal D-Expt and the product-sum output signal D-Mod are supplied to the comparator 25 without being synchronized.

FIG. 5 is a timing chart illustrating a processing time of the product-sum unit 21 according to the second embodiment of this invention.

FIG. 6 is a configuration diagram of a build-in self-test circuit showing a third embodiment of the present invention.

FIG. 7 is a timing chart of the third embodiment of the present invention.

FIG. 8 is a configuration diagram of a conventional sum-of-products tester.

[Explanation of symbols]

 1 ... Reset signal input terminal 2 ... First clock signal input terminal 3 ... Second clock signal input terminal 4 ... Error signal input terminal 5 ... Comparator output terminal 6 ... Signal generator 7 ... Module 8 ... Signal delay circuit 9, 24 ... error generation circuit 10, 25 ... comparator 11 ... reset signal output unit 12 ... first clock signal output unit 13 ... second clock signal output unit 14 ... error generation signal output unit 15 ... comparison signal detection unit 16 ... address signal generation Circuit 17 ... Signal generation unit 18 ... Signal inverter 19, 20, 22, 23 ... Flip-flop 21 ... Sum of products 26, 27 ... Tester Rst ... Reset signal Clk1 ... First clock signal Clk2 ... Second clock signal Err ... Error Signal Cmp ... Comparison signal Test ... Test signal Expt ... Prediction signal Mod ... Module signal ErSig ... Error occurrence Issue

Claims (5)

[Claims] 1. A test circuit for testing a module built in a semiconductor integrated circuit, which resets an internal counter based on a reset signal supplied from the outside and synchronizes with a first clock signal supplied from the outside. And a signal generator for supplying a prediction signal for predicting an output signal of the module corresponding to the test signal and the test signal for testing the module based on the count, and a signal generator externally supplied. (2) whether the module signal and the test signal supplied from the signal delay circuit match the signal delay circuit that delays the module signal and the prediction signal supplied by the module for a predetermined time in synchronization with the clock signal A test circuit comprising: a comparator for determining whether or not to supply a comparison signal, and a comparator. 2. A test circuit for testing a module built in a semiconductor integrated circuit, which resets an internal counter based on a reset signal supplied from the outside and synchronizes with a first clock signal supplied from the outside. And a signal generator for supplying a prediction signal for predicting an output signal of the module corresponding to the test signal and the test signal for testing the module based on the count, and a signal generator externally supplied. In synchronization with the two clock signals, the module signal supplied by the module and the prediction signal are delayed by a predetermined time and supplied, and the module signal and the prediction signal supplied from the signal delay circuit match each other. Based on a comparator that determines whether or not there is an error signal and an error signal that is externally supplied. Test circuit comprising the, an error generation circuit supplies by converting the module signal which is supplied to an error signal differs from the predicted signal from the signal delay circuit. 3. A test method for testing a module built in a semiconductor integrated circuit, wherein an internal counter is reset based on a reset signal supplied from the outside and synchronized with a first clock signal supplied from the outside. And counting, and supplying a test signal for testing the module based on the count and a prediction signal that predicts the output signal of the module corresponding to the test signal, and a second clock supplied from the outside. Synchronizing with the signal, the module signal supplied by the module and the predicted signal are delayed for a predetermined time and supplied, and it is determined whether the module signal and the test signal supplied from the signal delay circuit match. And a step of supplying a comparison signal, and a test method comprising: 4. A test method for performing an AC characteristic test of a module using the test circuit according to claim 1, wherein the second clock is at least from a state where the comparison signals do not match to a measurement timing when the comparison signals next match. A test method comprising: a step of changing a phase of a signal; and a step of detecting a phase difference between the first clock signal and the second clock signal at the measurement timing. 5. A test circuit test method for testing a module built in a semiconductor integrated circuit, wherein an internal counter is reset based on a reset signal supplied from the outside, and a first clock signal supplied from the outside. And a test signal for testing the module based on the count and a prediction signal that predicts an output signal of the module based on the test signal; The step of delaying and supplying the module signal and the prediction signal supplied by the module for a predetermined time in synchronization with the two clock signals, and whether or not the module signal and the prediction signal supplied from the signal delay circuit match. Whether or not the signal is supplied based on the error occurrence signal supplied from the outside. The method of testing the test circuit, characterized in that the module signal supplied from the delay circuit and a step of supplying converted to an error signal differs from the predicted signal.