JPH086676A - Device and method for preventing rush current - Google Patents

Abstract

PURPOSE:To shorten a wait time and prevent the rush current by varying the delay time of each delay circuit board connected to each CPU board and outputting a reset signal according to an initialization time. CONSTITUTION:The initialization times of plural CPU boards 1 in use are measured previously; and the longest initialization time of a CPU 1A is denoted TA, the next long initialization time of a CPU board 1B is denoted as TB, and the following initialization of a CPU board 1C is denoted as TC. In this case, the input timing points of reset signals to the respective CPU boards are so set that the delay time DB of a delay circuit board 5B connected to the CPU board 1B is TA-TB and the initialization time to the CPU board 1A delay time DC of a delay circuit 5C connected to the CPU board 1C is TA-TC on the basis of the delay time DA of a delay circuit board 5B connected to the CPU board 1A with the longest initialization time. Consequently, the wait time in parallel processing can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for preventing an inrush current, which is an excessive current at power-on of a system having a plurality of CPU boards and I / O boards.

[0002]

2. Description of the Related Art Conventionally, a plurality of CPU boards and I / O
In a microcomputer equipped with a board, when the CPU board is turned on at the same time, an instantaneous current becomes excessive, that is, a so-called rush current flows, which may damage the elements of each CPU. As a method of preventing such an inrush current, a system clock signal generation circuit that generates a plurality of system clock signals, a standby signal generation circuit that generates a standby signal, and a standby signal based on the standby signal when the standby mode is generated. It is disclosed that a constant level holding circuit for sequentially holding the plurality of system clock signals at a constant level is provided, and a microcomputer is driven according to the sequentially output system clock signals (for example, Japanese Utility Model Laid-Open Publication No. 1-142031). issue). Further, the control unit connected to the switch means provided between the power source and the plurality of electric devices sequentially controls the switch means to be in the connected state at predetermined time intervals, thereby sequentially supplying power to each electric device. It is disclosed that power is supplied and the power is sequentially activated (for example, Japanese Utility Model Laid-Open No. 4-88337).

[0003]

However, in the former related art, the length of each system clock signal is constant, and in the latter related art as well, the time interval for successive connection is constant, so that resetting is performed. When a plurality of CPUs with different initialization times from the start to the start of processing are sequentially activated, the time that each CPU can process becomes different, and a waiting time occurs in each CPU before the processing of all the CPUs starts. There is a problem that the CPU start time is delayed. It is an object of the present invention to output a reset signal according to the initialization time of each CPU and reduce the waiting time to prevent inrush current.

[0004]

In order to solve the above problems, the present invention provides a rush current prevention device for a system in which electric power is input to a plurality of CPU boards and I / O boards via a backplane board. The plurality of Cs between the CPU board and the backplane board.
The delay circuit board is connected with a plurality of delay circuits whose delay time is the time obtained by subtracting the initialization time of each CPU from the longest initialization time of the PU board. In addition, in a method for preventing an inrush current of a system in which electric power is input to a plurality of CPU boards and I / O boards via a backplane board, a plurality of delay circuits are mounted between the plurality of CPU boards and the backplane board. Delay circuit boards are connected, and the delay time of each delay circuit is set to the plurality of CPUs.
The initializing time of each CPU is subtracted from the longest initializing time of the board initializing times, and the reset signal input timing to each CPU board is changed according to the delay time.

[0005]

By the above means, the delay time of each delay circuit board connected to each CPU board is changed according to the initialization time of each CPU board, and the time when power is input to each CPU board is shifted, so that the inrush current is increased. Can be prevented. Further, the processing start times of all the CPU boards are the same, the waiting time from the input of the first reset signal to the start of the parallel processing is reduced, and the processing start time of the computer is shortened.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, for simplification of description, an example in which three CPU boards are used will be described. 1 is a plurality of CPU boards, 2 is a backplane board, 3 is a power supply, 4 is I /
O board and 5 are delay circuit boards. Each CPU board (1A, 1B, 1C) is supplied with power from the power supply 3 via the backplane board 2 and also transmits data between the CPUs 1 and command signals from the I / O board 4. is there. Backplane board 2 and each C
CPs are connected between the PU boards 1A, 1B and 1C respectively.
A delay circuit board 5 (5A, 5B, 5) equipped with a delay circuit for delaying a reset signal for reapplying power to the U board
C) is connected. As shown in FIG. 2, the delay circuit board 5 is provided with a plurality of delay elements 6 (61, 62, 63 ... 6n) between the input side and the output side of the reset signal, and by connecting the jumper terminals 7, a plurality of delay elements 6 are provided. The delay elements 6 are arbitrarily selected and connected in series, and the delay times of the respective delay elements are added so that the delay time can be arbitrarily set. When setting the delay time of the delay circuit board 5, the initialization time of the plurality of CPU boards 1 to be used is measured in advance, and the lengths are compared to determine the longest initialization time of the plurality of CPU boards. Each C
A time obtained by subtracting the PU initialization time is set as each delay time. For example, of the multiple CPU boards 1,
CPU board 1 with the longest initialization time is the CPU
In the board 1A, the initialization time is T _A , the CPU board 1B has the second longest initialization time, the initialization time is T _B , the CPU board 1B is the next initialization time, and the initialization time is T _C. In this case, the reset signal input timing to each CPU board is based on the delay time D _A of the delay circuit board 5A connected to the CPU board 1A by the CPU board 1 having the longest initialization time as a reference (0 or a minute time). The delay time D _B of the delay circuit board 5B connected to the board 1B is T _A -T _B , and the CPU board 1
The delay time D _C of the delay circuit board 5C connected to _{C is set} to T _A
And -T _C. Note that CPUs with the same initialization time
When there are boards, it is sufficient to shift the delay time slightly from each other. By setting the delay time in this way,
Since the time when power is input to each CPU board is shifted,
No inrush current flows. Further, the processing start times of all the CPU boards 1 are the same, the waiting time from the input of the first reset signal to the start of the parallel processing is reduced, and the processing start time of the computer is shortened.

[0007]

As described above, according to the present invention, the input time of the reset signal of a plurality of CPU boards is set to each CPU.
Since they are set to be shifted from each other according to the initialization time of the board, there is an effect that the waiting time from the input of the first reset signal to the start of the parallel processing can be reduced to prevent the inrush current.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a connection diagram showing a configuration of a delay circuit board according to an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

1 (1A, 1B, 1C) CPU board, 2 backplane boards, 3 power supplies, 4 I / O boards, 5 (5
A, 5B, 5C) Delay circuit board

Claims (2)

[Claims] 1. A rush current prevention device for a system in which electric power is input to a plurality of CPU boards and I / O boards via a backplane board, wherein the plurality of CPU boards and the backplane board are provided with a plurality of the plurality of CPU boards. C
An inrush current prevention device, comprising: a delay circuit board having a plurality of delay circuits, the delay time being a time obtained by subtracting the initialization time of each CPU from the longest initialization time of the PU board. 2. A method for preventing inrush current of a system for inputting power to a plurality of CPU boards and I / O boards via a backplane board, wherein a delay circuit is provided between the plurality of CPU boards and the backplane board. A plurality of mounted delay circuit boards are connected and the delay time of each delay circuit is set to a time obtained by subtracting the initialization time of each CPU from the longest initialization time among the initialization times of the plurality of CPU boards. A method for preventing inrush current, which comprises changing the input timing of a reset signal to the input circuit according to the delay time.