JPH0865119A - Power-on reset circuit - Google Patents

Abstract

PURPOSE: To surely provide an output of a reset signal used to initialize an internal circuit. CONSTITUTION: The power-on reset circuit is provided with an oscillator 1 and an output circuit 2 and a high potential power supply VCC and a low potential power stupply GND are applied to the power-on reset circuit as the operation power supplies. The oscillator 1 provides an output of an oscillation signal F1 with a frequency corresponding to voltages of the power supplies VCC, GND to be supplied. The output circuit 2 detects the frequency of the oscillation signal and when the detected frequency is less than the predetermined frequency, a reset signal POR1 to initialize the internal circuit to be a prescribed state is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit provided in a semiconductor device. For example, in a semiconductor device including a flip-flop circuit, a latch circuit, and the like as an internal circuit, a power-on reset circuit is provided,
When the power is turned on, it is necessary to delay the supply of power to the internal circuit and initially set it to a predetermined state to prevent malfunction of the semiconductor device.

For example, in a synchronous random access memory (STRAM), it is required to be able to guarantee that data of all memory cells of a memory cell array is L or H when power is turned on.

[0003]

2. Description of the Related Art FIG. 5 shows a power-on reset circuit in a conventional semiconductor device. Power-on reset circuit 4
Reference numeral 0 includes an NMOS transistor 41, a PMOS transistor 42, a capacitor C11, resistors R11 and R12, and inverters 43 and 44, and a power supply Vcc and a ground GND are supplied as operating power supplies.

When the power supply VCC is applied to this semiconductor device, the voltage of the power supply VCC rises from the voltage of the ground GND. When the power supply Vcc is turned on, the voltage of the node N2 is the resistance R
Since it is pulled up to the power supply Vcc by 12, the inverter 44 outputs the L-level reset signal POR0 to the internal circuit. Since the gate of the PMOS transistor 42 is connected to the node N2, at this time PM
The OS transistor 42 is off. On the other hand, power supply VCC
Is turned on, the gate of the NMOS transistor 41 is connected to the power supply Vcc, so that the transistor 41 is turned on. Capacitor C via transistor 41 turned on
11 is charged, and the voltage of the node N1 rises from the power supply VCC to a voltage lower by the threshold voltage Vth of the transistor 41. When the voltage of the node N1 becomes H level, the output of the inverter 43 becomes L level and the reset signal POR0 of the inverter 44 becomes H level. That is, the reset signal POR0 catches up with the power supply VCC and becomes H level with a delay of the time required to charge the capacitor C11, and the supply of the power supply VCC to the internal circuit is delayed. This delay time is determined by the resistance value of the resistor R12 and the capacitance of the capacitor C11.

[0005]

However, in the above conventional power-on reset circuit 40, since the capacitor C11 is charged by the power supply VCC, the timing at which the reset signal POR0 becomes H level varies depending on the rising speed of the power supply VCC. Will end up. Due to the reset signal POR0 whose timing changes in this way, even if the internal circuit is not desired to be reset, it may be reset,
Even if the reset is desired to be released, there is a problem that the reset remains applied, which causes a malfunction of the internal circuit.

The present invention has been made to solve the above problems, and an object thereof is to provide a power-on reset circuit that can reliably output a reset signal for initially setting an internal circuit. .

[0007]

FIG. 1 is a diagram illustrating the principle of the present invention. The power-on reset circuit includes an oscillator 1 and an output circuit 2, and a high-potential power supply VCC and a low-potential power supply GND are supplied to the power-on reset circuit as operating power supplies. The oscillator 1 outputs an oscillating signal F1 having a frequency according to the voltage of the power supplies Vcc and GND supplied. The output circuit 2 detects the frequency of the oscillation signal F1 and, when the detected frequency is less than a predetermined frequency, a reset signal POR for initially setting the internal circuit to a predetermined state.
1 is output.

[0008]

According to the present invention, the frequency of the oscillation signal F1 of the oscillator 1 becomes a value according to the voltage of the power supplies Vcc and GND to be supplied, and when the frequency of the oscillation signal F1 is less than the predetermined frequency, the reset signal is generated. POR1 is output. Therefore, the reset signal POR1 can be reliably output to the internal circuit when the power is turned on.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. FIG. 2 shows a power-on reset circuit 10 of this embodiment provided on a semiconductor device. The power-on reset circuit 10 has a power source V as a high potential power source.
CC and ground GND as a low potential power supply are supplied. The power-on reset circuit 10 supplies a reset signal PO to the internal circuit based on the turning on of the power supply Vcc and the ground GND.
By outputting R1, the internal circuit is initially set to a predetermined state.

The power-on reset circuit 10 includes an oscillator 11
And an output circuit 12. The oscillator 11 includes inverters 15 and 18, a 2-input NOR circuit 19, and eight inverters 20, and outputs an oscillation signal S1 having a frequency corresponding to the voltage of the power supply VCC and the ground GND supplied. The inverter 15 includes a PMOS transistor 16 and an NMOS connected in series between the power source Vcc and the ground GND.
It consists of a transistor 17 and both transistors 16 and 1
The gate of 7 is connected to the ground GND. The inverters 18 and 20 have the same configuration as the inverter 15,
The input terminal of the inverter 18 is connected to the output terminal between the transistors 16 and 17. Therefore, when the power supply Vcc and the ground GND are turned on, the output signal of the inverter 15 becomes H level and the output signal of the inverter 18 becomes L level.

Eight inverters 20 are connected in series to the output terminal of the NOR circuit 19, and the oscillation signal S1 is output from the final stage inverter 20. The output signal of the inverter 18 is input to one input terminal of the NOR circuit 19, and the oscillation signal S1 is input to the other input terminal.
Therefore, since the output signal of the inverter 18 becomes L level when the power supply VCC and the ground GND are turned on,
The NOR circuit 19 outputs a signal obtained by inverting the oscillation signal S1. The output signal of the NOR circuit 19 is eight inverters 20.
Are sequentially inverted by and are output as an oscillation signal S1 from the final stage inverter 20.

The output circuit 12 is a toggle flip-flop (hereinafter simply referred to as a toggle FF) 21 as a frequency dividing circuit,
A 2-input NAND circuit 22 as an adjusting circuit, a resistor R1,
And inverters 23 and 27. Output circuit 12
Detects the frequency of the oscillation signal S1 of the oscillator 11, and outputs the reset signal POR1 to the internal circuit when the detected frequency is less than the predetermined frequency.

The data terminal D of the toggle FF 21 is connected to the inverting output terminal bar Q, and the oscillation signal S1 is input to the clock terminal CK. The toggle FF 21 outputs from the output terminal Q a divided signal S2 obtained by dividing the frequency of the oscillation signal S1 by half.

The oscillation signal S1 is input to one input terminal of the NAND circuit 22, the divided signal S2 is input to the other input terminal, and the output terminal is connected to the inverter 23 via the resistor R1. There is. A capacitor C1 is connected between a node between the resistor R1 and the inverter 23 and the ground GND.

The NAND circuit 22 charges the capacitor C1 based on the H level output signal S3 based on the levels of the oscillation signal S1 and the divided signal S2, and discharges the capacitor C1 based on the L level output signal S3. NAND
The circuit 22 outputs the L-level signal S3 only when the levels of the oscillation signal S1 and the divided signal S2 are both H. In addition, the NAND circuit 22 outputs the oscillation signal S1 and the divided signal S2.
When at least one of the two levels is L, an H level signal S3 is output. In this way, the NAND circuit 22
Sets the discharging time of the capacitor C1 to 1/4 in one cycle of the frequency dividing signal S2, and sets the charging time of the capacitor C1 to 3/4 in one cycle of the frequency dividing signal S2.

When the level of the output signal S3 is H, the capacitor C1 is charged by the current flowing from the NAND circuit 23 via the resistor R1. When the level of the output signal S3 is L, the capacitor C1 is discharged by the current flowing to the NAND circuit 22 via the resistor R1. The resistor R1 controls the amount of current accompanying the charging and discharging of the capacitor C1.

The inverter 23 is a PMOS transistor 2
4 and NMOS transistors 25 and 26, and NMO
S transistor 26, PMOS transistor 24 and N
The MOS transistor 25 is connected in series in this order between the power supply Vcc and the ground GND. The gate of the NMOS transistor 26 is connected to the power source Vcc. PMO
A voltage signal S based on the charging voltage of the capacitor C1 is applied to the gates of the S transistor 24 and the NMOS transistor 25.
4 has been entered. The threshold voltage Vth of the PMOS transistor 24 is set to a small value by setting the gate width of the transistor 24 large or setting the channel length short. As a result, the inversion level of the inverter 23 is, as shown in FIGS.
Exists on the side. When the level of the voltage signal S4 is less than the inversion level, the PMOS transistor 24 is turned on, and the inverter 23 outputs the voltage of the power supply VCC to the transistor 26.
A signal of a voltage level (H level) lowered by the threshold voltage Vth of is output. On the contrary, when the level of the voltage signal S4 is equal to or higher than the inversion level, the NMOS transistor 25
Is turned on, and the signal of the voltage level (L level) of the ground GND is output from the inverter 23.

The inverter 27 is a PMOS transistor 2
8 and an NMOS transistor 29, and the gates of both transistors 28 and 29 are connected to the output terminal of the inverter 23. The inverter 27 inverts the level of the output signal of the inverter 23 so that the reset signal POR
1 is output to the internal circuit. When the output signal of the inverter 23 is at H level, the transistor 29 is turned on and the reset signal POR1 becomes L level. Conversely, when the output signal of the inverter 23 is L level, the transistor 28 is turned on and the reset signal POR1 becomes H level. Next, the operation of the power-on reset circuit 10 configured as described above will be described with reference to FIGS.

When the power supply VCC and the ground GND are turned on, the voltage of the power supply VCC rises from the voltage of the ground GND. As shown in FIG. 3, when the voltage of the power supply VCC is low when the power supply VCC is turned on, the frequency of the oscillation signal S1 is low, and the frequency of the frequency-divided signal S2 is one half of the oscillation signal S1. In other words, one cycle of the divided signal S2 becomes longer. The capacitor C1 changes from the voltage of the power supply VCC to the threshold voltage V of the transistor 26 during the H level period of the output signal S3.
It is charged to a voltage level (H level) lowered by th. Since one cycle of the divided signal S2 is long, the output signal S
3, the voltage level of the voltage signal S4 of the capacitor C1 becomes less than the inversion level of the inverter 23. As a result, the output signal of the inverter 23 becomes H level, and the inverter 27 surely outputs the L level reset signal POR1 to the internal circuit.

The voltage of the power supply VCC is still low, and the oscillation signal S1
If the frequency is low, the L level reset signal POR1 is surely output in the same manner as described above. The internal circuit is initially set to a predetermined state based on the L-level reset signal POR1, and malfunction of the internal circuit is prevented.

When the voltage of the power source Vcc further rises, as shown in FIG.
As shown in, the frequency of the oscillation signal S1 becomes high and one cycle of the divided signal S2 becomes short. The capacitor C1 is charged to the H level during the H level of the output signal S3. Since one cycle of the divided signal S2 is short, the output signal S
The time of the L level of 3 becomes short, and the voltage level of the voltage signal S4 of the capacitor C1 becomes equal to or higher than the inversion level of the inverter 23. As a result, the output signal of the inverter 23 becomes L level, and the inverter 27 outputs the H level reset signal POR1 to the internal circuit.

The initial setting of the internal circuit is released based on the H-level reset signal POR1, and the internal circuit starts its operation based on a control signal (not shown). As described above, in this embodiment, the capacitor C1 is charged / discharged based on the oscillation signal S1 having the frequency corresponding to the voltage of the power supply Vcc supplied, and the voltage level of the voltage signal S4 is changed to the inverter 23.
Is less than the inversion level of L, the reset signal PO of L level
R1 can be reliably output to the internal circuit. This L
The internal circuit can be initially set to a predetermined state by the level reset signal POR1.

Further, in this embodiment, the NAND circuit 22 sets the charging time of the capacitor C1 to three times the discharging time. Therefore, when the capacitor C1 is charged, the voltage level of the voltage signal S4 is surely reduced to the value (H level) lower than the voltage of the power supply VCC by the threshold voltage Vth of the transistor 26. When the capacitor C1 is discharged, the voltage level of the voltage signal S4 falls from the H level, and the output time of the reset signal POR1 is adjusted.

Further, in this embodiment, since the inversion level of the inverter 23 is set to the power supply VCC side, the L level is set to a low level based on a small decrease in the voltage level of the voltage signal S4 of the capacitor C1 from the voltage of the power supply VCC. Reset signal PO
R1 can be reliably output to the internal circuit.

The present invention can be embodied by being arbitrarily modified as follows. (1) In the output circuit 12 of the embodiment, one inverter is provided in addition to the inverters 23 and 27, the inverter is connected to the output side of the inverter 27, and the output signal of the inverter 27 is inverted to generate a reset signal. You may do it.

(2) Instead of the toggle FF 21, a frequency dividing circuit capable of dividing the frequency of the oscillation signal S1 into 1 / N (N is a natural number of 3 or more) may be used. The technical ideas other than the claims that can be understood from the above embodiments will be described below along with their effects.

(A) The power-on reset circuit according to claim 2 or 3, wherein the inversion level of the inverter (23) is set on the high potential power supply (VCC) side. With this configuration, the reset signal POR1 can be reliably output based on a small decrease in the charging voltage of the capacitor C1 from the voltage of the power supply VCC.

[0028]

As described in detail above, according to the present invention,
A reset signal for initial setting of the internal circuit can be surely output.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a power-on reset circuit according to an embodiment.

FIG. 3 is a time chart showing the operation when the oscillation signal has a low frequency in the power-on reset circuit of FIG.

FIG. 4 is a time chart showing the operation when the oscillation signal has a high frequency in the power-on reset circuit of FIG.

FIG. 5 is a circuit diagram showing a conventional power-on reset circuit.

[Explanation of symbols]

 1,11 Oscillator 2,12 Output circuit 21 Toggle flip-flop as frequency divider circuit 22 NAND circuit as adjustment circuit 23 Inverter C1 capacitor F1, S1 Oscillation signal GND Ground as low potential power supply POR1 Reset signal S2 Frequency division signal VCC High Potential power supply

Claims (3)

[Claims] 1. A power for supplying a high potential power supply and a low potential power supply as operating power supplies, and outputting a reset signal to the internal circuit when the both power supplies are turned on, thereby initially setting the internal circuit to a predetermined state. An oscillator for outputting an oscillation signal having a frequency corresponding to the voltage of the power supply supplied in the on-reset circuit, and detecting the frequency of the oscillation signal, and resetting the reset signal when the detected frequency is less than a predetermined frequency. A power-on reset circuit including an output circuit that outputs a signal. 2. The output circuit inputs a capacitor charged and discharged based on an oscillation signal of the oscillator and a charging voltage of the capacitor, and when the charging voltage is less than a predetermined value, the reset signal The power-on reset circuit according to claim 1, further comprising an inverter for outputting the. 3. The frequency divider circuit for outputting a frequency-divided signal obtained by frequency-dividing a frequency of an oscillation signal of the oscillator, the output circuit, and a charging time and a discharge time of the capacitor based on the oscillation signal and the frequency-divided signal. The power-on reset circuit according to claim 2, further comprising an adjusting circuit for adjusting time.