JPH0863446A - Flash memory and processor connected to the same - Google Patents

Abstract

PURPOSE: To provide an information processor which includes the processor and flash memory and to eliminate the need for external logic for processing the control signal and erasure/program end signal of the flash memory outside. CONSTITUTION: The processor 101 is provided with interface signal terminals for the chip select signal 106, output enable signal 107, and erasure/program end signal 111 of the flash memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device including a flash memory and a microprocessor.

[0002]

2. Description of the Related Art An example of prior art relating to flash memory is described in "Hitachi, HN28F1600 Series Provisional Specification, '92 .9", pp.1-20, published in December 1993. The characteristic data used for the description of the flash memory is based on this document.

The flash memory is a kind of semiconductor memory, and its characteristic is non-volatile. Non-volatile means that the stored contents are retained even when the power is cut off. Compared with another typical semiconductor memory, DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), where stored data cannot be retained when the power is cut off, this is a characteristic difference. is there.

Read, write, and other operations of the flash memory are given in a command format. For example, the first cycle when performing a read operation is 0000H (H is 16
The first cycle when performing a sector erasing operation (an operation of erasing all data in one sector) is 202
It is defined as 0H.

Next, the operation after the command is issued concerning the sector erase and the program operation will be described.

Completion of the sector erase operation is notified to the outside of the flash memory LSI by a transition from the L level (L = low potential) to the H level (H = high potential) of the READY pin which is an output pin of the flash memory LSI. . The minimum value for the completion of the operation is 7 milliseconds and the maximum value is 200 milliseconds, and there are variations within that range. In addition, there is a possibility that the sector erase operation is attempted but it physically fails and the operation is completed. The distinction between success and failure is to check the status information on the data line after the transition of the READY pin from L level to H level. It can be done by reading via.

The program operation is a write operation of a 16-bit (or 8-bit) value, and the completion of the operation is similar to the above with the transition of the READY pin, which is an output pin, from the L level to the H level. Notify outside the LSI. The minimum time for completing the operation is 5 microseconds (micro = 10 to the 6th power), and the maximum value is 20.
It is defined as 0 microseconds, and there are fluctuations in it.
In addition, there is a possibility that the program operation is attempted but it physically fails, and the operation is completed. As in the previous case, the success / failure is distinguished by displaying the status information after the transition from the L level to the H level of the READY pin. It can be determined by reading out via the data line.

The fluctuation range (maximum value-minimum value) of the time until the completion of the above two operations is much larger than that of one clock time of a microprocessor (hereinafter simply referred to as a processor) is 10 to 100 nanoseconds. , It does not have a requirement as a clock synchronization signal for the processor. Here, the clock synchronization signal is a signal which is determined to be 1 or 0 and does not take an intermediate value as long as it is referred to in a specific phase of the clock.

On the other hand, the description of the external terminals of the conventional processor is described in, for example, "i486 Processor User's Manual, 1989" (Intel i486 Microprocessor, 1989).
p.10-17, pp.100-103.

According to the "i486 Processor User's Manual", the i486 processor has 30-bit address external terminals A31-A2 and 32-bit data external terminals D31-D0 as a processor bus. It is also described that it has external input terminals RDY # and BRDY #. This signal is asserted (signal becomes logical value 1) in synchronization with the completion of the access operation (bus read / bus write) of the processor external circuit, and the processor starts the next bus cycle by receiving this information. You can However, this bus interface does not have the feature of matching the external bus interface of a particular memory. Also, with this interface, low-speed memory can be connected by extending RDY #, BRDY #.
The next external bus operation cannot start until BRDY # is returned.

Conventionally, the processor has an interrupt operation. Interrupts are sometimes called exceptions or traps, but they mean that control is forcibly transferred to a specific address during normal processor instruction execution. The main cause of an interrupt is mainly due to an external event such as assertion of a processor interrupt input terminal, or when an instruction or data access fails due to the operation of a memory protection mechanism.

In the example in the user's manual, INT
Input terminals that generate interrupts R and NMI are defined, but they must be synchronization signals related to the clock signal (CLK terminal).

The relationship between the flash memory and the interrupt operation is described in Japanese Patent Laid-Open Publication No. 61-123096 (filed on Nov. 20, 1984). According to this publication, a ready / busy signal indicating the erase / write operation of the nonvolatile semiconductor memory device is output to the CPU. Then, it is described that an interrupt occurs in the CPU when the nonvolatile semiconductor memory device finishes the erase / write operation.

[0014]

Within the scope of the prior art documents, it was not sufficiently practicable for the purpose of connecting the flash memory and the processor with the minimum external logic.

One of them is that the conventional literature does not describe the individual signal terminals necessary when all the signal terminals of the flash memory are directly connected to the processor.
In order to realize a system including flash memory,
Additional logic is required outside the processor.

Using a conventional processor, for example, requires additional logic, such as an address decoder, external to the processor to translate the processor's external bus access operations into flash memory access signals.

On the other hand, since the time uncertainty of the signal indicating the erase / write operation of the flash memory is larger than the period of one clock, it cannot be used as the clock synchronization input signal of the logic circuit. In that case, an asynchronous / synchronization conversion circuit is required externally. The problem to be solved by the present invention is to eliminate the above two external logics.

[0018]

A processor LSI and a flash memory LSI are included in an output terminal of the processor LSI, and at the same time an input terminal of the flash memory LSI, and a logical value of 1 when the processor accesses the flash memory. A first control signal that is an output terminal of the processor LSI and an input terminal of the flash memory LSI at the same time, and a second control signal that directs a signal drive to a data terminal of the flash memory. And an output terminal of the flash memory LSI and an input terminal of the processor LSI at the same time, which notifies completion of programming or erasing of the flash memory LSI, and an interrupt of the processor is generated by issuing the signal. It has three control signals.

[0019]

[Operation] As pointed out in the section of the problem to be solved by the invention,
No additional logic is needed external to the processor. Other effects will be clarified through the description of the embodiments.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a diagram of a processor and a flash memory in an information processing apparatus used in the present invention. 101
Is a processor, 102 is a flash memory, 103 is a 30-bit address signal of the processor, 104 is a 32-bit data signal of the processor, 105 is a main memory, 10
6 (/ FCE) is a chip enable signal of the flash memory, 107 (/ FOE) is an output enable signal of the flash memory, 108 (/ FUW) is an upper byte write enable signal of the flash memory, and 109 (/ FL).
W) is a low-order byte write enable signal for the flash memory, 110 (/ FBYTE) is a 16-bit / 8-bit mode selection signal for the flash memory, and 111 (FRD).
Y) is a flash memory ready signal. In addition, "
/ "Indicates a negative signal line. In this device, 110 is fixed to H level and the flash memory 102 is operated in 16-bit mode. 111 is erased or programmed is completed. Sometimes it transits to H.

Reference numeral 112 is a state control circuit for the main memory bus. Reference numeral 113 is a control signal sent from the processors 101 to 112, in which bus start (/ BS) is included.
And a read / write identification signal (R / W). Reference numeral 114 is a transfer completion (/ RDY) signal sent from 112 to 101.

FIG. 2 is an example of a timing chart in the information processing apparatus using the present invention. 103, 104, 106, 1
The values of signal lines 07, 108, 109, and 111 are shown. This timing chart will be described in order of time.

Period 201: No operation.

Periods 202-204: A sector erase command is transmitted from the processor 101 to the flash memory 102.

Period 205: FRDY111 transits to L level.

Period 206: The processor 101 is accessing the main memory 105 even while the FRDY 111 is L. At this time, the flash memory 102 is in the sector erase operation, but it should be noted that the flash memory 102 does not need to use the address 103 and the data bus 104 during that period.

Data bus 1 in the latter half of period 207: 207
The data from the main memory 105 is transferred to 04.

Period 208: No operation is performed.

As can be seen from the dashed lines drawn on the time axis of period 208, the processor bus operations can make multiple bus accesses during periods 206-208.

Period 209: FRDY (111) transits to H level. This means that the erasing process for one sector started from 205 is completed.

Period 210: Processor 101 / FCE (10
6), / FOE (107) is set to L to instruct the data pin 104 to read the erase status of the flash memory 102. At the same time, the processor 101 outputs an address, but this is an address to be output due to the bus operation format, and it has no meaning.

Period 211: The erase status of the flash memory 102 is read to the data pin 104.

Period 212: No particular operation.

FIG. 3 shows an internal block diagram of the processor 101. The internal block of the processor 101 is an instruction processing unit 30.
1, memory address management unit 302, interrupt processing unit 30
3, a flash control unit 304, and a main memory bus control 305. From the instruction processing unit 301 to the memory address management unit 3
02 has access address 311 and access start signal 3
12, the access type signal 313 is transmitted. A flash control activation signal 314 and a flash control type signal 315 are transmitted from the memory address management unit 302 to the flash control 304. Memory address management unit 30
2 to main memory bus control 305 access address 31
6, the main memory bus start signal 317, and the main memory bus control type signal 318 are transmitted. A flash memory-based interrupt request signal 319 is transmitted from the flash control unit 304 to the interrupt processing unit 303, and a flash memory-based interrupt approval signal 320 is transmitted from the interrupt processing unit 303 to the flash control unit 304. Interrupt processing unit 30
The interrupt signal 321 is transmitted from 3 to the instruction processing unit 301, and when the interrupt signal 321 is issued, it has an effect of interrupting the instruction execution being executed at that time in the instruction processing unit.

FIG. 4 shows a block diagram of a portion inside the flash control unit 304 for processing the FRDY (111) signal.

Reference numerals 401, 402, and 403 denote D-type flip-flops, which are triggered by a clock signal and taken into a value flip-flop of an input signal (D in the figure), and at the same time, output the value to an output signal (Q in the figure). . The clock signal is not shown.

The D-type flip-flop 401 converts FRDY (111), which is an asynchronous signal, into a synchronous signal, and functions as a synchronization conversion circuit. FRDY (11
1) does not satisfy the condition as a synchronization signal because the fluctuation width of the transition timing is larger than one processor clock, but the output of 401 is a synchronization signal.

Next, 404 is a 2-input AND gate,
Outputs the logical product of input signals. An inverter 406 outputs the inverted value of the input signal. When 111 changes from L to H, that is, at the beginning of the period 209 in the example of FIG. 2, the right input of the two-input AND gate 404 has a falling edge delayed by three flip-flops and the left input of 404. Is applied with a rising edge delayed by one flip-flop, and as a result, 404 outputs a pulsed signal to the signal line 407 as shown in the timing diagram 408.

The signal line 407 is input to the set terminal of the set / reset flip-flop 405 to set (set to 1) the interrupt request signal 319. The interrupt request signal 319 is sent to the interrupt processing unit 303, and after determining the priority relationship with other interrupts, it is sent to the instruction processing unit 301. When 321 is sent to the instruction processing unit 301, the present instruction execution is temporarily interrupted, and an effect of shifting to interrupt processing is provided.

When transitioning to the interrupt processing, the flash memory-caused interrupt acceptance signal 320 returned from the instruction control unit of the processor is input to the reset terminal of the set-reset type flip-flop 405, and the flash memory-caused interrupt request signal 319 is reset (set to 0). To do).

FIG. 4 shows the FRDY (11
The flowchart of the part regarding the program of 512 bytes is shown among the interrupt processing started when 1) changes to H. Here, one sector of the flash memory 102 consists of 512 bytes. The flash memory 102 is a floppy disk from software.
It is treated as a secondary memory such as a hard disk. According to the custom in software in that case, when writing to the flash memory 102, data for one sector is first prepared in the main memory 105, then one sector of the flash memory 102 is erased, and then data for one sector is mainly written. Write from the storage 105 to the flash memory 102. This write operation is achieved by the program operation of the flash memory 102. Since the data width of the flash memory 102 is 2 bytes, repetitive operations are required for programming 512 bytes. The interrupt handling must be properly designed in order to achieve the repetitive operation and at the same time, the processor 101 to perform different processing during each period during the repetition.

As a prerequisite for the explanation of the flowchart, a variable byte count (byte count) on software.
Indicates the position of the byte being processed in 512 bytes, and the variable byte count is set to 0 at the start of the program processing of 512 bytes. A variable called a transfer completion flag means that all 512 bytes of the program have been completed and is set to 0 at the start of processing.

Process 501: Start. Go to processing 502.

Process 502: It is judged whether or not the corresponding interrupt is caused by the completion of the program. If not caused by program completion, move to another process (not discussed here). If it is caused by the completion of the program, go to processing 503.

Process 503: The status of the flash memory 102 is read out via the data line 104. Process 5
To 04.

Process 504: It is judged whether or not the status indicates a program failure. If it indicates failure, go to processing 508. Otherwise, go to processing 505.

Process 505: Variable byte count (bytecou
nt) is 512 or more. If it is 512 or more, go to processing 509. Otherwise, go to processing 506.

Process 506: Variable byte count (bytecou
2) to nt). Go to processing 507.

Process 507: Program the flash memory with 2 bytes. The contents of the operation will be described with reference to FIG.
Go to process 510.

Process 508: Perform error processing. Specifically, the corresponding sector of the flash memory 102 is made unusable. A software-like procedure for making a certain sector unusable is known for a hard disk. Go to process 510.

Process 509: 1 is set to the transfer completion flag (variable on software). For example, this transfer completion flag will be referred to when it is desired to start the next 512-byte transfer. Go to process 510.

Process 510: Return to the program execution point when the interrupt occurred. Go to processing 511.

Process 511: End of process.

During the program time of the flash memory, that is, during each repetitive operation for programming 512 bytes, or during the erase time of the flash memory, the bus of the processor is free and the processor can perform another process. . This is the same as that explained in the period 206-208 of FIG.

FIG. 6 shows a timing chart of the operation itself of the program operation 507. Signal lines 103, 104, 106,
The values of 107, 108, 109, 111, 113 and 114 are shown. 2 bytes of data are transferred from the main memory 105 to the flash memory 10 by the operation within the range of this timing diagram.
Transferred to 2.

Period 601: No operation, period 602: Processor 101 to flash memory 1
A first command indicating a program operation is sent to 02.

Period 603: The second command of the program operation is sent from the processor 101 to the flash memory 102. The second command is an address.

Period 604: / BS (113) transits to L level and R / W is at H level. That is, the processor 101 is reading the main memory 102.

Period 605: Continuation of the period 604.

Period 606: The data read from the main memory 102 is transmitted to the data bus 104. Further, L-level / RDY (114) meaning that data is ready is transferred from the main memory bus state control circuit 112. Upon receiving the transition of / RDY to L level, the processor 101 changes / FCE (106) to H level. As a result, data transfer, which is the third command to the flash, is performed.

Period 607: F due to the operation of period 606
RDY (111) changes to L level. This L level is L level during the program period, and then returns to H level (similar to period 205-209).

Period 608: Another bus operation is performed in parallel with the program processing.

In the above description, the transition of FRDY111 to the H level has been described as causing an interrupt of the processor 101, but as another possibility, FRDY1
The transition of 11 to the H level can be reflected in the change of the register value that can be read from the processor 101. For example, using FIG. 4, it is possible to configure that the output value 319 of the flip-flop 405 is transferred to the arithmetic register of the processor according to a specific instruction of the processor.
If you are a logic design expert, you can do it without difficulty.

FIG. 7 shows a block diagram of another embodiment using the present invention. 701-714 is 101-11, respectively
It is composed of the same items as 4. However, unlike the 102, the flash memory 702 has a sector program operation. In the sector program operation, data of one sector, that is, 512 bytes, is continuously stored in the temporary data register inside the flash memory, and then the program processing is collectively performed inside the flash memory.

715 (/ FSTB) is a flash data strobe signal, which is asserted (the signal line is 1 when the sector program operation is performed, in synchronization with data fetching).
To become).

A timing diagram for the device described in FIG. 7 is shown in FIG. FIG. 8 shows a process when programming data for one sector.

The period 801: / FCE (706) is transited to the L level, indicating that the flash memory 702 is in the selected state.

Periods 802 and 803: The processor 701 notifies the flash memory 702 that command transfer has been performed to the flash memory 702 and the sector program operation has started.

Period 804: The address is designated as 703,
At the same time when the data read from the main memory 705 is transmitted to the main memory bus 704 and the data read from the main memory 705 is transmitted, the / RDY signal (714) transits from the H level to the L level, and the arrival of the data to the processor 701. Notice. / R
The / FSTB signal (715) is generated from the DY signal (714), and the contents of the data line (0:15) at that time are transferred to the internal data register of the flash memory 702. This is called the first data transfer.

Period 805: 4 is added to the address bus 703, and the same operation as in period 804 is performed. This is called the second data transfer.

Period 806: The 25th operation is repeated.
The sixth data transfer is performed. 1 at the end of period 806
Data for sectors is prepared.

Period 807: No operation is performed.

Period 808: / FLW (708), / FUW (7
09), an L level pulse is output and the sector program is performed. FRDY (711) transits from 1 to 0.

Period 809: No operation is performed.

FIG. 9 shows another embodiment using the present invention.
FIG. 9 shows the processor 101 and the flash memory 102 formed by the same semiconductor element 912 as compared with FIG. 901-911 has the same functions as 101-111, and no new explanation is necessary.
2, 4, and 5 can be applied to the apparatus of FIG. 9 as they are. The 2-byte program operation (507) in FIG. 5 is observed as a read access to the main memory 905 from the outside of the processor 920.

FIG. 10 shows another embodiment using the present invention. FIG. 10 shows two flash memories 1002 and 100.
The feature is that 3 is present. 1001 is a processor. Each of these flash memories is provided with 16 data pins, and by connecting two memories in parallel in the bit direction, 32-bit data access becomes possible. The data bus 1009 connects DATA (0:15) (1009) of the processor 1001 to the flash memory 1002. Data bus 1
010 is DATA of the processor 1001 (16:31)
(1010) is connected to the flash memory 1003.

Further, the flash memories 1002 and 1003
Is different from 102 in the FDRY output circuit,
It is an open drain output. In other words, focusing attention on the flash memory 1002, the FRDY terminal is driven to the L level by the N-channel MOS transistor 1004 and can be driven to the L level, but not to the H level. N-channel MOS transistor 10
05 is the same as 1004. The FRDY signals of the two flash memories are connected to the same node 1008,
Further, the resistor 1006 is connected to the node 1008 and the positive power source 100.
Tie 7 Further, FRDY promises that the drive operation to the L level is performed when the operation is not completed. Since the open drain output is used, the FRDY output of at least one of the two flash memories is L level.
When driving to the level, the node 1008 drops to the L level, and when both FRDY outputs are not driven, the resistor 1006 causes the node 1011 to go to the H level. From this, when the processor receives the H level in 1008, the two flash memories 100
It can be confirmed that both 2 and 1003 have completed the operation.

FIG. 11 shows a diagram of still another information processing apparatus using the present invention. 1101-1114 is 10 each
1-114, and the description of each is omitted. This figure is characterized by 11 flash memories.
02a and 1102b, and 1111a and 11
Reference numeral 11b is an erase and program completion signal for the respective flash memories (1102a, 1102b). The processor 1101 inputs 1111a and 1111b as separate input terminals. Therefore, one control terminal is increased as compared with the processor of FIG.

[0079]

In an information processing apparatus including a processor and a flash memory, a logic for notifying the processor of erase or program completion information generated by a flash memory added outside the processor, or a processor added outside the processor. The logic for converting the external bus access operation into the flash memory access signal is unnecessary.

The presence of the synchronization circuit in the portion of the flash memory that receives the erase or program completion signal ensures the reliable synchronization operation of the processors.

In one of the embodiments, the processor can know the completion of the operation from one input terminal indicating the completion of the operation by directly connecting the signals indicating the erasing or programming of the plurality of flash memories. .

[Brief description of drawings]

FIG. 1 is a diagram of an information processing apparatus using the present invention.

FIG. 2 is an example of a timing diagram in an information processing apparatus using the present invention.

FIG. 3 is an internal configuration diagram of a processor 101.

FIG. 4 is a configuration diagram of a portion inside the flash control unit 304, which processes a FRDY (111) signal of the flash memory.

FIG. 5 shows the FRDY (111) signal of the flash memory
7 is a flowchart of an interrupt process that occurs in the processor 101 when it changes to H.

FIG. 6 is a timing diagram of program operation 507.

FIG. 7 is a diagram of another information processing apparatus using the present invention.

8 is an example of a timing diagram in the information processing apparatus of FIG.

FIG. 9 is a diagram of another information processing apparatus using the present invention.

FIG. 10 is a diagram of another information processing apparatus using the present invention.

FIG. 11 is a diagram of another information processing apparatus using the present invention.

[Explanation of symbols]

101-processor, 102-flash memory, 10
3-processor 30-bit address signal, 104-
30-bit data signal of processor, 105-main memory, 106-chip enable (activation) signal of flash memory, 107-output enable signal of flash memory, 108-write enable signal of upper byte of flash memory, 109-flash Write enable signal for lower byte of memory, 110-16 bit / 8 bit mode select signal for flash memory, 111
-Flash memory erase and program completion signal,
112-main memory bus state control circuit, 113-main memory bus control signal, 114-main memory bus transfer completion signal, 20
1 to 212-period, 301-instruction processing unit, 302-memory address management unit, 303-interruption processing unit, 304
-Flash control unit, 305-Main memory bus management unit, 31
1-access address, 312-access activation signal, 3
13-access type signal, 314-flash control activation signal, 315-flash control type signal, 316-access address, 317-main memory bus activation signal, 318-
Main memory bus control type signal, 319-flash memory origin interrupt request signal, 320-flash memory origin interrupt approval signal, 321-interrupt signal, 401 to 4
03-D type flip-flop, 404-2 input AND gate
405-set reset type flip-flop, 40
6-inverter, 407-set signal, 408-timing diagram, 501-start of process, 502 to 510-process, 511-end of process, 601 to 608-period,
701 to 714 to 101 to 114, respectively,
715-Data strobe signal of flash 801 to 809-same as 901 to 911-101 to 111 respectively, 912-semiconductor device including processor and flash memory, 1001-processor, 1002, 1003-flash memory, 100
4, 1005-N-channel MOS transistor, 100
6-resistor, 1007-positive power supply, 1008-flash memory erase and program completion signal, 1009, 1
010-data bus, 1101-processor, 1102
a, 1102b-flash memory, 1103 to 11
Same as 09-103 to 109, 1110a, 1110
b-Flash memory 16-bit / 8-bit mode selection signal, 1111a, 1111b-Flash memory erase and program completion signal, 1112 to 1114
Same as -112-114.

Claims (3)

[Claims] 1. A processor LSI, a flash memory LS
I, which is an output terminal of the processor LSI and which is also an input terminal of the flash memory LSI, and which has a first control signal which becomes a logical value 1 when the processor accesses the flash memory.
It is an output terminal of SI, and at the same time, the flash memory LS
The flash memory LS, which is an input terminal of I and has a second control signal for instructing a signal drive to the data terminal of the flash memory.
It is an output terminal of I and also an input terminal of the processor LSI, and has a third control signal for notifying the completion of programming or erasing of the flash memory LSI, and the interruption of the processor is generated by the notification. A characteristic information processing device. 2. The information processing apparatus according to claim 1,
A clock synchronization circuit is provided in a path for inputting the third control signal inside the processor. 3. An output signal terminal for indicating completion of programming or erasing is provided, and an output buffer of the signal terminal performs an operation of driving only one of a high potential side and a low potential side, so that a plurality of LSIs are provided. A flash memory LSI capable of connecting the output terminals.