TW530199B - Method for reducing the number of computer initial strapping devices and apparatus thereof - Google Patents

Abstract

The present invention discloses a method for reducing the number of initial strapping devices of a computer that includes at least a configuration setting device. The method includes the following procedures: providing a configuration value stored in a non-volatile memory to assert a processor reset signal and a bus reset signal of high-speed peripheral bus during computer power-on or condition reset; retrieving the configuration value from the non-volatile memory once the operating clock of a high-speed peripheral bus reaches its operating voltage and frequency; repeating the retrieving procedure until the most significant bit (MSB) of the retrieved configuration value changes from the first condition to the second condition; asserting the configuration value retrieved from the non-volatile memory to the configuration setting device to setup its configuration; de-asserting the processor reset signal so as to complete the configuration setup of the configuration setting device.

Description

530199 V. Description of the invention (1) The present invention relates to the initial configuration settings of a computer system, and particularly to a method and a device for reducing initial setting components used by a computer.

A typical computer system includes several integrated circuit devices, or electronic chip sets, which can operate in more than one configuration (c ο n f i g u r a t i ο η). A general computer system is designed to use a computer chipset in a specific configuration. Therefore, when the user turns on the computer or resets (reset) the computer chipset must be initialized or set. The computer chipset also has certain operating parameters that must be set properly before the first CPU cycle is issued, so these parameters cannot be set during normal CPU configuration cycles. Such a chip usually provides an electronic signal to the chip for initial setting when the computer is turned on or reset, and the circuit system used to generate such a signal is often called a initial setting device (strapping device). Jumpers and DIP switches are two examples of initial setting components commonly used to set the initial configuration of a computer. In this case, several chip signal pins must be allocated to receive the configuration signal generated by the initial setting component immediately when the power supply starts.

However, a computer motherboard using such initial setup components requires the cost of a car owner and consumes a lot of space. In addition, integrated circuit chips cannot free up too many dedicated pins to receive configuration signals generated by the initial setting components. Therefore, during the startup process, certain pins of the chip can be used to perform certain functions. The subsequent normal operation process is used to perform another function. In other words, these pins are multiplexed pins, and the data pins of the chip are generally used as such multiplexed pins. For computers using Double Data Rate (DDR) technology, if

530199

Some problems will occur when the pin is connected to the initial setting component, because the DDR data pin must be maintained at a stable voltage during the DDR data bus is idle. Similarly, data pins that conform to the peripheral component interconnect (hereafter referred to as PCI) specifications cannot be used to receive the initial setting signal. This is because the PC I bus is a common bus. If there is more than one PC, If the I device uses the same pc j data pin to receive the initial setting signal, a contention problem will occur. Therefore, the above-mentioned initial setting elements are no longer attractive due to the static setting characteristics of the currently available initial setting elements. Strictly based on this, the present invention proposes a configuration structure for initializing operating parameters of a computer system, but without the limitation of the conventional technology. It is an object of the present invention to provide a method and device which can be used to reduce the initial setting components used in a computer. Another object of the present invention is to provide a method and device that can be used to effectively set the initial computer configuration before the CPU reset signal is deasserted. To achieve the above-mentioned object, the present invention provides a method for reducing the initial computer setting. The computer has at least one settable configuration device. In short, the method provided by the present invention includes the following steps. First, a configuration is provided. Values are stored in non-volatile memory to reduce the computer's initial setting components. During the computer power-on, start-up, and reset states, an assert processor reset signal and a bus reset signal for the high-speed peripheral bus are issued, where the high-speed peripheral bus is included in the computer. When operating a high-speed peripheral bus

530199 V. Description of the invention (3) When the pulse (c 1 〇ck) reaches its operating voltage and frequency, take out the configuration value from the non-volatile memory, and repeat this extraction step until the most significant bit of the obtained configuration value. The value of the Most Significant Bit (MSB) is changed from the first state to the second state. Then, the configuration value obtained from the non-volatile memory is sent to the above-mentioned configurable configuration device to configure its configuration, and then the processor reset signal is retracted to complete the configuration configuration of the configurable configuration device. The device for implementing the above method includes at least a low-speed peripheral bus, non-volatile memory, and a bridge logic. Non-volatile memory disks_ are connected to the logic respectively to the low-speed peripheral bus. The non-volatile memory has a reserved space for storing configuration values of at least one configurable device. The bridge logic also includes at least a latch and a multiplexer. The latch is controlled by a configuration enabling signal, and outputs the above configuration value to configure the configuration of the settable configuration device. The multiplexer has an output port coupled to the latch, and sends the configuration value stored in non-volatile memory from the output port during the power-on and reset state of the computer according to a state of a ready signal. To the latch, and in other operating states, the program configuration information of an execution period is sent from the output port to the latch. In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, a detailed description is provided as shown in FIG. 1A. A block diagram of a computer system as an example;

530199 V. Description of the invention (4) Figure 1B is a block diagram of a computer system according to another illustrative example; Figure 2 is a block diagram according to a preferred embodiment of the present invention; Figure 3 is a diagram illustrating the configuration initialization steps of the present invention Flow chart; FIG. 4 is a timing diagram of related signals in the initialization period of the present invention. [Label description] 1 0 0 ~ computer system; 1 0 0 '~ computer system; 1 0 1 ~ processor; 1 0 3 ~ random access memory; 1 0 5 ~ system bus; 1 0 7 ~ second Bridge logic; I 0 9 ~ First bridge logic; 111 ~ Hard disk drive; II 3 ~ I / O device; 11 5 ~ High-speed peripheral bus; 11 7 ~ I / O device; 11 9 ~ Non-volatile memory ; 1 2 1 ~ low-speed peripheral bus; 1 2 3 ~ clock generator; 1 2 5 ~ point-to-point bus; 1 2 7 ~ third bridge logic; 1 50 ~ computer motherboard; 2 0 1 ~ more Multiplexer; 2 03 ~ latch; 2 05 ~ logic reverse brake; 2 07 ~ logic reverse AND brake; 2 0 9 ~ multiplexer input 珲; 2 11 ~ multiplexer input 珲; 213 ~ acquisition Ready signal (STRP_RDY); 215 ~ Configuration enable signal (C0NF_ENA); 217 ~ Run-time programming configuration write signal (C0NF_WR); 219 ~ Multiplexer output port; 221 ~ Combined logic circuit; 223 ~ Latch Device output. [Example] As shown in FIG. 1A, the computer system 100 is composed of a computer motherboard 150

0702-6554TWf; 90P65; Lin.ptd page 7 530199

'It includes a processor 101, a random access memory (RAM) 103, and a clock generator U3, each of which is coupled to the system bus 105. The second bridge logic is 107, which is also lightly connected to the system bus. 05, so that the system bus 105 can lightly connect one or more input and output buses. In this example, 'this sink 3 bus Is a high-speed peripheral bus 丨 丨 5, such as pc I bus 115 'that is,' the second bridge logic 1107 is a system-to-PCI bus bridge (also known as the no bridge bridge), As shown in the figure, the North Bridge 107 bridges the system bus 105 to the pc I bus 丨 5. The hard disk drive n is coupled to the PC I bus 115 to store information and instructions required by the processor.

The input / output device 11 3 is also coupled to the PC I bus 11 5 to input and output data and control information from the processor 101. The input / output device i j 3 may include devices such as a display card and a network card. Figure 丨 B is a block diagram of a computer system illustrating another example.

With continued reference to Figure 1, the p CI bus 115 is bridged to a low-speed peripheral bus 121 via the first bridge logic 109. In this example, the low-speed peripheral bus 121 is an industry standard architecture (incjustry Standard Architecture, hereinafter referred to as The first bridge logic 109 is a PCI-to-ISA bus bridge (also known as a south bridge). The clock signals of the PCI bus 115 and the ISA bus 121 are provided by the clock generator 1 2 3. As shown in the figure, the non-volatile memory 11 9 is coupled to the ISA bus 1 2 1 to store static information and instructions required by the processor 1 0 1. In this example, the non-volatile memory 11 9 is a Fast flash (f 丨 ash) memory or electronic erasable programmable read-only memory (EEPROM). The input / output device 11 7 can also be connected to the I S A bus 1 2 1 to input from the processor 1 0 1

0702-6554TWf; 90P65; Lin.ptd page 8 530199 V. Description of the invention (7) and output to output port 2 1 9. The latch 2 03 is controlled by a configuration enabling signal 'CONF-ENA 215, which is a combination logic composed of a logic gate NO2 and a logic gate 207 Output from circuit 221. As shown in the figure, one input pin of logic inverse gate 207 is directly connected to STRP-RDY 213, and the other input pin of logic inverse gate 207 is coupled to an execution via logic inverse gate 2.5. The time-programmed configuration write signal, C0NF-WR 217. Except for the state issued by STRP-RDY 213 and the CONF-WR 217 retracted, the CONF-ENA 215 will be initiated and issued in the other states. During the period when both WR 217 are issued, no matter what the input port of the latch 203 is, it will be output to the PC I bus 11 5. Next, reference is made to Figs. 3 and 4 to further explain the operation flow of the present invention. The first step must first be a basic input / output system (B a s i c

Input / Output System (BIOS) area reserves a 64-bit memory space. This reserved space is defined as the hexadecimal address range of the above non-volatile memory 1 1 9 from FFFFFFD0 to FFFFFFD7, and the configuration value The MSB value is planned as a logical π 〇 π to indicate the initial value acquisition status, and then the above set of traumatic values are stored in the non-volatile memory 119-6 64-bit memory reserved space. When the computer system 1000 is turned on or reset (step 3 〇1), a processor reset signal CPURST # (# is a low-level valid signal) and a bus reset signal of the PCI bus 115 are issued first. pci RST # (step 303). In step 305, PCIRST # will be collapsed after a short time as shown in Figure 4. When the system clock signal SYSCLK of system bus 105 and the PCI clock signal PCICLK of PCI bus 115 are stable, it will reach the

0702-6554TWf; 90P65; Lin.ptd page 10 530199, description of the invention (8) When the voltage and frequency are applied, an internal signal FWT_RD of the South Bridge 10 will be issued.

Once the FWT-RD is issued, a pc! Read transaction (rea (i transaction) is started to fetch data from the hexadecimal address FFFFFFD〇 until all 64-bit configuration values are read successfully (step 3 〇7). In step 3 ^ 09, if the MSB value of the obtained configuration value is still logical " Γ, then the reading of the parent must be repeated until the MSB value of the obtained configuration value changes to logic. 'If the MSB value of the acquired configuration value has become logical π 〇π, then the internal signal FWT — RD is retracted. At step 31 1, STRp_RDY is issued to latch the acquired configuration value in the latch 2 〇3 output port. In step 3 1 3, the flash-locked configuration value is transmitted to North Bridge 1 07. In step 3 15 when North Bridge 1 0 7 receives the configuration value and latches it at After the configuration register (not shown in the figure), the internal signal nb — sTRP — RDY of North Bridge 1 107 will be issued. Finally, the CPU reset control unit (not shown) in North Bridge 1 0 7 starts. Action 'and after the configuration of the configurable configuration device including the processor and the computer chipset is completed, the C PURST # (step 317). [Effect of the invention]

In summary of the above, the present invention discloses a method and a device for reducing the initial setting components of a computer, mainly by using the configuration values of a settable configuration device in a computer to be stored in non-volatile memory to reduce the use of the initial settings Components' and can effectively set the computer's initial configuration before the processor reset signal is retracted. Although the present invention has been disclosed as above with a specific embodiment, it is only for easy explanation of the technical content of the present invention, and does not limit the present invention to this embodiment in a narrow sense. Any person skilled in the art will not depart from the spirit of the present invention.

0702-6554TWf; 90P65; Lin.ptd page Η 530199

0702-6554TWf; 90P65; Lin.ptd Page 12

Claims (1)

^ 0199 6. Scope of patent application1. A method for reducing the initial setting of a computer and at least one configurable configuration device. The method has the following steps: (1) providing -M state value stored in H. (b) shoot out One luli. . The non-volatile memory; the bus reset signal, which is one of the high-speed, real Ami peripheral bus; 8. The edge bus is included in the computer (C) when an operation clock reaches Its working volatile memory takes out the configuration value, where \ = frequency 'works from the clock that is not according to the operating clock; the peripheral bus line in the middle of the 30th (d) repeats step (c) until a Obtaining a unary value changes from the -first-state to a second state: ,, /, The effective bit of the round can be sent to the two Λ Λ to configure the configurable (status) The configuration of the device; and the configuration of the device. The method of reducing the initial setting components of the computer as described in item 1 of the patent scope is as follows: The above step (C) includes at least the following Steps: When the operating clock and frequency of the high-speed peripheral buses reach the operating voltage and frequency, retract the bus reset signal of the high-speed peripheral buses; and take out the configuration values from the non-volatile memory. 4 0.. + ^ Μ Fang J In the above step (e) of at least:: Initial setting off a small computer device 3. The scope of the patent f steps of the configuration described in item 1 has been achieved in a first bridge logic latch collar 0702-6554TWf; 90P65; Lin.ptd 530199 6. Scope of patent application 2. Non-volatile memory, coupled to the peripheral bus. Sexual memory has a reserved space to store the settable value, state value; and At least one set of mind ring is connected to the logic device, to the peripheral bus, the bridge logic device: the latch is controlled by the-configuration enable signal, the Xiao latch outputs the set of sad values to configure the The configuration of the configuration device can be set; and a multiplexer having an output port coupled to the latch, the multiplexer can obtain a state of a ready signal when the computer power is on and reset The configuration value stored in the non-volatile memory is sent from the input port to the latch, and the program configuration information of an execution period is sent from the output port to the latch in other operating state periods. Device. 8. The device for reducing the initial setting components of the computer as described in item 7 of the scope of the patent application, wherein the above reserved space is defined as the hexadecimal address range of the nonvolatile memory & FFFFFFD0 to accommodate the above configuration value. 9 · The device for reducing the initial setting components of the computer as described in item 7 of the scope of the patent application, wherein the configuration enable signal will be Was started to issue. I 〇 • The device for reducing the initial setting components of the computer as described in item 7 of the scope of the patent application, wherein the peripheral bus / IS A bus described above. II. The device for reducing the initial settings of the computer as described in the scope of the patent application, wherein the bridge logic device is a PCI-to-ISA bus bridge 0702-6554TWf; 90P65; Lin.ptd Page 15 530199 0702-6554TWf; 90P65; Lin.ptd page 16