JPH0863142A - Image processing method and its device - Google Patents

Abstract

PURPOSE: To provide an image processing method and device capable of chang ing over dot clocks having different frequencies as necessary. CONSTITUTION: When a frequency-division value '1708' is selected with a switch 104, a dot clock DTCK having a frequency 6.13635MHz is generated. RGB signals are generated in the timing of the dot clock DTCK synchronized with a color sub-carrier from an image display circuit 109 and form s of respective dots to be displayed on a TV monitor become a square. Moreover, a frequency- division '1820' is selected with the switch 104 and then the dot clock DTCK having a frequency 7.15909MHz being the integer multipule of the frequency of the color sub-carrier is generated. Then, RGB signals are outputted in synchronization with the color sub-carrier from the image display circuit 109 to reduce blots of colors of the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus capable of switching dot clocks.

[0002]

2. Description of the Related Art Conventionally, as an image processing apparatus used in a video game machine or the like, a CD-ROM has been controlled by a CPU.
Image data of a background image and a moving image such as a character is transferred from a storage medium such as a ROM to an image memory such as a video RAM, and the video display processor (VDP) calls the image data from the image memory and outputs it as a video signal. There is a known device of the type.

In such an image processing apparatus, an NTSC type TV monitor is widely used as a monitor device for displaying the image data. In this NTSC system, as shown in FIG.
To VDP21, the dot clock DTCK is supplied, and the RGB signal is output from VDP21 to the RGB encoder 31 at the timing of the dot clock DTCK. In the RGB encoder 31, by a predetermined calculation,
The RGB signals are converted into a luminance signal that represents the lightness and darkness of the image and a color difference signal that represents the hue and color saturation. In addition, the RGB encoder 31 is provided with color subcarrier generation circuits 61 to 3.57.
A color subcarrier SC of 9545 MHz is supplied. R
The GB encoder 31 amplitude-modulates the color subcarrier SC by the color difference signal to obtain a carrier color signal, which is multiplexed with the luminance signal and supplied as a video signal VOUT to the TV monitor 41.

By the way, in the above image processing apparatus, if the dot clock DTCK and the color subcarrier SC are not synchronized, the following problems occur. That is, FIG.
As shown in (a) and (b), the phase of the color subcarrier SC and the dot clock DTCK do not match each horizontal one cycle T. For this reason, the RGB data output from the VDP 21 is not synchronized with the color subcarrier SC, iridescent noise due to the color change of each dot is conspicuous, and color bleeding occurs in the image, degrading the image quality.

Therefore, as shown in FIG. 6, the dot clock DTCK and the color subcarrier SC are the same reference clock C.
There is known a device that synchronizes each by generating it based on the output of the LK. In the figure,
The clock generation circuit 71 includes, for example, 14.31818M.
A reference clock CLK of Hz is supplied. Then, the clock generation circuit 71 uses the reference clock CLK to generate a color subcarrier SC with a frequency of 3.579545 MHz.
And an integer multiple of this frequency, 7.15909MHz
And dot clock DTCK.

[0006]

By the way, in the above image processing apparatus, unless the shape of one dot forming the screen of the TV monitor 41 is a square, when the image is drawn by combining these dots, the drawn image is Distortion occurs with the displayed image. For example, as shown in FIG. 7, when the image of the character CHR shown in FIG. 7A is rotated as shown in FIG. 7B, the vertical and horizontal dimensions may change.

The shape of such a dot is determined by the number of display dots in the horizontal direction in the standard display area (the overlapping portion of the horizontal display period and the vertical display period) on the TV screen. Normally, the screen ratio of a home TV is vertical: horizontal = 3: 4. The standard display area of the TV screen has 240 lines. Therefore, if the number of display dots in the horizontal direction is 320, then 240: 320 = 3: 4, and the dots are close to a square. For this, VD
The frequency of the dot clock DTCK supplied to P21 may be 6.13635 MHz.

However, if the above setting is made, the dot clock DTCK and the color subcarrier SC are not synchronized with each other, so that the iridescent noise is generated as described above and the image quality is deteriorated.

Further, since the frequency of the dot clock DTCK is not an integral multiple of the frequency of the color subcarrier SC, blurring is noticeable in the color of the image. However, when the image is not drawn directly, it is more important to make the color blur less noticeable than to make the dots square. For example, image data such as photographs and videos from the outside may be used as a captured image. This is for converting image data such as photos and videos compressed in CD-ROM to CD-RO.
This is performed by reading and reproducing using the M drive and CD buffer. In such a case, unlike when a graphic designer draws as a dot picture,
Since the original picture is read and played back, there is little problem that the shape of the drawn image changes when it is displayed.

The present invention has been proposed in view of the problems of the prior art as described above, and its first object is to reduce the distortion of an image or to reduce the blurring of colors. An object of the present invention is to provide an image processing method capable of handling the above case.

A second object of the present invention is to provide an image processing apparatus which can realize the above image processing method with a simple structure.

A third object of the present invention is to provide an image processing apparatus capable of generating two types of dot clocks without increasing the circuit scale.

A fourth object of the present invention is to provide an image processing apparatus capable of displaying an image corresponding to the above two types of dot clocks.

[0014]

In order to achieve the above object, the image processing method according to the invention of claim 1 is based on the image data read from the image storage means and the color subcarrier, and at the timing of the dot clock. Generate a video signal,
In the image processing method for outputting to a monitor, the shape of the dots displayed on the monitor is substantially eliminated by using a PLL (Phase Locked Loop) circuit based on a reference clock whose frequency is an integral multiple of the frequency of the color subcarrier. It is characterized in that a first dot clock having a square frequency and a second dot clock having a frequency that is an integer multiple of the frequency of the color subcarrier are generated and one of them is output.

An image processing apparatus according to a second aspect of the present invention includes an image data generating circuit which reads out image data from the image storage means and outputs the image data at a dot clock timing.
In an image processing device that has an encoder that generates a video signal based on the image data and a color subcarrier, and outputs the video signal to a monitor, a reference clock generation unit that generates a reference clock, and the reference clock A color subcarrier generating means for generating a color subcarrier based on the first subclock, and a first dot clock having a frequency that makes each dot displayed on the monitor substantially square based on the reference clock; It is characterized by comprising a PLL circuit for switching and outputting either one of the second dot clock which is an integral multiple of the frequency of the carrier wave and the second dot clock.

An image processing apparatus according to a third aspect of the present invention includes an image data generating circuit which reads out image data from the image storage means and outputs the image data at a dot clock timing.
In an image processing device that has an encoder that generates a video signal based on the image data and a color subcarrier and that outputs the video signal to a monitor, reference clock generation means that generates a reference clock, and the reference clock Color subcarrier generating means for dividing and outputting the frequency to 1 / n (n is an integer), and a first dividing unit for dividing and outputting the frequency of the reference clock to 1 / m (m is an integer). Circuit and division value l
A PLL circuit having a second frequency dividing circuit (1 is an integer) for multiplying the frequency of the output signal of the first frequency dividing circuit by 1 and outputting the frequency; and a frequency dividing value of the second frequency dividing circuit. l is the first
The first frequency division for setting the frequency of the output signal of the frequency dividing circuit to a frequency k times (k is an integer) the frequency of the dot clock for making the shape of the dots displayed on the monitor substantially square. A frequency division value selecting means for selecting one of a value and a second frequency division value for making an integral multiple of the frequency of the color subcarrier, and the output signal of the PLL circuit is divided into 1 / k. Then, a dot clock generating means for outputting as the first dot clock or the second dot clock is provided.

An image processing apparatus according to a fourth aspect of the present invention is the image processing apparatus according to the second or third aspect, wherein the image data generating circuit has an H count value corresponding to the first dot clock and the second count value. The H count value selecting means for selecting either one of the H count value corresponding to the dot clock, and the H count value for counting at the timing of one of the first dot clock and the second dot clock. The H count value selected by the selection means and the counted value are compared with each other, and when the count values match, the counting means restarts counting from 0.

[0018]

According to the first aspect of the present invention, when the video signal is output at the timing of the first dot clock, the shape of each dot displayed on the monitor becomes substantially square, and when the dot is drawn and when it is displayed. Image distortion is reduced. Further, when the video signal is output at the timing of the second dot clock, the frequency of the second dot clock is an integral multiple of the frequency of the color subcarrier, so that color bleeding is reduced. By switching these, it is possible to cope with both the case where it is necessary to reduce the distortion of the image and the case where it is necessary to reduce the color blur. Also,
The first dot clock whose frequency is not an integral multiple of the frequency of the color subcarrier can be synchronized with the color subcarrier by using the reference clock having a frequency that is an integral multiple of the color subcarrier as a reference. It will be possible.

According to the second aspect of the present invention, when the first dot clock is output from the PLL circuit, the shape of each dot displayed on the monitor becomes a substantially square shape. The distortion of the image when displayed is small. Further, when the second dot clock is output, the frequency of this dot clock is an integral multiple of the frequency of the color subcarrier, so that color blurring of the image is reduced. Further, since the first and second dot clocks are generated by the PLL circuit based on the same reference clock as the color subcarrier, it does not matter whether the frequency is an integral multiple of the frequency of the color subcarrier. Instead, they synchronize with each other.

According to the third aspect of the invention, when the first frequency division value is set as the frequency division value l by the frequency division value selection means, the frequency of the output signal of the first frequency division circuit is l. It is doubled and output from the PLL circuit, and the output signal of this PLL circuit is divided into 1 / k in the dot clock generating circuit.
As a result, the first dot clock for making the shape of the dots displayed on the monitor substantially square is output. Further, when the second frequency division value is set as the frequency division value 1 by the frequency division value selection means, the output signal of the PLL circuit is frequency-divided into 1 / k in the dot clock generation circuit,
A second dot clock that is an integer multiple of the frequency of the color subcarrier is output.

According to the fourth aspect of the invention, when the first dot clock is output, the counting means counts at the timing of the first dot clock, and the count value and the H count value selecting means. Compare with the H count value selected by. When they match, it is considered that the counting of the dots of one line in the horizontal direction is completed, and the counting is started again from 0. Similarly,
When the second dot clock is output, the counting means counts at the timing of the second dot clock,
The count value is compared with the H count value selected by the H count value selection means. This makes it possible to display an image corresponding to two types of dot clocks.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing apparatus according to the present invention will be described below with reference to the drawings. The description of the parts corresponding to those shown in the figure will be omitted.

(1) Configuration of the Embodiment (a) Overall Configuration FIG. 1 is a block diagram showing an embodiment of the image processing apparatus according to the present invention. In the figure, 10 indicates a game console body,
An input device such as a control pad 11 for a user to operate a game is provided on the game machine main body 10 by S
It is connected via an MPC (System Manager & Peripheral Control) 12. Further, a cartridge 13 storing a game program is removably attached to the game machine body 10. Further, the game machine body 10 is equipped with a CD-ROM drive (not shown), so that a game program, image data, and the like can be supplied from the CD-ROM.

Further, the bus 14, a CPU 15, a work RAM 16 for storing a program, a VDP 21 to which a VRAM 17 is connected, and the SMPC 12 are connected. The SMPC 12 is an I / O controller and manages and controls the reset of the entire system 1
Controls the interface with external equipment such as 1. Also,
The PLL circuit 18 is connected to the SMPC 12 and S
The MPC 12 switches the clock of the PLL circuit 18.

(B) Dot Clock Control Configuration Next, the configuration of the dot clock control in the PLL circuit 18 and the VDP 21 will be described with reference to FIG. 3 is a timing chart of each signal.

In FIG. 2, 100 is a reference clock CLK having a frequency of 14.31818 MHz shown in FIG.
It is a crystal oscillator that generates. Also, 101 is 14.
It is a frequency dividing circuit for dividing 31818 MHz into 1/910. The output signal Sr of the 910 frequency divider circuit 101 is as shown in FIG.
As shown in (b), the frequency is about 15.73 kHz, which is synchronized with the horizontal synchronizing signal. Further, reference numerals 102a and 102b denote frequency division value setting units used in the frequency division circuit 103 in which frequency division values are set, and the frequency division value setting unit 102a includes frequency division value "1560" and frequency division value setting unit 102b. Is set to the frequency division value "1820".

Reference numeral 104 denotes the frequency division values "1560" and "1".
820 ”, and the selection signal S supplied from the SMPC 12
It is a switch for switching and outputting by EL. The SMPC 12 outputs the selection signal SEL when the CPU 15 sets the number of display dots in the horizontal direction in an internal register (not shown). The number of display dots in the horizontal direction is, for example, “320” and “373”.
And are set. That is, when the shape of the dots forming the screen of the TV monitor 41 is a square, the number of display dots in the horizontal direction is “320” as described above.
On the other hand, the frequency of the dot clock DTCK is the color subcarrier S
When it becomes an integral multiple of the frequency of C, for example, twice, the frequency of the dot clock DTCK becomes 7.15909 MHz, and the number of display dots in the horizontal direction becomes “373”.

Therefore, when "320" is set as the number of display dots in the horizontal direction in the SMPC 12, the selection signal SEL changes the output of the switch 104 to "1560".
Switch to, and if "373" is set, "182
Switch to 0 ”.

Further, the frequency dividing circuit 103 divides the output signal Sout of the voltage control circuit 106, which will be described later, by the frequency dividing value "1560".
Alternatively, the frequency is divided by "1820" to generate the output signal Ss shown in FIG. 3C or 3F.

Further, 105 is a phase comparison circuit, and 91
The phase difference between the output signal Sr of the 0 frequency dividing circuit 101 and the output signal Ss of the frequency dividing circuit 103 is detected, and a signal corresponding to the phase difference is generated. Then, the voltage control circuit 106 receives the output signal of the phase comparison circuit 105,
It oscillates at a frequency synchronized with the output signal Sr of the frequency-dividing circuit 101. With such a configuration, the voltage control circuit 106
Output signal Sout 1560 times or 1820 times the frequency of the output signal Sr of the 910 frequency divider circuit 101 is generated. Therefore, this output signal Sout is
As shown in (d) or (g), the crystal unit 100
1560/910 of the reference clock CLK generated from
That is, about 1.7142 times, or 1820/91
0, that is, twice the frequency.

On the other hand, 107 is a divide-by-four circuit, which divides the frequency of the reference clock CLK generated from the crystal unit 100 into quarters. The frequency-divided signal is supplied to the RGB encoder 31 as a color subcarrier SC.

In the VDP 21, reference numeral 108 denotes a divide-by-4 circuit, which divides the frequency of the signal output from the PLL circuit 18 into 1/4 and forms an image as a dot clock DTCK shown in FIG. 3E or 3H. Output to the display circuit 109 and the H counter 110. 111a and 111b are H count value setting units, and the H count value "3" is stored in 111a.
90 "is set, and the H count value" 455 "is set in 111b. Above dot value "390"
Is the value when the dot shape is square, as described above, and the dot value “455” is the dot clock D
It is a value when the frequency of TCK is an integral multiple of the frequency of the color subcarrier SC.

The H count value is a predetermined count value for one line and is determined by the number of display dots in the horizontal direction described above. That is, when the number of display dots in the horizontal direction is 320, the dot clock is 6.13635 MHz (about 163.0 nsec), so the H count value is 390. When the number of display dots in the horizontal direction is 373, the dot clock is 7.15909 MHz (about 139.70 nse).
Since it is c), the H count value is 455.

Further, 112 is the above-mentioned selection signal SEL.
Is a switch for switching and outputting the H count value of "390" and "455".

The H counter 110 counts according to the dot clock DTCK during a period for displaying one line (horizontal display period + horizontal blank period), and supplies this count value to the image display circuit 109. At the same time, it is compared with the H count value output from the switch 112, and if they match, it is considered that the display of one line is completed and the count value is returned to 0.

The image display circuit 109 is a frequency-dividing circuit 108.
Dot clock DTCK and H counter 1 output from
Based on the count value output from 10, the dot data at the corresponding position of each line on the screen is output at the timing of the dot clock DTCK.

(2) Operation of Embodiment Next, the operation of the image processing apparatus according to this embodiment will be described.

First, a case where the shape of each dot displayed on the TV monitor 41 is a square will be described. For example, when the operator specifies that the shape of the dots displayed by the operating means (not shown) is square, the selection signal SEL for setting the number of horizontal display dots to 320 is SMPC1.
2 to the PLL circuit 18 and the VDP 21. As a result, the switch 104 of the PLL circuit 18 outputs the frequency division value “1560” set in the frequency division value setting unit 102a to the frequency division circuit 103. Thereby, FIG.
As shown in (d), the output signal S of the voltage control circuit 106
The frequency of out is the output signal S of the 910 frequency divider circuit 101.
1560 times the frequency of r, that is, the reference clock CLK
About 1.7142 times (about 24.5454 MHz).

The output signal from the voltage control circuit 106 is supplied to the divide-by-4 circuit 108 of the VDP 21 and is divided into 1/4.
And is supplied to the image display circuit 109 and the H counter 110 as a dot clock DTCK having a frequency of 6.13635 MHz. On the other hand, by outputting the selection signal SEL, the H counter 110 is switched from the switch 112.
On the other hand, the H count value “390” set in the dot setting unit 111a is output. Therefore, the H counter 110
Starts counting according to the dot clock DTCK, supplies the count value to the image display circuit 109, and sequentially compares the count value with the H count value "390".

From the image display circuit 109, the frequency 6.1
RG according to the dot clock DTCK of 3635 MHz
The B signal is output. This RGB signal is supplied to the RGB encoder 31 and is supplied to the TV monitor 41 as the video signal VOUT. As a result, the shape of each dot displayed on the TV monitor 41 becomes a square.

Next, the case where the frequency of the dot clock DTCK is an integral multiple of the color subcarrier SC will be described. For example, if the operator specifies that the frequency of the dot clock DTCK is an integral multiple of the frequency of the color subcarrier SC, the selection signal SE that sets the number of display dots in the horizontal direction to 455 dots.
L is supplied from the SMPC 12 to the PLL circuit 18 and the VDP 21. As a result, the switch 1 of the PLL circuit 18
04 to the frequency dividing circuit 103, the frequency division value setting unit 102
The frequency division value "1820" set in b is output. Thereby, as shown in FIG.
The frequency of the output signal Sout of 6 is 910 frequency divider circuit 101.
1820 times the frequency of the output signal Sr of, that is, twice the frequency of the reference clock CLK (about 28.63636M
Hz) signal is output.

The output signal S from this voltage control circuit 106
out is 1/0 in the divide-by-4 circuit 108 of the VDP 21.
The frequency is divided by 4 and supplied to the image display circuit 109 and the H counter 110 as a dot clock DTCK having a frequency of 7.15909 MHz. On the other hand, when the selection signal SEL is output, the H counter 1 is switched from the switch 112.
For H, the H count value “455” set in the dot setting unit 111b is output. Therefore, the H counter 110 starts counting according to the dot clock DTCK, supplies the count value to the image display circuit 109, and sequentially compares the count value with the H count value “455”.

From the image display circuit 109, the frequency of 7.1
RG according to the dot clock DTCK of 5909 MHz
The B signal is output. Also, the RGB encoder 31 is supplied with a color subcarrier SC having a frequency of 3.579545 MHz, and as shown in FIGS. 3 (h) and 3 (i),
The frequency of the dot clock DTCK is twice the frequency of the color subcarrier SC. Therefore, the RGB signal is synchronized with the color subcarrier SC, and the color bleeding for each dot of the image displayed on the TV monitor 41 is reduced.

(3) Effects of the Embodiment As described above, according to this embodiment, the image display circuit 10 can be operated only by switching the switch 104 and the switch 112.
It is possible to change the frequency of the dot clock DTCK to be supplied to No. 9. Also, even if the frequency of the dot clock DTCK is not a positive multiple of the frequency of the color subcarrier SC, PL
By using the L circuit 18, the dot clock DTCK and the color subcarrier SC can be synchronized with each other as shown in FIGS.

(4) Other Embodiments In the above-described embodiment, each value such as the dot clock, the display dot value, the H count value, and the frequency division value is an example and is not limited to this. Absent. Further, in the above-mentioned embodiment, the case where the aspect ratio of 1 dot is set to 1: 1 is set, but when the image actually displayed on the monitor is seen,
If one dot is about vertical: horizontal = 1: 1 ± 0.1, it will not appear distorted. Therefore, one dot is vertical: horizontal = 1: 1 ± 0.1
You may set each value so that it may become a degree.

In this embodiment, an NTSC system TV is used.
Although the case of using a monitor has been described, the present invention can also be applied to the case of using a PAL TV monitor.
That is, in the case of the PAL system, the frequency of the color subcarrier is different from that in the case of the NTSC system, and the reference clock is set accordingly. Also, since the display time (horizontal frequency) and the number of display lines (vertical resolution) of one line are different, the frequency of the dot clock for making the dot shape square is also set by them. Then, the dot clock for making the dot shape square and the dot clock whose frequency is an integral multiple of the frequency of the color subcarrier are switched using the PLL circuit.

Further, the present invention is not limited to the above-mentioned embodiment, but can be widely used in an image display device of a computer other than a video game machine, that is, a personal computer or the like.

[0048]

As described above, according to the present invention, the dot clock can be switched with a simple structure.
Further, by using the PLL circuit, the dot clock and the color subcarrier can be synchronized even when the frequency of the dot clock is not an integral multiple of the frequency of the color subcarrier. As a result, it is possible to deal with both the case where it is desired to reduce the image distortion between the time of drawing and the time when it is displayed and the case where it is desired to reduce color bleeding, without generating iridescent noise. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a P for controlling a dot clock in the embodiment.
6 is a block diagram showing the configurations of an LL circuit 18 and a VDP 21. FIG.

FIG. 3 is a time chart of each signal in the present embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional image processing apparatus.

FIG. 5 is a time chart showing a color subcarrier SC and a dot clock DTCK in the conventional image processing apparatus.

FIG. 6 is a block diagram showing a conventional image processing apparatus.

FIG. 7 is a diagram illustrating a problem in a conventional image processing apparatus.

[Description of Codes] 12 ... SMPC 18 ... PLL circuit 21 ... VDP (image data generation circuit) 31 ... RGB encoder (encoder) 41 ... TV monitor 100 ... Crystal oscillator (reference clock generation means) 101 ... 910 frequency divider circuit ( First frequency dividing circuit 102a, 102b ... Frequency dividing value setting means 103 ... Frequency dividing circuit (second frequency dividing circuit) 104 ... Switch (frequency dividing value selecting means) 107 ... 4 frequency dividing circuit (color subcarrier generation) Means) 108 ... Dividing circuit (dot clock generating means) 109 ... Image display circuit 110 ... H counter (counting means) 111a, 111b ... H count value setting section 112 ... Switch (H count value selecting means)

Claims (4)

[Claims] 1. An image processing method for generating a video signal at a dot clock timing based on image data read from an image storage means and a color subcarrier and outputting the video signal to a monitor, wherein the frequency is the frequency of the color subcarrier. By using a PLL (Phase Locked Loop) circuit based on a reference clock that is an integral multiple, a first dot clock having a frequency that makes the shape of the dots displayed on the monitor substantially square and the frequency of the color subcarrier. And a second dot clock having a frequency that is an integral multiple of, and outputting any one of them. 2. An image data generating circuit for reading image data from an image storage means and outputting the image data at a dot clock timing, and an encoder for generating a video signal based on the image data and a color subcarrier. An image processing apparatus for outputting a video signal to a monitor, comprising: a reference clock generating means for generating a reference clock; a color subcarrier generating means for generating a color subcarrier based on the reference clock; and the monitor based on the reference clock. Output by switching between one of a first dot clock having a frequency that makes each dot displayed in a square shape a substantially square shape and a second dot clock having a frequency that is an integer multiple of the frequency of the color subcarrier. An image processing apparatus comprising: 3. An image data generation circuit for reading image data from an image storage means and outputting the image data at a dot clock timing, and an encoder for generating a video signal based on the image data and a color subcarrier. In an image processing device for outputting a video signal to a monitor, a reference clock generating means for generating a reference clock, and a color subcarrier generating means for dividing and outputting the frequency of the reference clock by 1 / n (n is an integer). A frequency dividing circuit for dividing the frequency of the reference clock into 1 / m (m is an integer) and outputting the divided frequency; and a second dividing circuit having a frequency division value 1 (l is an integer), A PLL circuit that multiplies the frequency of the output signal of the first frequency dividing circuit by 1 and outputs the frequency of the output signal of the first frequency dividing circuit as the frequency division value 1 of the second frequency dividing circuit. , The screen displayed on the monitor Of the dot subclock for making the shape of the square substantially square, and a second frequency division value for making the frequency of the color subcarrier an integral multiple of k (k is an integer). And a frequency division value selecting means for selecting one of the frequency division values, and a dot for dividing the output signal of the PLL circuit into 1 / k and outputting as the first dot clock or the second dot clock. An image processing apparatus comprising: a clock generating unit. 4. The image data generation circuit, an H count value corresponding to the first dot clock,
H count value selection means for selecting one of the H count value corresponding to the second dot clock, and counting at the timing of one of the first dot clock and the second dot clock, An H count value selected by the H count value selection means,
4. The image processing apparatus according to claim 2, further comprising a counting unit that compares the counted values and restarts counting from 0 when they match.