JP2002158895A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a television receiver which appropriately corrects a horizontal outline in accordance with the number of display picture pixels in a display device. SOLUTION: A dot clock generation means 90 generates a dot clock based on a horizontal synchronizing signal. A first delay circuit 13 delays an original video signal by prescribed time t1 by using the dot clock and a first delay video signal is outputted. A second delay circuit 15 delays the first delay video signal by prescribed time t2 by using the dot clock, and a second delay video signal is outputted. An operation means 70 performs an operation by using the original video signal, the first delay video signal and the second delay video signal, and an operation result and the first delay video signal are added so as to obtain a horizontal outline correction signal. Then, t1 and t2 are set to be integer-times as much as the period of the dot clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver having a horizontal contour correction circuit, and more particularly to a television receiver having a dot matrix type image display device. Is what you do.

[0002]

2. Description of the Related Art In recent years, as the size of a display screen in a television receiver has increased, the demand for higher image quality of displayed images has increased, and horizontal contour correction processing has often been performed on video signals. ing. FIG. 4 is a diagram illustrating an example of a horizontal contour correction device according to a conventional television receiver.
FIG. 5 is a diagram showing signal waveforms at various parts in the horizontal contour correction device 40 shown in FIG. FIG. 4 schematically shows a state in which a horizontal contour correction signal is obtained from a video signal and added to the video signal to obtain a video signal having a horizontal contour corrected. In FIG. 4, j1 is an original video signal to be subjected to horizontal contour correction, CL1 is a clock signal for horizontal contour correction, and is four times the color subcarrier frequency fsc of the original video signal j1. It is.

The symbols j1 to j8 shown in FIG. 5 correspond to the signs of the signals of the respective parts shown in FIG. First, the original video signal j1 is
The first delay circuit 13 composed of a flip-flop circuit delays the signal by a predetermined time t0 to obtain a first delayed video signal j2, and further the second delay circuit 13 composed of a flip-flop circuit
The second delay video signal j3 is obtained by the delay circuit 15 delayed by the same time t0 as that of the first delay circuit 13. Next, the original video signal j1 and the second delayed video signal j3 are added by the addition circuit 17 to obtain an addition signal j4, and the amplitude is doubled by the coefficient unit 19 to obtain a signal j5. Then, the subtraction circuit 21
The signal j5 is subtracted from the first delay signal j2 to obtain a horizontal contour correction signal j6. The level of the horizontal contour correction signal j6 is set to K times the level by the gain control circuit 23, and then added to the first delayed video signal j2 to obtain a video signal j8 with the horizontal contour corrected.

The frequency of the clock signal CL1 is generally set to four times (4 fsc) the color subcarrier frequency.
The delay time t0 of each of the first delay circuit 13 and the second delay circuit 15 and the gain of the gain control circuit 23 are fixed in advance at the stage of design or manufacture, or are adjusted by an operator of the television receiver. It is possible. Specifically, to obtain an image in which the contour is emphasized, K is increased.
On the other hand, when trying to obtain a soft image without emphasizing the contour, the gain K is generally set to be small. When the clock signal CL1 is 4 fsc, the delay time of each flip-flop circuit is a time corresponding to one cycle of the clock signal, and fsc is about 3.58 MHz. Therefore, the delay time t0 is 70 ns (the correction width is t0). 140n in double
s), and K is, for example, about 0.2.

[0005]

However, in the above-mentioned conventional configuration, the delay time t0 of the first delay circuit 13 and the second delay circuit 15 is fixed to a predetermined value in advance, so that the display screen of the television receiver is not fixed. However, there is a problem that the optimum horizontal contour correction cannot be performed on the image displayed on the screen. That is, when the display device of the television receiver is a dot matrix type such as a liquid crystal or a plasma display (hereinafter also referred to as a PDP), a horizontal contour correction signal is formed regardless of the number of display pixels of the PDP or the like. Therefore, when the PDP or the like connected to the television receiver is changed, there is a problem that the amount of horizontal contour correction is excessive or insufficient.

For example, when one horizontal scanning line has a small number of horizontal pixels and a large number of horizontal pixels, if the number of horizontal pixels is small, high-definition display cannot be performed. If the correction width of horizontal contour correction (twice the delay time) is too small, it is difficult to obtain the effect of horizontal contour correction. On the other hand, if the number of horizontal pixels is large, high-definition display can be performed. The better the bandwidth, the better
The correction width of horizontal contour correction (twice the delay time) needs to be reduced to some extent. This is because if the correction width of the horizontal contour correction is large when the number of horizontal pixels is large, the high-frequency component of the video signal is masked by the horizontal contour correction signal and cannot be displayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a television receiver that performs appropriate horizontal contour correction according to the number of display pixels of a display device.

[0008]

SUMMARY OF THE INVENTION A television receiver according to the present invention has been made to solve the above-mentioned problems.
According to a first aspect, in a television receiver provided with a horizontal contour correction circuit for performing horizontal contour correction of an original video signal, the horizontal contour correction circuit includes a dot for generating a dot clock based on a horizontal synchronization signal. Clock generation means;
A first delay circuit that delays the original video signal by a predetermined time t1 using the dot clock and outputs the first delayed video signal as a first delayed video signal, and delays the first delayed video signal by a predetermined time t2 using the dot clock A second delay circuit that outputs the second delayed video signal as a second delayed video signal, an arithmetic circuit that performs an arithmetic operation using the original video signal, the first delayed video signal, and the second delayed video signal, and an output of the arithmetic circuit. An adder circuit for adding the first delayed video signal to the first delay video signal;
This is a television receiver in which 1 and time t2 are set to integral multiples of the period of the dot clock.

According to the present invention, in a horizontal contour correcting circuit for performing horizontal contour correction on an original video signal, a dot clock is generated by a dot clock generating means based on a horizontal synchronizing signal, and a first delay circuit is provided. The first delayed video signal is output by delaying the original video signal by an integer multiple of the dot clock cycle using the dot clock, and the second delayed circuit converts the first delayed video signal using the dot clock. A second delayed video signal is output with a time delay of an integral multiple of the dot clock cycle, and a calculation is performed using the original video signal, the first delayed video signal, and the second delayed video signal. Since the video signal subjected to the horizontal contour correction is obtained by adding the first delayed video signal, the correction width of the horizontal contour correction signal is equal to the water width in the dot matrix type image display device. Becomes as proportional to the reciprocal of the number of display pixels, it is possible to display an image corrected by the horizontal contour correction signal appropriate correction width. For example, in the case of a display device for high definition, compared to the case of a display device for low definition,
By reducing the correction width of the horizontal contour correction signal, it is possible to prevent the high frequency component of the video signal from being crushed by the horizontal contour correction signal and not being displayed, and conversely, in the case of a display device for low definition, a high The effect of the horizontal contour correction can be increased by increasing the correction width of the horizontal contour correction signal as compared with the case of the display device for definition.

According to a second aspect, in the television receiver according to the first aspect, the arithmetic circuit multiplies a signal obtained by adding the original video signal and the second delayed video signal by 0.5 to produce a third signal. A television receiving apparatus for obtaining a video signal, subtracting the third video signal from the first delayed video signal to obtain a fourth video signal, and multiplying the fourth video signal by a coefficient of 1 or less and outputting the multiplied signal; Machine.

According to the present invention, it is possible to generate a horizontal contour corrected video signal having a correction width proportional to the period of the dot clock with a simple circuit configuration.

According to a third aspect, in the television receiver according to the first aspect, the arithmetic circuit includes: a video signal obtained by subtracting the original video signal from the first delayed video signal; A television receiver configured to add a video signal obtained by subtracting the second delayed video signal from the video signal, multiply the video signal obtained by the addition by a coefficient of 0.5 or less, and output the multiplied video signal. is there.

According to the present invention, it is possible to obtain a horizontal contour corrected video signal having a correction width proportional to the period of the dot clock with a simple circuit configuration.

According to a fourth aspect of the present invention, there is provided the television receiver according to any one of the first to third aspects, further comprising a selection means for selecting the delay time t1 and the delay time t2. It is.

According to the present invention, when the correction width of the horizontal contour correction is inappropriate for, for example, a viewer of a television receiver or a video signal to be displayed, a horizontal contour corrected image having an appropriate correction width is used. You can switch to a signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a television receiver according to the present invention, in a horizontal contour correction circuit for correcting a horizontal contour of an original video signal, a dot clock is generated by a dot clock generating means based on a horizontal synchronizing signal. A first delay circuit that delays the original video signal by a predetermined time t1 using the dot clock to output a first delayed video signal, and a second delay circuit uses the dot clock to convert the first delayed video signal to the dot clock. And outputs a second delayed video signal with a delay of a predetermined time t2. The second delayed video signal is calculated using the original video signal, the first delayed video signal, and the second delayed video signal. The horizontal contour correction is performed by adding the video signal and the time t1, and the time t1 and the time t2 are set to integral multiples of the period of the dot clock, thereby providing a display device of a television receiver. Obtaining horizontal contour correction signal having the appropriate correction width in accordance with 示画 prime. In this specification, the t
The sum of 1 and t2 is referred to as a correction width in horizontal contour correction.

Hereinafter, a television receiver according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a horizontal contour correcting device according to the television receiver of the present invention. In FIG. 1, reference numeral 90 denotes a dot clock generating means for generating a dot clock dc based on the horizontal synchronizing signal c1, which is an oscillator having a phase locked loop (PLL). The dot clock generation means 90 is a phase comparator (PC)
27, a low pass filter (LPF) 29, a voltage controlled oscillator (VCO) 31, and a frequency divider 33. The dot clock having the cycle td output from the dot clock generating means 90 is supplied to the sampling unit 11, the first delay circuit 13, and the second delay circuit 15. Each of the first delay circuit 13 and the second delay circuit 15 is a delay circuit composed of a flip-flop. The first delay circuit 13 and the second delay circuit 15 delay the signal input to the D terminal by one cycle of the clock supplied to the CK terminal and output the signal from the Q terminal. Output.

The sampling section 11 samples the input video signal s0 with the dot clock dc and converts the original video signal s1 having pixel data for each display pixel of a dot matrix type display device (not shown) into a first delay circuit 13 And an adder 17. The first delay circuit 13 delays the original video signal s1 by one period (td) of the dot clock dc, and provides the same as the first delayed video signal s2 to the second delay circuit 15, the subtraction circuit 21, and the addition circuit 25. The second delay circuit 15 delays the first delayed video signal s2 by one period (td) of the dot clock dc and provides the second delayed video signal s3 to the adding circuit 17 as a second delayed video signal s3.

The arithmetic means 70 generates a horizontal contour correction signal s6 from the original video signal s1, the first delayed video signal s2, and the second delayed video signal s3, and multiplies the level of the horizontal contour correction signal s6 by K1. This is given to the addition circuit 25 as s7. The calculating means 70 includes an adding circuit 17, a coefficient unit 19, and a subtracting circuit 21.
And a gain control circuit 23.

The adder circuit 17 compares the original video signal s1 with the second
Adds the delayed video signal s3 and the added signal s4 to the coefficient unit 1
Give 9 The coefficient unit 19 reduces the amplitude of the addition signal s4 to １ ／.
The signal is given to the subtraction circuit 21 as a signal s5. The subtraction circuit 21 subtracts the signal s5 from the first delayed video signal s2 and supplies the result to the gain control circuit 23 as a horizontal contour correction signal s6. The gain control circuit 23 is a circuit that multiplies the level of the horizontal contour correction signal s6 by K1 and supplies the same to the addition circuit 25 as a signal s7, and the K1 is usually set to 1 or less, for example, 0.2. K1 may be changed or set by a viewer of the television receiver. The addition circuit 25 outputs a video signal s8 whose horizontal contour has been corrected by adding the first delayed video signal s2 and the signal s7.

The horizontal contour corrected video signal s8 output from the addition circuit 25 has pixel data for each display pixel, and the contour correction width of the horizontal contour corrected video signal is twice the period td of the dot clock dc. When the pixel interval of the display device is large, the correction width of the horizontal contour correction is large, and when the pixel interval of the display device is small, the correction width of the horizontal contour correction is also small. Accordingly, when a dot matrix type image display device such as a liquid crystal display or a PDP is driven by the video signal s8 having the horizontal contour corrected, a display device for high definition having a large number of display pixels, particularly a large number of horizontal display pixels, is more effective. A fine image can be displayed, and in a display device for low definition having a small number of display pixels, particularly a small number of horizontal display pixels, the effect of horizontal contour correction can be further enhanced.

FIG. 2 is a view showing a second embodiment of the horizontal contour correcting device according to the television receiver of the present invention. The same reference numerals are given to the same functions, the elements having the same operations, and the same signals as in the first embodiment shown in FIG. 1, and the description thereof will be omitted. FIG.
1 differs from the device of FIG. 1 in that the calculation method in the calculation means 70b is different from the calculation method in the calculation means 70. 2, the calculating means 70b includes a subtraction circuit 41, an addition circuit 43, a subtraction circuit 45, and a gain control circuit 47.
It is composed of The calculating means 70b generates a horizontal contour correction signal s13 from the original video signal s1, the first delayed video signal s2, and the second delayed video signal s3, and generates the horizontal contour correction signal s1.
3 is multiplied by K2 to obtain an addition circuit 25 as a signal s14.
Give to.

The subtraction circuit 41 subtracts the original video signal s1 from the first delayed video signal s2 to generate an addition circuit 43 as a signal s11.
Give to. The subtraction circuit 45 subtracts the second delayed video signal s3 from the first delayed video signal s2 and supplies the signal as the signal s12 to the addition circuit 43. The adder circuit 43 outputs the signal s11 and the signal s
12 and the horizontal contour correction signal s13 is supplied to the gain control circuit 47. The gain control circuit 47 is a circuit that raises the level of the horizontal contour correction signal s13 by K2 and supplies it to the addition circuit 25 as a signal s14. The K2 is usually set to 0.5 or less, for example, 0.1. The K2 may be changed or set by a viewer of the television receiver. The addition circuit 25 outputs a video signal s8 having a horizontal contour corrected by adding the first delayed video signal s2 and the signal s14. 2, the coefficient unit 19 shown in FIG. 1 is not required, and the configuration of the calculation means is simplified.

FIG. 3 is a diagram showing a third embodiment of the horizontal contour correcting device according to the television receiver of the present invention. The same reference numerals are given to the same functions, the elements having the same operations, and the same signals as in the first embodiment shown in FIG. 1, and the description thereof will be omitted. FIG.
The main differences between this device and the device shown in FIG. 1 are that the number of delay circuits is large and that a switch (selection means) 63 is provided. In FIG. 3, delay circuits 51, 53, 55,
Reference numerals 57 are cascade-connected in this order, and each delay circuit delays the input video signal by one period td of the dot clock dc and outputs it. The adding circuit 59 adds the first delayed video signal s2 output from the delay circuit 51 and the third delayed video signal s24 output from the delay circuit 55 to generate a signal s.
26 is given to a switch (selection means) 63. Adder circuit 6
1 is the original video signal s1 and the fourth output from the delay circuit 57.
The delayed video signal s25 and the signal s27 are added to the switch 63 and added.

The switch (selection means) 63 outputs the signal s2
6 or the signal s27 is selected and given to the coefficient unit 19 as a signal s28. The operation from the coefficient unit 19 to the adding circuit 25 is as described in the apparatus of FIG. When the switch (selecting means) 63 selects the signal S26,
The horizontal contour correction signal output from the subtraction circuit 21 has a correction width twice the period td of the dot clock dc, and when the switch (selection means) 63 selects the signal S27,
The correction width of the horizontal contour correction signal output from the subtraction circuit 21 is four times the period td of the dot clock dc, and the correction width is large.

By increasing the number of delay circuits, the delay time selectable by the switch (selection means) 63 can be further increased. Further, which signal is selected by the switch (selection means) 63 may be selected by the viewer of the television receiver, or may be automatically switched according to the nature of the video signal. Is also good. The property of the video signal is, for example, the amount of noise included in the video signal,
Alternatively, it is the frequency band of the video signal. The amount of the noise can be easily estimated with a C / N meter, and the frequency band can be easily estimated from the amount of a high-frequency signal component having a predetermined frequency or higher included in the video signal. In a standard setting, the switch (selection means) 63 selects the signal s26 for obtaining a correction signal whose correction width is twice as large as td, and when the video signal has a large amount of noise or a signal lacking a high frequency component. A signal s27 for obtaining a correction signal whose correction width is four times td is selected.

As described above in detail, according to the television receiver of the present invention, in the horizontal contour correction circuit for correcting the horizontal contour of the original video signal, the dot clock generating means uses the horizontal synchronizing signal based on the horizontal synchronizing signal. A first delay circuit generates a first delay video signal by delaying the original video signal by an integer multiple of a dot clock cycle using the dot clock, and generates a first delay video signal.
Using the dot clock, the delayed video signal is delayed by an integer multiple of the dot clock cycle to output a second delayed video signal, and the original video signal, the first delayed video signal, and the second delayed video signal are Since the video signal subjected to the horizontal contour correction is obtained by adding the calculation result and the first delayed video signal, the display of the dot matrix type image display device in the television receiver is performed. In accordance with the number of pixels, it is possible to display an image corrected by a horizontal contour correction signal having an appropriate correction width.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a horizontal contour correction device according to a television receiver of the present invention.

FIG. 2 is a diagram showing a second embodiment of the horizontal contour correcting device according to the television receiver of the present invention.

FIG. 3 is a diagram showing a third embodiment of the horizontal contour correcting device according to the television receiver of the present invention.

FIG. 4 is a diagram illustrating an example of a horizontal contour correction device according to a conventional television receiver.

FIG. 5 is a diagram showing signal waveforms at various parts in the horizontal contour correction device shown in FIG.

[Explanation of symbols]

 Reference Signs List 11 sampling section 13 flip-flop circuit (first delay circuit) 15 flip-flop circuit (second delay circuit) 17, 25, 43 addition circuit 19 coefficient device 21, 41, 45 subtraction circuit 23, 47 gain control circuit 27 phase comparator Reference Signs List 29 low-pass filter (LPF) 31 voltage-controlled oscillator 33 frequency divider 63 switch (selection means) 70, 70b calculation means 90 dot clock generation means

Claims (4)

[Claims] 1. A television receiver having a horizontal contour correction circuit for performing horizontal contour correction of an original video signal.
The horizontal contour correction circuit includes: a dot clock generation unit configured to generate a dot clock based on a horizontal synchronization signal;
A first delay circuit that delays the first delayed video signal as a first delayed video signal and a second delay circuit that delays the first delayed video signal by a predetermined time t2 using the dot clock and outputs the delayed second video signal as a second delayed video signal An arithmetic circuit that performs an operation using the original video signal, the first delayed video signal, and the second delayed video signal, and an addition circuit that adds the output of the arithmetic circuit and the first delayed video signal. A television receiver, wherein the time t1 and the time t2 are integer multiples of a period of the dot clock. 2. A television receiver according to claim 1, wherein said arithmetic circuit multiplies a signal obtained by adding said original video signal and said second delayed video signal by 0.5 to obtain a third video signal. A television receiver, wherein the third video signal is subtracted from the first delayed video signal to obtain a fourth video signal, and the fourth video signal is multiplied by a coefficient of 1 or less and output. 3. The television receiver according to claim 1, wherein the arithmetic circuit is configured to subtract the original video signal from the first delayed video signal and a video signal obtained by subtracting the original video signal from the first delayed video signal. The video signal obtained by subtracting the second delayed video signal is added, and 0.5 is added to the video signal obtained by the addition.
A television receiver characterized by multiplying by the following coefficient and outputting: 4. The television receiver according to claim 1, further comprising a selection unit for selecting the delay time t1 and the delay time t2. Machine.