JP3870022B2 - Television receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a television receiver including a horizontal contour correction circuit, and more particularly to a television receiver including a dot matrix type image display device.
To do.
[0002]
[Prior art]
In recent years, with an increase in the size of a display screen in a television receiver, there is an increasing demand for higher image quality of displayed images, and horizontal contour correction processing is often performed on video signals.
FIG. 4 is a diagram showing an example of a horizontal contour correcting device according to a conventional television receiver, and FIG. 5 is a diagram showing signal waveforms of respective parts in the horizontal contour correcting device 40 shown in FIG. FIG. 4 schematically shows how the horizontal contour correction signal is obtained from the video signal and added to the video signal to obtain a video signal with the horizontal contour corrected.
In FIG. 4, j1 is an original video signal to be subjected to horizontal contour correction, CL1 is a clock signal for horizontal contour correction, and has a frequency four times the color subcarrier frequency fsc related to the original video signal j1. It is.
[0003]
J1 to j8 shown in FIG. 5 match the signs of the signals of the respective parts shown in FIG. First, an original video signal j1 is delayed by a predetermined time t0 by a first delay circuit 13 constituted by a flip-flop circuit to obtain a first delayed video signal j2, and further a second delay circuit constituted by a flip-flop circuit. 15 is delayed by the same time t0 as the first delay circuit 13 to obtain the second delayed video signal j3.
Next, the original video signal j1 and the second delayed video signal j3 are added by the adder circuit 17 to obtain an added signal j4, and the coefficient 19 is multiplied by 1/2 to obtain a signal j5. Then, the subtracting circuit 21 subtracts the signal j5 from the first delay signal j2 to obtain a horizontal contour correction signal j6. The horizontal contour correction signal j6 is set to a K-fold level by the gain control circuit 23, and then added to the first delayed video signal j2, thereby obtaining the video signal j8 having the horizontal contour corrected.
[0004]
The frequency of the clock signal CL1 is generally set to 4 times the color subcarrier frequency (4 fsc). The delay time t0 of each of the first delay circuit 13 and the second delay circuit 15 and the gain of the gain control circuit 23 are fixed in advance at the stage of design or manufacture, or adjusted by the operator of the television receiver. It is possible. Specifically, in order to obtain an image with an emphasized outline, K is increased. On the other hand, when trying to obtain a soft image without enhancing the outline, it is common to set the gain K small. When the clock signal CL1 is 4 fsc, the delay time by each flip-flop circuit is a time corresponding to one cycle of the clock signal, and the fsc is about 3.58 MHz, so the delay time t0 is 70 ns (the correction width is t0). 2 times 140 ns), and K is, for example, about 0.2.
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, the delay time t0 of the first delay circuit 13 and the second delay circuit 15 is fixed to a predetermined value in advance, so that the optimum horizontal for the image displayed on the display screen of the television receiver. There was a problem that contour correction was not possible. That is, when the display device of the television receiver is a dot matrix type such as a liquid crystal or a plasma display (hereinafter also referred to as PDP), a horizontal contour correction signal is formed regardless of the number of display pixels such as the PDP. Therefore, when the PDP or the like connected to the television receiver is changed, there is a problem that the horizontal contour correction amount is excessive or insufficient.
[0006]
For example, when the number of horizontal pixels constituting one horizontal scanning line is small or large, when the number of horizontal pixels is small, the band of the video signal to be displayed may be slightly narrow because high definition display is not possible. If the correction width of the contour correction (twice the delay time) is too small, it is difficult to obtain the effect of horizontal contour correction. It is better, and the horizontal contour correction width (twice the delay time) needs to be reduced to some extent. This is because if the horizontal contour correction width is large when the number of horizontal pixels is large, the high frequency component of the video signal is masked by the horizontal contour correction signal and cannot be displayed.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a television receiver that performs an appropriate horizontal contour correction according to the number of display image pixels of a display device.
[0008]
[Means for Solving the Problems]
The television receiver of the present invention has been made to solve the above-mentioned problems, and the first invention is a television receiver including a horizontal contour correction circuit that performs contour correction in the horizontal direction of an original video signal. The horizontal contour correction circuit includes a dot clock generation unit that generates a dot clock based on a horizontal synchronization signal, and delays the original video signal by a predetermined time t1 using the dot clock as a first delayed video signal. A first delay circuit for outputting, a second delay circuit for delaying the first delayed video signal by a predetermined time t2 using the dot clock and outputting it as a second delayed video signal, the original video signal, and the first An arithmetic circuit for calculating using the delayed video signal and the second delayed video signal, and an adding circuit for adding the output of the arithmetic circuit and the first delayed video signal; t1 and time t2 is a television receiver as an integer multiple of the period of the dot clock.
[0009]
According to the present invention, in a horizontal contour correction circuit that performs a horizontal contour correction on an original video signal, a dot clock is generated by a dot clock generation unit based on a horizontal synchronization signal, and the original delay circuit generates the original clock. The first delay video signal is output by delaying the video signal by an integer multiple of the dot clock cycle using the dot clock, and the first delay video signal is output by the second delay circuit using the dot clock. The second delayed video signal is output with a time delay that is an integral multiple of the first delayed video signal, and is calculated using the original video signal, the first delayed video signal, and the second delayed video signal, and the calculation result and the first delay Since the video signal obtained by performing horizontal contour correction by adding the video signal is obtained, the correction width of the horizontal contour correction signal is the number of horizontal display pixels in the dot matrix type image display device. Becomes as proportional to the reciprocal, it is possible to display an image corrected by the horizontal contour correction signal appropriate correction width.
For example, in the case of a high-definition display device, the horizontal contour correction signal reduces the high-frequency region of the video signal by reducing the correction width of the horizontal contour correction signal compared to the case of a low-definition display device. The component can be prevented from being crushed and not displayed. Conversely, in the case of a display device for low definition, the correction width of the horizontal contour correction signal is increased compared to the case of a display device for high definition. As a result, the effect of horizontal contour correction can be increased.
[0010]
According to a second aspect of the present invention, in the television receiver according to the first aspect, the arithmetic circuit multiplies a signal obtained by adding the original video signal and the second delayed video signal by 0.5 to obtain a third video signal. And obtaining a fourth video signal by subtracting the third video signal from the first delayed video signal, and multiplying the fourth video signal by a coefficient of 1 or less for output. .
[0011]
According to the present invention, it is possible to generate a horizontal contour corrected video signal having a correction width proportional to the dot clock cycle with a simple circuit configuration.
[0012]
According to a third aspect of the present invention, in the television receiver according to the first aspect of the invention, the arithmetic circuit uses a video signal obtained by subtracting the original video signal from the first delayed video signal, and the first delayed video signal. The television receiver is configured to add a video signal obtained by subtracting the second delayed video signal, and multiply the video signal obtained by the addition by a coefficient of 0.5 or less to output.
[0013]
According to the present invention, it is possible to obtain a video signal after horizontal contour correction having a correction width proportional to the dot clock cycle with a simple circuit configuration.
[0014]
A fourth invention is a television receiver according to any one of the first to third inventions, comprising a selection means for selecting the delay time t1 and the delay time t2.
[0015]
According to the present invention, when the correction width of the horizontal contour correction is inappropriate for a viewer of a television receiver or a video signal to be displayed, for example, switching to a horizontal contour corrected video signal having an appropriate correction width is performed. I can do it.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
In the television receiver of the present invention, in the horizontal contour correcting circuit for correcting the contour of the original video signal in the horizontal direction, the dot clock generating means generates a dot clock based on the horizontal synchronizing signal, and the first delay circuit generates the dot clock. The original video signal is delayed by a predetermined time t1 using the dot clock and a first delayed video signal is output, and the second delay circuit delays the first delayed video signal by the predetermined time t2 using the dot clock. Output the second delayed video signal, calculate using the original video signal, the first delayed video signal, and the second delayed video signal, and add the calculation result and the first delayed video signal The horizontal contour correction is performed by the above, and the time t1 and the time t2 are set to integer multiples of the dot clock cycle, so that they are suitable for the number of display pixels of the display device of the television receiver. Obtaining a horizontal contour correction signal having a Do correction width. In this specification, the total value of t1 and t2 is referred to as a correction width in horizontal contour correction.
[0017]
Hereinafter, a television receiver according to the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a first embodiment of a horizontal contour correcting apparatus according to the television receiver of the present invention. In FIG. 1, reference numeral 90 denotes dot clock generating means for generating a dot clock dc based on the horizontal synchronizing signal c1, and is a transmitter having a phase locked loop (PLL). The dot clock generation means 90 includes a phase comparator (PC) 27, a low pass filter (LPF) 29, a voltage control oscillator (VCO) 31, and a frequency divider 33. The dot clock having the period td output from the dot clock generation unit 90 is supplied to the sampling unit 11, the first delay circuit 13, and the second delay circuit 15. Each of the first delay circuit 13 and the second delay circuit 15 is a delay circuit composed of flip-flops, and delays the signal input to the D terminal by one cycle of the clock applied to the CK terminal and from the Q terminal. Output.
[0018]
The sampling unit 11 samples the input video signal s0 with the dot clock dc, and an original video signal s1 having pixel data for each display pixel of a dot matrix type display device (not shown) is added to the first delay circuit 13 and the addition circuit. 17 and give. The first delay circuit 13 delays the original video signal s1 by one period (td) of the dot clock dc, and supplies it to the second delay circuit 15, the subtracting circuit 21, and the adding circuit 25 as the first delayed video signal s2. The second delay circuit 15 delays the first delayed video signal s2 by one period (td) of the dot clock dc and supplies the delayed signal to the adder circuit 17 as the second delayed video signal s3.
[0019]
The calculation means 70 generates a horizontal contour correction signal s6 from the original video signal s1, the first delayed video signal s2, and the second delayed video signal s3, and multiplies the level of the horizontal contour correction signal s6 by K1 and adds it as a signal s7. This is given to the circuit 25. The computing means 70 is composed of an adding circuit 17, a coefficient unit 19, a subtracting circuit 21, and a gain control circuit 23.
[0020]
The adder circuit 17 adds the original video signal s1 and the second delayed video signal s3 and supplies the added signal s4 to the coefficient unit 19. The coefficient unit 19 halves the amplitude of the addition signal s4 and provides it to the subtraction circuit 21 as a signal s5. The subtracting circuit 21 subtracts the signal s5 from the first delayed video signal s2 and provides it to the gain control circuit 23 as a horizontal contour correction signal s6. The gain control circuit 23 is a circuit that multiplies the level of the horizontal contour correction signal s6 by K1 and gives it to the adder circuit 25 as a signal s7. The K1 is normally set to 1 or less, for example, 0.2. The K1 may be changed or set by the viewer of the television receiver. The adder circuit 25 adds the first delayed video signal s2 and the signal s7 to output the video signal s8 with the horizontal contour corrected.
[0021]
The horizontal contour corrected video signal s8 output from the adder circuit 25 has pixel data for each display pixel, and the horizontal contour corrected video signal contour correction width is twice the period td of the dot clock dc. When the pixel interval of the display device is large, the correction width of the horizontal contour correction is large, and when the pixel interval of the display device is small, the correction width of the horizontal contour correction is also small. Therefore, when a dot matrix type image display device such as a liquid crystal or a PDP is driven by the video signal s8 with the horizontal contour corrected, the display device for high definition having a large number of display pixels, especially the number of horizontal display pixels, is more. A fine image can be displayed, and the effect of horizontal contour correction can be further increased in a display device for low definition with a small number of display pixels, particularly the number of horizontal display pixels.
[0022]
FIG. 2 is a diagram showing a second embodiment of the horizontal contour correcting apparatus according to the television receiver of the present invention. The same function, the same action element, and the same signal as those in the first embodiment shown in FIG. The difference between the apparatus in FIG. 2 and the apparatus in FIG. 1 is that the calculation method in the calculation means 70 b is different from the calculation method in the calculation means 70.
In FIG. 2, the calculation means 70 b includes a subtraction circuit 41, an addition circuit 43, a subtraction circuit 45, and a gain control circuit 47. The computing means 70b generates a horizontal contour correction signal s13 from the original video signal s1, the first delayed video signal s2, and the second delayed video signal s3, and doubles the level of the horizontal contour correction signal s13 by K2 and adds it as a signal s14. This is given to the circuit 25.
[0023]
The subtracting circuit 41 subtracts the original video signal s1 from the first delayed video signal s2 and provides it to the adding circuit 43 as a signal s11. The subtracting circuit 45 subtracts the second delayed video signal s3 from the first delayed video signal s2 and provides it to the adding circuit 43 as a signal s12. The adder circuit 43 adds the signal s11 and the signal s12, and gives a horizontal contour correction signal s13 to the gain control circuit 47. The gain control circuit 47 is a circuit that doubles the level of the horizontal contour correction signal s13 and supplies it to the adder circuit 25 as a signal s14. The K2 is normally set to 0.5 or less, for example, 0.1. The K2 may be changed or set by the viewer of the television receiver. The adder circuit 25 adds the first delayed video signal s2 and the signal s14 to output a video signal s8 whose horizontal contour is corrected. The apparatus of FIG. 2 does not require the coefficient unit 19 shown in FIG. 1, and the configuration of the calculation means is simplified.
[0024]
FIG. 3 is a diagram showing a third embodiment of the horizontal contour correcting apparatus according to the television receiver of the present invention. The same function, the same action element, and the same signal as those in the first embodiment shown in FIG. The main differences between the apparatus of FIG. 3 and the apparatus of FIG. 1 are that the number of delay circuits is large and that a switch (selection means) 63 is provided.
In FIG. 3, delay circuits 51, 53, 55, and 57 are cascade-connected in this order, and each delay circuit delays the input video signal by one period td of the dot clock dc and outputs it. The adder circuit 59 adds the first delayed video signal s2 output from the delay circuit 51 and the third delayed video signal s24 output from the delay circuit 55, and provides a signal s26 to the switch (selection means) 63. The adder circuit 61 adds the original video signal s 1 and the fourth delayed video signal s 25 output from the delay circuit 57 and gives a signal s 27 to the switch 63.
[0025]
The switch (selection means) 63 selects either the signal s26 or the signal s27 and supplies it to the coefficient unit 19 as the signal s28. The operation from the coefficient unit 19 to the adding circuit 25 is as described in the apparatus of FIG.
When the switch (selection means) 63 selects the signal s 26, the horizontal contour correction signal output from the subtraction circuit 21 has a correction width that is twice the period td of the dot clock dc, and the switch (selection means) 63. When the signal s27 is selected, the correction width of the horizontal contour correction signal output from the subtraction circuit 21 is four times the period td of the dot clock dc, and the correction width is increased.
[0026]
If the number of delay circuits is increased, the delay time selectable by the switch (selection means) 63 can be further increased. Also, which signal the switch (selection means) 63 selects may be selected by the viewer of the television receiver, or automatically switched according to the nature of the video signal. Also good.
The property of the video signal is, for example, the amount of noise included in the video signal or the frequency band of the video signal. The amount of noise can be easily estimated with a C / N meter, and the frequency band can be easily estimated from the amount of high-frequency signal components of a predetermined frequency or higher included in the video signal.
In a standard setting, the switch (selection means) 63 selects a signal s26 for obtaining a correction signal having a correction width twice as large as td, and when there is a lot of noise in the video signal or a signal lacking a high frequency component. A signal s27 for obtaining a correction signal whose correction width is four times td is selected.
[0027]
As described above in detail, according to the television receiver of the present invention, in the horizontal contour correction circuit that performs the contour correction in the horizontal direction of the original video signal, the dot clock is generated by the dot clock generation means based on the horizontal synchronization signal. And generating a first delayed video signal by delaying the original video signal by an integer multiple of a dot clock period using the dot clock by a first delay circuit, and outputting the first delayed video signal by a second delay circuit. Is delayed by an integral multiple of a dot clock period using the dot clock to output a second delayed video signal, and the arithmetic operation is performed using the original video signal, the first delayed video signal, and the second delayed video signal. Since the video signal having the horizontal contour corrected is obtained by adding the calculation result and the first delayed video signal, the dot matrix in the television receiver is obtained. Depending on the number of display pixels of the image display device can display an image corrected by the horizontal contour correction signal appropriate correction width.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a horizontal contour correcting apparatus according to a television receiver of the present invention.
FIG. 2 is a diagram showing a second embodiment of the horizontal contour correcting apparatus according to the television receiver of the present invention.
FIG. 3 is a diagram showing a third embodiment of the horizontal contour correcting apparatus according to the television receiver of the present invention.
FIG. 4 is a diagram illustrating an example of a horizontal contour correction apparatus according to a conventional television receiver.
5 is a diagram showing signal waveforms at various parts in the horizontal contour correcting apparatus shown in FIG. 4;
[Explanation of symbols]
11 Sampling unit 13 Flip-flop circuit (first delay circuit)
15 Flip-flop circuit (second delay circuit)
17, 25, 43 Adder circuit 19 Coefficient units 21, 41, 45 Subtractor circuits 23, 47 Gain control circuit 27 Phase comparator 29 Low pass filter (LPF)
31 Voltage control transmitter 33 Frequency divider 63 Switch (selection means)
70, 70b calculation means 90 dot clock generation means

Claims (3)

In a television receiver including a horizontal contour correction circuit that performs horizontal contour correction of an original video signal,
The horizontal contour correction circuit includes:
Dot clock generation means for generating a dot clock based on the horizontal synchronization signal;
A first delay circuit that delays the original video signal by a predetermined time t1 using the dot clock and outputs the delayed signal as a first delayed video signal;
A second delay circuit that delays the first delayed video signal by a predetermined time t2 (where t2 ≦ t1) using the dot clock and outputs the delayed second video signal as a second delayed video signal;
An arithmetic circuit for calculating using the video signal before the predetermined time t2 from the original video signal or the first delayed video signal, the first delayed video signal, and the second delayed video signal;
An adder circuit for adding the output of the arithmetic circuit and the first delayed video signal ;
Adjusting means for adjusting the length of the predetermined time t2,
With
The time t1 and the time t2 are integer multiples of the period of the dot clock ,
When the amount of noise included in the original video signal is large or the high-frequency component is lacking, the adjusting means makes the length of the predetermined time t2 longer than a standard set length. And a horizontal contour correction width is increased . 2. The television receiver according to claim 1, wherein the arithmetic circuit outputs a signal obtained by adding the video signal before the predetermined time t2 and the second delayed video signal to the original video signal or the first delayed video signal. .Times.5 to obtain a third video signal, subtract the third video signal from the first delayed video signal to obtain a fourth video signal, and multiply the fourth video signal by a coefficient of 1 or less to output A television receiver characterized by that. 2. The television receiver according to claim 1, wherein the arithmetic circuit subtracts the original video signal or the video signal before the predetermined time t2 from the first delayed video signal from the first delayed video signal. Adding a signal and a video signal obtained by subtracting the second delayed video signal from the first delayed video signal, and multiplying the video signal obtained by the addition by a coefficient of 0.5 or less and outputting the result A television receiver characterized by.

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