JPH086074A - Transistor array for display element and its production - Google Patents

Abstract

PURPOSE:To eliminate propagation delay of signals and to obtain long-term reliability by forming gate wirings and auxiliary wirings of a metal silicide. CONSTITUTION:The surface of a substrate 1 is provided with active part 2 consisting of polycrystal silicon to an island shape and an insulating film 3 is formed in the state of covering these parts. Gate wirings 4 and auxiliary wirings 5 passing above these active parts 2 are formed thereon. These gate wirings 4 and auxiliary wirings 5 are formed of the metal silicide. Further, an interlayer insulating film 6 is foamed in the state of covering the gate wirings 4 and the auxiliary wirings 5 and is provided with contact holes 7. The surface of a thin-film transistor array is provided with a protective insulating film 10 over the entire part thereof. Namely, the metal silicide has a low resistance value and the gate wirings 4 and auxiliary wirings 5 having the low resistance value are obtd. In addition, the metal silicide has heat resistance and does not, therefore, contaminate the insulating film 3, the interlayer insulating film 6, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor array for a display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in a liquid crystal display device having a thin film transistor array, the size of the screen has been increasing in order to make it easier to see. Further, the number of display pixels is increased in order to achieve high definition. Therefore, the resistance value of the gate wiring and the auxiliary wiring of the thin film transistor array, the transistor capacitance and the parasitic capacitance increase, and the signal propagation delay resulting from this is an important problem. The auxiliary wiring described here is, for example, a capacitance (Cs) line or a lead line from a power source.

Among these, it is easy to take measures to reduce the resistance value of the gate wiring and the auxiliary wiring, and the following attempts have been made, for example. For example, when amorphous silicon or polycrystalline silicon containing impurities is used as the material of the gate wiring and the auxiliary wiring, the film thickness of these wirings is increased or the above impurity concentration is increased. Further, for example, a metal material such as aluminum or α-tantalum having a low resistance is used as a material for the gate wiring and the auxiliary wiring.

[0004]

However, even if the film thickness of the wiring is increased or the impurity concentration is increased, the resistance values of the gate wiring and the auxiliary wiring are not fundamentally lowered. Further, the manufacturing process of the conventional thin film transistor array includes a process of treating at a high temperature. Therefore, when the gate wiring and the auxiliary wiring are formed of a metal material, the metal material contaminates the insulating film formed on the gate wiring and the auxiliary wiring during the high temperature treatment. And this has reduced the long-term reliability of the thin film transistor array.

On the other hand, a metal silicide formed by a reaction between these metal materials and silicon and having low resistance and heat resistance has been conventionally known. However, when the metal silicide is formed only by the deposition method, it is difficult to make the metal silicide have a stoichiometric composition showing the lowest resistance value. Therefore, the metal silicide formed by the deposition method cannot reduce the resistance values of the gate wiring and the auxiliary wiring to sufficiently low values.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a display element transistor array having no signal propagation delay and long-term reliability, and a method of manufacturing the same.

[0007]

SUMMARY OF THE INVENTION The present invention is a transistor array for a display device and a method of manufacturing the same for achieving the above object. That is, in the display element transistor array of the present invention, the gate wiring and the auxiliary wiring are made of metal silicide.

A method of manufacturing a transistor array for a display element of the present invention is a method of manufacturing the transistor array for a display element. First, in the first step, a silicon-based thin film made of a material containing at least silicon as a main component is formed on the surface of a substrate. After that, the pattern of the gate wiring and the pattern of the auxiliary wiring are formed by the above-mentioned silicon-based thin film by lithography and etching. Next, in a second step, a metal thin film is formed on the substrate while covering the gate wiring pattern and the auxiliary wiring pattern. Next, in the third step, heat treatment is performed to cause the metal thin film, the gate wiring pattern and the auxiliary wiring pattern to undergo a metal silicidation reaction. Then, in the fourth step, the unreacted portion of the metal thin film is removed by etching to form the gate wiring and the auxiliary wiring made of metal silicide.

The metal thin film is made of one of titanium, molybdenum, nickel, tungsten and chromium. Further, it is a method of performing the heat treatment by rapid thermal annealing.

[0010]

In the display element transistor array, the resistance value of the gate wiring and the resistance value of the auxiliary wiring are lowered by the low resistance metal silicide. In addition, since the metal silicide has heat resistance, the insulating film is not contaminated by the metal silicide even when heat treatment is performed.

Further, in the above method for manufacturing a transistor array for a display element, a reaction between a silicon-based thin film and a metal thin film is performed by heat treatment so that the reaction is thermodynamically most stable and has the lowest resistance in the stoichiometric composition. Proceed in the direction of forming metal silicide. Further, by removing the unreacted metal thin film by etching, metal silicide formed in the pattern of the gate wiring and the auxiliary wiring can be obtained.

Further, since the heat treatment is performed by rapid thermal annealing, the metal silicidation reaction is promoted rather than the oxidation reaction during the heat treatment. Furthermore, since the metal thin film is made of any one of low resistance titanium, molybdenum, nickel, tungsten, and chromium, low resistance metal silicide is formed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a transistor array for a display device (hereinafter referred to as a device of the present invention) and a manufacturing method thereof (hereinafter referred to as a method of the present invention) of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an example of the device of the present invention, showing a planar type thin film transistor array.

In the figure, reference numeral 1 is a substrate made of glass, for example. On the surface of the substrate 1, active portions 2 made of, for example, polycrystalline silicon are provided in an island shape as in the conventional planar type. An insulating film 3 is formed on the substrate 1 so as to cover the active portion 2.

In this embodiment, the insulating film 3 is used as a base, and the gate wiring 4 passing over the active portion 2 is formed on the insulating film 3.
And the auxiliary wiring 5 is formed. Auxiliary wiring 5 here
Is a so-called capacitance (Cs) line, a lead line from a power source (not shown), or the like.

The feature of the device of the present invention is that the gate wiring 4 and the auxiliary wiring 5 are made of metal silicide. Examples of the metal silicide include titanium silicide, molybdenum silicide,
Examples include nickel silicide, tungsten silicide, and chromium silicide.

It is preferable that the composition of any metal silicide is a stoichiometric composition showing the lowest resistance value. The stoichiometric composition that exhibits the lowest resistance value means, for example, titanium silicide and molybdenum silicide, respectively.
₂ ) in the form of molybdenum disilicide (MoSi ₂ ). In the case of nickel silicide, tungsten silicide, and chromium silicide, they are in the form of nickel disilicide (NiSi ₂ ), tungsten disilicide (WSi ₂ ), and chromium disilicide (CrSi ₂ ), respectively.

An interlayer insulating layer 6, a source wiring 8 and a drain wiring 9 are provided on the gate wiring 4 and the auxiliary wiring 5 as in the conventional planar type. For example, in FIG. 1, an interlayer insulating film 6 is formed on the insulating film 3 in a state of covering the gate wiring 4 and the auxiliary wiring 5. Contact holes 7 are provided in the insulating film 3 and the interlayer insulating film 6 on the source and drain of the active portion 2, respectively.

Further, a source wiring 8 and a drain wiring 9 are formed on the interlayer insulating layer 6 in a state of filling the respective contact holes 7. That is, the source wiring 8
Is connected to the source side of the active part 2 and the drain wiring 9 is formed to be connected to the drain side of the active part 2. The protective insulating film 10 is provided so as to cover the entire surface of such a thin film transistor array.

As described above, in the thin film transistor array of this embodiment, the gate wiring 4 and the auxiliary wiring 5 are made of metal silicide. Metal silicide has a low resistance value, and has a lower resistance, especially if it has a stoichiometric composition. Therefore, the gate wiring 4 and the auxiliary wiring 5 have low resistance values.

Since the metal silicide has heat resistance, it does not contaminate the insulating film 3 and the interlayer insulating film 6 even if it is subjected to high temperature treatment. Therefore, in this embodiment, a thin film transistor array having no signal propagation delay and long-term reliability is realized.

Next, an example of the method of the present invention will be described. FIG. 2 is a process drawing showing an example of the method of the present invention, and FIG. 3 is a sectional view of a thin film transistor array manufactured by this process. In this embodiment, prior to the first step shown in FIG. 2A, the active portion 2 is formed on the surface of the substrate 1 made of glass by a method similar to the conventional method. Further, the insulating film 3 is formed on the substrate 1 in a state of covering the active portion 2.

For example, first, a chemical vapor deposition method (hereinafter, CV
A polycrystalline silicon film was formed on the surface of the substrate 1 by the method D). After that, the formed film was patterned into an island shape by lithography and etching to form the active portion 2. Next, the active portion 2 was subjected to ion implantation for adjusting the threshold value. Subsequently, the insulating film 3 was formed on the substrate 1 in a state of covering the active portion 2 by, for example, the CVD method.

Then, as shown in FIG. 2A, in the first step, the insulating film 3 is used as a substrate, and a silicon-based thin film 12 is formed on the insulating film 3. The silicon-based thin film 12 is made of at least a material containing silicon as a main component, and is made of, for example, CV.
It is formed by the D method.

The silicon-based thin film 12 preferably has no impurities in the portion that reacts with the metal thin film 13 described later. For example, it is preferable to form the silicon-based thin film 12 with a silicon-based thin film containing no impurities. Alternatively, the silicon-based thin film 12 may be formed by depositing a silicon-based thin film containing no impurities on the silicon-based thin film containing impurities. In this embodiment, the silicon-based thin film 12 made of, for example, polycrystalline silicon is formed to a thickness of about 80 nm.

Next, a mask pattern 11 made of a resist is formed on the surface of the silicon-based thin film 12, and then etching is performed using this mask pattern 11, so that the silicon-based thin film 12 is patterned into the gate wiring 4 shown in FIG. And a pattern of the auxiliary wiring 5.

Next, in a second step shown in FIG. 2B, the mask pattern 11 is removed. Then, an ion shower is performed using the silicon-based thin film 12 formed on the pattern of the gate wiring 4 and the pattern of the auxiliary wiring 5 as a mask to implant impurities into the source and drain regions of the active portion 2. After that, an annealing process is performed to activate the active portion 2.

Then, a metal thin film 13 is formed on the insulating film 3 in a state of covering the patterned silicon-based thin film 12. The metal thin film 13 is made of, for example, any one of titanium, molybdenum, nickel, tungsten, and chromium. Moreover, as a method of forming the metal thin film 13, for example, a sputtering method, a CVD method or the like can be mentioned. For example, in this embodiment, titanium is deposited to a thickness of about 40 nm on the insulating film 3 by the sputtering method to form the metal thin film 13.

Subsequently, in the third step shown in FIG. 2C, heat treatment is performed. Examples of the heat treatment method include rapid heating anneal such as lamp anneal and laser anneal that can perform high temperature treatment in a short time. By this heat treatment, a reaction occurs between the silicon-based thin film 12 and the metal thin film 13 formed on the surface thereof, and the silicon-based thin film 12 is metal-silicided. It should be noted that the metal thin film 13 is unreacted even if the heat treatment is performed except for the surface of the silicon-based thin film 12.

In this embodiment, the substrate 1 on which the metal thin film 13 made of titanium is formed as described above,
Lamp annealing was performed at a temperature of about 600 ° C. for about 30 seconds to perform heat treatment. As a result, a titanium silicidation reaction occurred between the silicon-based thin film 12 made of polycrystalline silicon and the metal thin film 13 made of titanium on the upper surface thereof.

Next, in a fourth step shown in FIG. 2D, the unreacted portion of the metal thin film 13 is removed by wet etching. In this wet etching, the unreacted metal thin film 13 is selectively removed, and metal silicide is formed in the pattern of the gate wiring 4 and the pattern of the auxiliary wiring 5. Therefore, the gate wiring 4 and the auxiliary wiring 5 made of metal silicide are obtained.

In this embodiment, the metal thin film 13 side which has been subjected to the titanium silicidation reaction as described above was immersed in an etching solution in which sulfuric acid and hydrogen peroxide were mixed at a ratio of 4: 1. As a result, the unreacted portion was dissolved, and the gate wiring 4 and the auxiliary wiring 5 made of titanium silicide were obtained.

After the gate wiring 4 and the auxiliary wiring 5 are obtained in this way, the interlayer insulating film 6, the contact hole 7, the source wiring 8, the drain wiring 9 and the protection are formed by a method similar to the conventional method as shown in FIG. The insulating film 10 is formed.
The interlayer insulating film 6 was formed on the insulating film 3 by the CVD method while covering the gate wiring 4 and the auxiliary wiring 5.

Next, the insulating film 3 on the source and drain of the active portion 2 is formed by lithography and etching.
A contact hole 7 was formed in each of the insulating film 6 and the interlayer insulating film 6. Next, a wiring material is deposited on the entire surface by vapor deposition or sputtering. After that, the source wiring 8 and the drain wiring 9 were formed by patterning by lithography and etching.

Then, CV is applied so as to cover these entire surfaces.
The protective insulating film 10 was provided by the D method. Through the above steps, the thin film transistor array for a display device shown in FIG. 3 is obtained.

In the above embodiment, the silicon-based thin film 12 and the metal thin film 13 are reacted with each other by heat treatment to form a metal silicide. Therefore, the silicon-based thin film 12 and the metal thin film 1
The reaction with 3 proceeds in the direction of forming a stoichiometric metal silicide that is thermodynamically most stable and has the lowest resistance value.

Actually, the gate wiring 4 is made of titanium silicide.
The sheet resistance value of the thin film transistor array having the auxiliary wiring 5 formed therein was measured during the manufacturing process. Further, the sheet resistance value was similarly measured for the conventional thin film transistor array in which the gate wiring and the auxiliary wiring were formed of only polycrystalline silicon to a thickness of about 300 nm.

As a result, the gate wiring and auxiliary wiring of the conventional thin film transistor array have a sheet resistance value of 30 Ω /
It was □. On the other hand, in the thin film transistor array of the above example, the resistance values of the gate wiring 4 and the auxiliary wiring 5 were as low as 4Ω / □.

As is clear from this result, according to the above-mentioned embodiment, the low resistance gate wiring 4 and auxiliary wiring 5 are formed. Moreover, since the metal silicide formed is known to have heat resistance, the gate wiring 4 and the auxiliary wiring 5 have heat resistance.

Further, since the above heat treatment is performed by rapid thermal annealing, the metal silicidation reaction is promoted by the oxidation reaction during the heat treatment, and the metal silicide having a desired composition is always formed with good reproducibility. Furthermore, since a low resistance material made of any one of titanium, molybdenum, nickel, tungsten and chromium is used as the material of the metal thin film 13, a low resistance metal silicide can be obtained also by this.

Further, since the unreacted metal thin film 13 is selectively removed by etching, the gate wiring 4 and the auxiliary wiring 5 in which the self-aligned structure is maintained are formed. Therefore, in this embodiment, the low resistance gate wiring 4 and the auxiliary wiring 5 can always be easily formed. For this reason,
It is possible to stably manufacture a thin film transistor array for a display device without a signal propagation delay.

Although the planar type thin film transistor has been described in the present embodiment, the structure of the present invention can be applied to the gate wiring and auxiliary wiring of various types of display element transistor arrays.

[0043]

As described above, in the device of the present invention, the gate wiring and the auxiliary wiring are formed of metal silicide which has a low resistance and does not contaminate the insulating film even when the high temperature treatment is performed. Therefore, it is possible to realize a thin film transistor array having no signal propagation delay and long-term reliability.

Further, in the method of the present invention, since the silicon-based thin film and the metal thin film are subjected to a metal silicidation reaction by heat treatment, the reaction is stoichiometrically stable and has a stoichiometric composition showing the lowest resistance value. Go in the direction of forming. Therefore, it is possible to form the gate wiring and the auxiliary wiring made of metal silicide having the stoichiometric composition showing the lowest resistance value and having heat resistance.

Further, since the unreacted metal thin film can be selectively removed by etching, it is possible to form the gate wiring and the auxiliary wiring in which the self-aligned structure is maintained. Therefore, since the low-resistance gate wiring and the auxiliary wiring can be easily formed, it becomes possible to stably manufacture the display element transistor array without signal propagation delay.

Furthermore, by performing heat treatment by rapid thermal annealing that effectively promotes the metal silicidation reaction, the metal silicide having the stoichiometric composition can be formed with good reproducibility at all times. Further, since the metal thin film is made of any one of titanium, molybdenum, nickel, tungsten and chromium which are low resistance materials, the low resistance gate wiring and the auxiliary wiring can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a device of the present invention.

FIG. 2 is a process drawing showing an example of the method of the present invention.

FIG. 3 is a cross-sectional view showing an example of a manufactured thin film transistor array.

[Explanation of symbols]

 3 Insulating film (base) 4 Gate wiring 5 Auxiliary wiring 12 Silicon-based thin film 13 Metal thin film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/786

Claims (4)

[Claims] 1. A display element transistor array having a gate wiring and an auxiliary wiring, wherein the gate wiring and the auxiliary wiring are made of metal silicide. 2. A method of manufacturing a transistor array for a display device according to claim 1, wherein a silicon-based thin film made of at least a material containing silicon as a main component is formed on a surface of a substrate, and the thin film is formed by lithography and etching. A first step of forming a gate wiring pattern and an auxiliary wiring pattern with a silicon-based thin film, and a second step of forming a metal thin film on the substrate while covering the gate wiring pattern and the auxiliary wiring pattern. And a third step of subjecting the metal thin film to a metal silicidation reaction between the metal thin film, the pattern of the gate wiring and the pattern of the auxiliary wiring by heat treatment, and of the metal thin films, the silicon-based thin film is not reacted. And a fourth step of removing a portion by etching to form a gate wiring and an auxiliary wiring made of the metal silicide. Transistor array for a display device according to claim. 3. The metal thin film comprises titanium, molybdenum,
3. The method for manufacturing a transistor array for a display element according to claim 2, wherein the method comprises the one of nickel, tungsten and chromium. 4. The method of manufacturing a transistor array for a display element according to claim 2, wherein the heat treatment is performed by rapid thermal annealing.