JPH0851215A - Semiconductor device and liquid crystal panel using it - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can have a margin when etching during formation of a contact hole, and improve the contact between a takeout electrode and a gate electrode, and raise the yield rate. CONSTITUTION:In a semiconductor device, where source and drain regions having high-concentration impurities are made in the semiconductor layer 2 provided on a substrate 1, and a gate electrode 4 is made through a gate insulating film 3 on the semiconductor layer 2, and a protective insulating film 8 is made on the source and drain regions and the gate electrode 4, and wirings are connected to the source and drain regions and the gate electrode through the contact hole 9 provided in this protective insulating film 8, an electrode layer 14 is provided below the gate electrode 4 lying under the contact hole 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly a thin film semiconductor transistor device and a liquid crystal panel using the same.

[0002]

2. Description of the Related Art A conventional coplanar thin film transistor is shown in FIGS. 16 is a plan view, FIG. 17 is a sectional view taken along line xx ′, and FIG. 18 is a sectional view taken along line yy ′.
As shown in these figures, a gate insulating film 3 is provided on a thin film semiconductor film 2 made of amorphous silicon or polycrystalline silicon formed on a transparent insulating substrate 1 made of glass or the like. A gate electrode 4 made of polycrystalline silicon is provided on the gate electrode 3. Using the gate electrode 4 as a mask, the semiconductor film 2 is doped with impurities such as phosphorus (P) and boron (B) to form source and drain regions 6 and 7, and the gate electrode 4 is included on the semiconductor film. Are covered with a protective insulating film 8. Contact holes 9, 9, 9 are provided in the protective insulating film 8, and lead-out electrodes 10 made of aluminum (Al) and the like, source / drain regions 6, 7 and gate electrodes are provided through the contact holes 9, 9, 9. 4 are connected to each other.

As described above, when forming a conventional thin film transistor, the insulating film located on the source / drain regions 6 and 7 is the insulating film 3 formed at the time of forming the gate insulating film.
The protective insulating film 8 has a two-layer structure.

On the other hand, since the gate electrode 4 is formed after the gate insulating film 3 is formed, the upper portion of the gate electrode 4 becomes a single layer of the protective insulating film 8 as shown in FIG.
Therefore, a difference occurs in the film thickness of the insulating film on the source / drain regions 6 and 7 and on the gate electrode 4. When the contact hole 9 is formed in these situations, the etchant reaches the gate electrode 4 faster because the film thickness on the gate electrode 4 is thinner than on the source / drain regions 6 and 7, and
The exposure time to the etchant becomes longer than that of the drain regions 6 and 7. At this time, since the gate electrode 4 is made of polycrystalline silicon containing impurities or the like, it is easily attacked by the etchant of the protective insulating film 8 and the gate electrode 4 is thinned.

As a result, there is a problem that the contact with the electrode 10 made of A1 or the like becomes insufficient and the yield is deteriorated due to poor contact or the like. This tendency is especially caused when the gate insulating film 3 is thick like a thin film transistor,
This frequently occurs when the etching rate of the gate insulating film 3 is very slow with respect to the protective insulating film 8.

[0006]

As an example for overcoming this problem, it is conceivable to increase the thickness of the gate electrode 4 as a whole. However, when the gate electrode 4 is thick, the thickness of the protective insulating film 8 is increased. Must be thicker, and film formation and etching take time, resulting in poor throughput. In addition, the step becomes large and the coverage of the step of the protective insulating film 8 deteriorates, which causes problems in other parts. Further, in the case of activation by laser, there is a problem that if the film thickness of the gate electrode 4 is increased, the lower part of the gate electrode 4 is not sufficiently activated.

The present invention has been made in order to solve the above-mentioned conventional problems, and provides a margin for the etching time at the time of forming a contact hole, and improves the contact between the extraction electrode and the gate electrode. An object of the present invention is to provide a semiconductor device capable of improving the yield.

A further object of the present invention is to provide a semiconductor device suitable for use in a liquid crystal panel, and to provide a liquid crystal panel in which a driver section and a pixel array section are arranged on one substrate.

[0009]

According to the present invention, a source and drain regions having high concentration impurities are formed in a semiconductor layer, and a gate electrode is formed on the semiconductor layer via a gate insulating film. In a semiconductor device in which a protective insulating film is formed on a region and a gate electrode, and wiring is connected to a source / drain region and a gate electrode through a contact hole formed in the protective insulating film, the protective insulating film is located below the contact hole. The region of the gate electrode is characterized by being formed of at least two electrode layers.

It is preferable that an electrode layer having the same type of conductivity as the gate electrode is arranged in the region of the gate electrode located below the contact hole, and the gate electrode located below the contact hole is composed of two electrode layers. .

The liquid crystal panel of the present invention is a liquid crystal panel in which a driver section and a pixel array section are provided on a transparent insulating substrate, wherein a coplanar thin film transistor is used in the driver section for pixel switching of the pixel array section. With the use of an inverted staggered thin film transistor for a transistor, the coplanar thin film transistor is provided with a source and drain region having a high concentration impurity in a semiconductor film formed on the transparent insulating substrate, and via a gate insulating film on the semiconductor film. A gate electrode is formed, a protective insulating film is formed on the source and drain regions and the gate electrode, and wiring is connected to the source, drain region and the gate electrode through contact holes provided in the protective insulating film, and Region of the gate electrode located under the contact hole Characterized in that it is formed in the electrode layer of at least two layers.

The semiconductor layer and the electrode layer of the coplanar type thin film transistor and the gate electrode of the inverted stagger type thin film transistor may be formed in the same step.

[0013]

[Function] Since the gate electrode under the contact hole is formed of two electrode layers, it has sufficient resistance even if the gate electrode is exposed to the etchant for a long time, and a good contact between the gate electrode and the wiring can be obtained. To be

By using the above semiconductor device in the driver portion of the liquid crystal panel and using the inverted staggered transistor in the transistor of the pixel array portion, good contact between the gate electrode and the wiring in the driver portion can be obtained and the yield can be improved. It is possible to provide an inexpensive liquid crystal panel that is dramatically improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a sectional view taken along line xx 'in FIG. 1, and FIG. 3 is yy' in FIG.
It is a line sectional view. The same parts as those in the conventional example are designated by the same reference numerals.

As shown in FIGS. 1 to 3, a thin film semiconductor film 2 (semiconductor layer) made of polycrystalline silicon is provided on a transparent insulating substrate 1, and a gate insulating film 3 is provided on the semiconductor film 2. ing. A gate electrode 4 made of polycrystalline silicon is provided on the gate insulating film 3. In the portion where the contact hole of the gate electrode 4 is formed, an electrode layer 14 made of polycrystalline silicon having the same conductivity type as the channel portion 2a or the gate electrode 4 is previously provided on the semiconductor thin film 2. There is.

Source / drain regions 6 and 7 are formed by doping the semiconductor film 2 with impurities such as phosphorus (P) using the gate electrode 4 as a mask. The semiconductor film 2 including the gate electrode 4 is covered with the protective insulating film 8.

A contact hole 9 is formed in the protective insulating film 8.
9, 9 are provided, and these contact holes 9, 9, 9 are provided.
The extraction electrode 10 made of aluminum (Al), the source / drain regions 6 and 7, and the gate electrode 4
Are connected respectively.

Now, according to the present invention, as shown in FIG. 3, the channel portion 2a is formed under the gate electrode 4 at a position where the contact hole 9 of the protective insulating film 8 on the gate electrode 4 is formed.
An electrode layer 14 having the same conductivity as the gate electrode 4 is provided. That is, the gate electrode region in this portion is composed of a two-layer electrode film including the gate electrode 4 and the electrode layer 14. With this structure, the region of the gate electrode 4 including the lower part of the contact hole 9 is thickened.

By adopting this structure, even if the etchant is exposed to the gate electrode 4 for a long time when the contact hole 9 is formed, it has sufficient durability.

In addition, the gap between the semiconductor 2a of the channel portion and the semiconductor film of the electrode layer 14 newly added in the present invention is narrowed,
At the same time that the gate insulating film 3 is formed, the concave portion between the channel layer 2a and the electrode layer 14 is filled so that the channel portion 2
It is possible to prevent the step difference of the gate electrode 4 due to the step difference a.

Needless to say, since the gate electrode 4 on the channel has the same structure and film thickness as the conventional one, it has no influence on the characteristics of the thin film transistor.

Next, an example of manufacturing the thin film transistor of the present invention will be described with reference to FIGS. 4 to 1
Reference numeral 2 shows a cross-sectional portion taken along the line yy 'in FIG.

As shown in FIG. 4, a polycrystalline silicon (poly-Si) film is formed on the transparent insulating substrate 1 by a plasma CVD method or the like to a thickness of 500 to 1000 angstroms to form a semiconductor for forming a channel, a source and a drain region. A first electrode layer 14, which is a feature of the present invention, is formed in a portion of the film 2 and the gate electrode that makes contact with the extraction electrode.

Next, as shown in FIG. 5, an insulating film 3 is formed on the polycrystalline silicon film 2 by a CVD method, a sputtering method or the like at a temperature of 200 to 600 ° C. for 1000 to 2000 angstroms.

Next, as shown in FIG. 6, the gate insulating film 3 on the electrode layer 14 is removed by etching using a photolithography process to expose the electrode layer 14.

Subsequently, as shown in FIG. 7, polycrystalline silicon or amorphous silicon is deposited thereon at a temperature of 200 to 500 ° C. by a CVD method, a vapor deposition method, a sputtering method, or the like.
A film having a thickness of 00 to 2000 angstrom is formed, and a gate electrode 4 is formed through a photolithography process.

In this state, as shown in FIG. 8, the gate electrode 4 is used as a mask to implant P (phosphorus) ions with an energy of 1 by ion implantation to form source and drain regions.
0 to 100 KeV, dose amount 2 × 10 ¹⁵ to 1 × 10 ¹⁶ c
Inject at m ^-2 .

Thereafter, as shown in FIG. 9, the excimer laser 15 simultaneously activates the source and drain regions 6 and 7 and restores the crystallinity of the gate electrode 4. The laser energy at this time was 150 to 400 mJ / cm ² . By this activation treatment, the impurities included in the gate electrode 4 that determine the conductivity diffuse into the electrode layer 14.

Next, as shown in FIG. 10, the protective insulating film 8 is formed.
Is formed by a CVD method, a sputtering method, or the like to a film thickness of 5000 to 10,000 angstroms.

Thereafter, as shown in FIG. 11, a contact hole 9 penetrating the protective insulating film 8 on the source / drain regions 6 and 7 and the gate electrode 4 is provided by a photolithography process. At this time, as described above, the gate electrode 4 is exposed to the etchant for a longer period of time than the source / drain regions 6 and 7, but the present invention has a sufficient film thickness and does not pose a problem.

Next, as shown in FIG. 12, a vacuum evaporation method,
A metal electrode film of Al or the like is formed from 8000 to 1 by a sputtering method.
By forming a 5000 angstrom film and patterning it by a photoresist process, the extraction electrode 1
By forming 0, a thin film transistor having a structure as shown in FIGS. 1 to 3 can be manufactured.

In this step, P ions were used for ion implantation, but of course, other B (boron), As (arsenic) ions, etc. may be used.

In the step of FIG. 4, the photolithography process is used to form the film twice,
The semiconductor film 2 and the electrode layer 14 may have different film thicknesses and film qualities.

Although the electrode layer 14 is provided in the lower layer of the gate electrode 4 in the above-described embodiment to have a two-layer structure, a metal layer such as molybdenum (Mo) is laminated on the gate electrode 4. It may have a two-layer structure.

Although the thin film transistor has been described in the above embodiments, the same effect can be obtained by applying the present invention to a MOS transistor.

As shown in FIG. 13, the active matrix liquid crystal panel comprises a pixel array section 201, a data line driver section 202 and a gate line driver section 203. Each driver section 202, 203 receives a data line 201d, The gate line 201g extends and is connected to a switching thin film transistor (TFT) 201a of each pixel of the pixel array 201, and each pixel is driven.

Here, the pixel switching TFT 20
A TFT having a low leak current is suitable for 1a. When amorphous silicon is used for the active layer, the TFT
Can be easily reduced. Therefore, a TFT using amorphous silicon is suitable as the switching TFT 201a of the pixel. For the TFT using amorphous silicon, an inverted stagger type TFT structure that causes less damage to the amorphous silicon film during film formation is suitable.

On the other hand, in the data line driver unit 202 and the gate line driver unit 203, TFT can be used as a driver transistor. By configuring the driver units 202 and 203 also with TFTs, the driver units 202 and 203 and the pixel array unit 201 can be provided on the same substrate. This driver part 20
Since the TFTs used for Nos. 2 and 203 are required to operate at high speed, polycrystalline silicon is used for the active layer. When the reverse stagger structure is used for the TFT using polycrystalline silicon, the gate electrode is damaged when the polycrystalline silicon is formed, and therefore the coplanar structure is generally used.
However, this coplanar TFT has a problem that the gate electrode is damaged when the contact hole is formed, as described above.

Therefore, in the present invention, the coplanar type TFT of this embodiment shown in FIGS. 1 to 3 is used for the data line driver section 202 and the gate line driver section 203, and the inverted stagger type amorphous is used as the pixel switching TFT 201a. A silicon TFT was used.

FIG. 14 shows a pixel switching TFT 20.
1A is a schematic cross-sectional view showing the structure of 1a, and FIG. 15 is a plan view showing an embodiment using the present invention for a shift register of a data line driver unit 202 and a gate line driver unit 203.

The first electrode layer 14 made of a polycrystalline silicon film is formed on the transparent insulating substrate 1 at a position located in the contact hole of the gate electrode of each TFT forming the driver portions 202 and 203. The first electrode layer 4 is
As described above, the channel and the semiconductor film to be the source / drain region are formed at the same time. Further, at this time, the gate electrode 31 made of the polycrystalline silicon film of the switching TFT 201a is simultaneously formed.

Then, the shift register shown in FIG. 15 is formed according to the steps of FIGS. 4 to 12 described above. In FIG. 15, 4 is a gate electrode, 6 and 7 are source and drain regions, 9 is a contact hole, 10 is a gate wiring, and 14 is a first electrode layer.

Further, the inverted stagger type TFT shown in FIG.
After the gate electrode 31 is formed at the same time as the first electrode layer 14, an inverted stagger type amorphous silicon TFT is formed by a known method. That is, the gate electrode 31
A gate insulating film 32 made of silicon oxide or the like is formed thereon, and an i-type amorphous silicon layer 33 serving as an active layer is provided on the gate insulating film 32. Then, an n ⁺ type amorphous silicon film 34 serving as a source and a drain region is provided on the amorphous silicon layer 33, and a pixel electrode 35 such as ITO is provided on the amorphous silicon film 34. In FIG. 14, 36 is an etching stopper and 37 is a passivation film.

In this way, the data line driver unit 2
02, the coplanar TFT of this embodiment shown in FIGS. 1 to 3 is used for the gate line driver section 203,
A liquid crystal panel using an inverted stagger type amorphous silicon TFT as the pixel switching TFT 201a is obtained.

[0046]

As described above, according to the present invention, even if the gate electrode is exposed to the etchant for a long time when the contact hole is formed, it has sufficient resistance and has good contact with the wiring. Is obtained.

Further, according to the present invention, there is a margin in the etching time at the time of forming the contact hole, which leads to the improvement of the yield. Further, the gap between the semiconductor film in the channel portion and the lower electrode layer can be narrowed to prevent the gate electrode from being stepped.

Further, by using the above semiconductor device in the driver portion of the liquid crystal panel and using the inverted stagger type transistor in the transistor of the pixel array portion, good contact between the gate electrode and the wiring in the driver portion can be obtained. The yield can be dramatically improved, and an inexpensive liquid crystal panel can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a thin film transistor according to the present invention.

FIG. 2 is a sectional view taken along line x-x ′ of FIG.

FIG. 3 is a cross-sectional view taken along line y-y ′ of FIG.

FIG. 4 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the thin film transistor according to the present invention.

FIG. 13 is a structural explanatory view of an active matrix liquid crystal panel.

FIG. 14 is a schematic cross-sectional view of an inverted staggered thin film transistor.

FIG. 15 is a plan view in which the present invention is used for a shift register of a driver section of a liquid crystal panel.

FIG. 16 is a plan view showing a conventional thin film transistor.

FIG. 17 is a sectional view taken along line x-x ′ of FIG. 16.

FIG. 18 is a cross-sectional view taken along line y-y ′ of FIG. 16.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Polycrystalline silicon semiconductor film 3 Gate insulating film 4 Gate electrode 6 Source region 7 Drain region 8 Protective insulating film 9 Contact hole 10 Extraction electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/336 9056-4M H01L 29/78 627 A

Claims (5)

[Claims] 1. A source / drain region having a high concentration of impurities is formed in a semiconductor layer, and a gate electrode is formed on the semiconductor layer via a gate insulating film.
In a semiconductor device in which a protective insulating film is formed on the drain region and the gate electrode, and wiring is connected to the source, drain region and gate electrode through the contact hole provided in the protective insulating film, the semiconductor device is located below the contact hole. The semiconductor device, wherein the region of the gate electrode to be formed is formed of at least two electrode layers. 2. The semiconductor device according to claim 1, wherein an electrode layer having the same kind of conductivity as that of the gate electrode is arranged in a region of the gate electrode located under the contact hole. 3. A source and drain region having a high concentration of impurities is formed in a semiconductor film formed on an insulating substrate, and a gate electrode is formed on the semiconductor film via a gate insulating film. A thin film semiconductor device in which a protective insulating film is formed on the gate electrode, and wiring is connected to the source / drain region and the gate electrode through the contact hole provided in the protective insulating film, respectively. A thin film semiconductor device, characterized in that an electrode layer having the same conductivity type as that of the gate electrode is arranged between the gate electrode and the substrate. 4. A liquid crystal panel having a driver section and a pixel array section provided on a transparent insulating substrate, wherein a coplanar thin film transistor is used for the driver section, and an inverted staggered thin film transistor is used for a pixel switching transistor of the pixel array section. Together with the coplanar thin film transistor, the semiconductor film formed on the transparent insulating substrate is provided with source and drain regions having high concentration impurities, a gate electrode is formed on the semiconductor film via a gate insulating film, A protective insulating film is formed on the source / drain region and the gate electrode, and wiring is connected to the source / drain region and the gate electrode through a contact hole formed in the protective insulating film, and is located under the contact hole. The area of the gate electrode is at least 2
A liquid crystal panel, which is formed of two electrode layers. 5. The liquid crystal panel according to claim 4, wherein the semiconductor film and the electrode layer of the coplanar thin film transistor and the gate electrode of the inverted staggered thin film transistor are formed in the same step.