JPH08511655A - 縦の溝を有する高電圧用の半導体デバイス - Google Patents
縦の溝を有する高電圧用の半導体デバイスInfo
- Publication number
- JPH08511655A JPH08511655A JP6522384A JP52238494A JPH08511655A JP H08511655 A JPH08511655 A JP H08511655A JP 6522384 A JP6522384 A JP 6522384A JP 52238494 A JP52238494 A JP 52238494A JP H08511655 A JPH08511655 A JP H08511655A
- Authority
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- Prior art keywords
- layer
- groove
- substrate
- depth
- doped
- Prior art date
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- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000001960 triggered effect Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 239000010454 slate Substances 0.000 claims description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 90
- 235000012431 wafers Nutrition 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/111—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors
- H01L31/1113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors the device being a photothyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26145—Flow barriers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13034—Silicon Controlled Rectifier [SCR]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Thyristors (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 半導体のサブストレート(22)に、相対する第1表面と第2表面があり 、 不純物をドーピングした第1層(23)が、前記サブストレートの第1表面 側に配設され、 前記サブスレート(21)の第2表面側に溝(30)が形成され、前記溝( 30)には深さと表面があり、 前記溝(30)の深さにより、前記第1層(23)と前記第2層(31)と の間の距離が事実上決定されるように、不純物をドーピングした第2層(31) が、前記溝(30)の表面に配設されていることを特徴とする半導体デバイス( 21)。 2. 前記サブストレート(22)と前記第2層(31)とは、反対の性質を持 つようにドーピングされている請求項1に記載の半導体デバイス。 3. 前記第1層(23)と前記サブストレート(22)とは、反対の性質を持 つようにドーピングされている請求項2に記載の半導体デバイス。 4. 不純物をドーピングした第3層(24)が、前記第1層(23)の隣に配 設されている請求項3に記載の半導体デバイス。 5. 前記第3層(24)と第2層(31)とは、反対の性質を持つようにドー ピングされている請求項 4に記載の半導体デバイス。 6. 前記第2層(31)、および第3層(24)に取り付けられたオーム接点 (26、36)を設けた請求項5に記載の半導体デバイス。 7. リードフレーム(34)を設け、前記リードフレーム(34)に、前記第 2層と接触するオーム接点(36)がマウントされている請求項6に記載の半導 体デバイス。 8. 半導体のサブストレート(22)に、上側の表面と下側の表面とがあり、 制御層(23)は、前記サブストレート(22)の上部表面側に配設され、 カソード層(24)は、前記制御層(23)の上部表面に配設され、 カソード接点(26)は、前記カソード層(24)に取り付けられ、 溝(30)は、前記サブストレート(22)の下部表面側に形成され、前記 溝(30)には、深さと表面があり、 前記溝(30)の深さにより、アノード層(31)と制御層(23)との間 の間隙を事実上決定するように、アノード層(31)は、前記溝(30)の表面 に配設され、 アノード接点(36)は、前記溝(30)に取り付けられ、前記アノード層 (31)と接触すること を特徴とするシリコンの制御整流素子(SCR)のデバイス(21)。 9. 前記サブストレート(22)と前記アノード層(31)とは、反対の性質 を持つようにドーピングされている請求項8に記載のSCRデバイス。 10. 前記制御層(23)と前記サブストレート(22)とは、反対の性質を 持つようにドーピングされている請求項9に記載のSCRデバイス。 11. 前記第カソード層(24)と制御層(23)とは、反対の性質を持つよ うにドーピングされている請求項10に記載のSCRデバイス。 12. リードフレーム(34)を設け、前記リードフレーム(34)に、前記 アノード接点(36)がマウントされている請求項11に記載のSCRデバイス 。 13. N型のサブストレート(22)に、上側の表面と下側の表面とがあり、 第1P+制御層(23)は、前記サブストレート(22)の上部表面側に配 設され、 N+層(24)が、前記P+層(23)の上部表面に配設され、 カソード接点(26)は、前記N+層(24)に取り付けられ、 溝(30)は、前記サブストレート(22)の下部表面側に形成され、前記 溝(30)には、深さと 表面があり、 前記溝(30)の深さにより、第1P+層(23)と第2P+層(31)との 間の間隙を事実上決定するように、第2P+層(31)は、前記溝(30)の表 面に配設され、 アノード接点(36)は、前記溝(30)に取り付けられ、前記第2P+層 (31)と接触することを特徴とするシリコンの制御整流素子(SCR)のデバ イス(21)。 14. リードフレーム(34)を設け、前記リードフレーム(34)に、前記 アノード接点(36)がマウントされている請求項13に記載のSCRデバイス 。 15. 半導体のサブストレート(22)に、相対する第1表面と第2表面とを 設けるステップと、 前記サブストレートの第1表面側に不純物をドーピングした第1層(23) を拡散するステップと、 前記サブスレート(21)の第2表面側に、深さと表面のある溝(30)を エッチングするステップと、 前記溝(30)の深さにより、前記第1層(23)と前記第2層(31)と の間の距離が事実上決定されるように、不純物をドーピングした第2層(31) を、前記溝(30)の表面に拡散するステップ とを有することを特徴とする半導体チップの製造方 法。 16. 前記拡散するステップには、前記サブストレート(22)に対し反対の 性質を持つように、前記第1層(23)および第2層(31)をドーピングする ことを含む請求項15に記載の方法。 17. 前記第1層(23)と第3層(24)とが反対の性質を持つようにドー ピングされ、不純物をドーピングした第3層(24)を、第1層(23)に拡散 することを含む請求項16に記載の方法。 18. 前記第2層(31)に接するオーム接点(と、第3層(24)に接する オーム接点とが配設され、前記第2層(31)に配設されたオーム接点を、リー ドフレーム(34)上にマウントする請求項17に記載の方法。 19. N型のサブストレート(22)に、上側の表面と下側の表面とを設ける ステップと、 第1P+層(23)を、前記サブストレート(22)の上部表面側に拡散す るステップと、 N+層(24)を、前記P+層(23)の上部表面に拡散するステップと、 透過性の酸化層(25)を前記第1P+層(23)の一部の領域に形成する ステップと、 カソード接点(26)を、前記N+層(24)に配設するステップと、 深さと表面を持つ溝(30)を、前記サブストレ ート(22)の下部表面にエッチングするステップと、 前記溝(30)の深さにより、第1P+層(23)と第2P+層(31)との 間の間隙を事実上決定するように、第2P+層(31)は、前記溝(30)の表 面に拡散するステップと、 アノード接点(36)は前記溝(30)に取り付けられ、前記第2P+層( 31)と接触することを特徴とする光によりトリガされるシリコンの制御整流素 子(SCR)のデバイス(21)の製造方法。 20. 前記アノード接点(36)をリードフレームにマウントすることを含む 請求項19に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4083093A | 1993-03-31 | 1993-03-31 | |
US08/040,830 | 1993-03-31 | ||
PCT/US1994/003556 WO1994023455A1 (en) | 1993-03-31 | 1994-03-31 | High-voltage, vertical-trench semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08511655A true JPH08511655A (ja) | 1996-12-03 |
JP3718223B2 JP3718223B2 (ja) | 2005-11-24 |
Family
ID=21913209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52238494A Expired - Fee Related JP3718223B2 (ja) | 1993-03-31 | 1994-03-31 | 縦の溝を有する高電圧用の半導体デバイス |
Country Status (5)
Country | Link |
---|---|
US (2) | US5445974A (ja) |
EP (1) | EP0692145A1 (ja) |
JP (1) | JP3718223B2 (ja) |
KR (1) | KR100329672B1 (ja) |
WO (1) | WO1994023455A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2784801B1 (fr) | 1998-10-19 | 2000-12-22 | St Microelectronics Sa | Composant de puissance portant des interconnexions |
DE102005035346A1 (de) * | 2004-08-19 | 2006-03-09 | Atmel Germany Gmbh | Verlustleistungsoptimierter Hochfrequenz-Koppelkondensator und Gleichrichterschaltung |
US8074622B2 (en) | 2005-01-25 | 2011-12-13 | Borgwarner, Inc. | Control and interconnection system for an apparatus |
JP4629490B2 (ja) * | 2005-05-09 | 2011-02-09 | 三菱電機株式会社 | 誘電体分離型半導体装置 |
US7582917B2 (en) * | 2006-03-10 | 2009-09-01 | Bae Systems Information And Electronic Systems Integration Inc. | Monolithically integrated light-activated thyristor and method |
US7446424B2 (en) * | 2006-07-19 | 2008-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor package |
CN104380470B (zh) * | 2012-05-18 | 2018-01-02 | 富士电机株式会社 | 半导体装置 |
EP2851946A1 (en) * | 2013-09-19 | 2015-03-25 | Nxp B.V. | Surge protection device |
US20200335826A1 (en) * | 2019-04-18 | 2020-10-22 | International Business Machines Corporation | Lithium energy storage |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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NL252855A (ja) * | 1959-06-23 | |||
US3370209A (en) * | 1964-08-31 | 1968-02-20 | Gen Electric | Power bulk breakdown semiconductor devices |
US3808673A (en) * | 1971-03-17 | 1974-05-07 | Monsanto Co | Opto-isolator devices and method for the fabrication thereof |
DE2237086C3 (de) * | 1972-07-28 | 1979-01-18 | Semikron Gesellschaft Fuer Gleichrichterbau Und Elektronik Mbh, 8500 Nuernberg | Steuerbares Halbleitergleichrichterbauelement |
US4051507A (en) * | 1974-11-18 | 1977-09-27 | Raytheon Company | Semiconductor structures |
DE2610942C2 (de) * | 1976-03-16 | 1983-04-28 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum Herstellen eines Halbleiterbauelements mit in einem Halbleiterkörper monolithisch integrierten Halbleiterelementeinheiten |
JPS56150863A (en) * | 1980-04-21 | 1981-11-21 | Nec Corp | Bidirectional photothyristor |
DE3151141A1 (de) * | 1981-12-23 | 1983-06-30 | Siemens AG, 1000 Berlin und 8000 München | Halbleiterbauelement mit hoher stossstrombelastbarkeit |
JPH0682859B2 (ja) * | 1984-08-28 | 1994-10-19 | 財団法人半導体研究振興会 | 静電誘導型半導体光検出器 |
EP0262485A1 (de) * | 1986-10-01 | 1988-04-06 | BBC Brown Boveri AG | Halbleiterbauelement mit einer Ätzgrube |
US5344794A (en) * | 1993-03-31 | 1994-09-06 | Siemens Components, Inc. | Method of making a semiconductor chip |
-
1993
- 1993-09-10 US US08/120,147 patent/US5445974A/en not_active Expired - Fee Related
-
1994
- 1994-03-31 KR KR1019950704209A patent/KR100329672B1/ko not_active IP Right Cessation
- 1994-03-31 JP JP52238494A patent/JP3718223B2/ja not_active Expired - Fee Related
- 1994-03-31 WO PCT/US1994/003556 patent/WO1994023455A1/en not_active Application Discontinuation
- 1994-03-31 EP EP94911750A patent/EP0692145A1/en not_active Withdrawn
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1996
- 1996-03-29 US US08/625,638 patent/US5793063A/en not_active Expired - Fee Related
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US5445974A (en) | 1995-08-29 |
WO1994023455A1 (en) | 1994-10-13 |
JP3718223B2 (ja) | 2005-11-24 |
KR100329672B1 (ko) | 2002-08-13 |
EP0692145A1 (en) | 1996-01-17 |
US5793063A (en) | 1998-08-11 |
KR960702680A (ko) | 1996-04-27 |
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