JPH0850798A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device having redundancy function in which high capacity, low power consumption, low price and high reliability are realized by providing a redundancy fuse circuit, a switching signal generation circuit, and a selection circuit. CONSTITUTION:A redundancy fuse circuit FUS (not shown) designates a memory array having a defect among memory arrays 1-01 each holding defect information and including a data line and a word line. A switching signal generation circuit GEN delivers a switching signal based on defect information received from the redundancy fuse circuit FUS through terminals RSL, BL1-3. Selection circuits SEL111-118, 121-128 are provided while corresponding to two adjacent memory arrays among the memory arrays 1-01 and connected electrically with one of them depending on the switching signal. The defect information comprises a plurality of pieces of binary information and the number of switching signals is higher than that of the binary information. This constitution decreases the area being occupied by the elements constituting means for holding the defect information thus realizing a high capacity device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device, and for example, it is used in a digital switch integrated circuit having a multi-bit structure, a large capacity and a speech path memory or a control memory used in a time division digital exchange. And particularly effective technology.

[0002]

2. Description of the Related Art ISDN (Integrated Service Digital)
There is a digital switch integrated circuit that constitutes a time switch of a time-division digital exchange such as Network: integrated digital communication network. These digital switch integrated circuits include a speech path memory formed on a single semiconductor substrate and its control memory.

Japanese Patent Laid-Open No. 3-119284 discloses a speech path memory and a control memory.

February 1987, "Digest Of Technical Papars," ISSCC Digest Of Technical Papars, pages 290 to 291 and 431, are digital switch integrated circuits incorporating a static memory. A circuit is disclosed.

A memory redundancy repair system is described in, for example, Japanese Patent Application Laid-Open No. 2-89299.

[0006]

With the increase in the scale of ISDN, it is necessary to increase the capacity and speed of the speech path memory and its control memory built into the digital switch integrated circuit, and these memories are integrated into one semiconductor. When mounted on a chip, redundant relief is indispensable. The following problems were encountered in adopting the memory redundancy repair method. In other words, in the redundancy repair method of repairing a defective memory array by shifting the input / output of a memory array composed of a plurality of words, data lines and memory cells, when the ratio of the memory array to the redundant memory array becomes large, it is rephrased. When the number of input / output data becomes large, the inventor has clarified that the switching circuit at the time of redundancy repair becomes complicated and the number of redundant fuses holding information in the redundant memory array increases. . As a result, it has become clear that there is a problem that the chip area increases and the labor for disconnecting the redundant fuse increases.

A first object of the present invention is to reduce the number of redundant fuses for retaining defect information when shifting the input / output to / from the memory array to repair the defective memory array, and suppress the increase of the chip area due to the redundant fuses. Is.

A second object of the present invention is to provide a semiconductor integrated circuit device which suppresses an increase in power consumption.

[0009]

The outline of a typical one of the present invention will be briefly described as follows. That is, a memory array including a data line, a word line, and a memory cell, a means for holding defect information for indicating a defective memory array in the memory array,
A switching signal generating circuit for outputting a switching signal based on the defect information, and one of two memory arrays adjacent to each other according to the switching signal are provided respectively corresponding to two adjacent memory arrays of the memory arrays. A semiconductor memory circuit device is constituted by a selection circuit electrically coupled. The defect information is a plurality of binary information, and the number of switching signals is larger than the number of binary information.

Further, the supply of the first or second power supply voltage to the unused memory array or the sense amplifier provided corresponding to the unused memory array is stopped.

Further, the means for holding the defect information is as follows:
Includes a fuse element that holds specific information by physically processing it by irradiating it with a laser beam,
The switching signal generation circuit is a ROM (Read Only Memory)
including.

[0012]

It is possible to reduce the number of fuse elements. This makes it possible to reduce the total area occupied by the switching signal generating circuit and the fuse element. Further, it is possible to reduce the power consumption of the unused memory array and sense amplifier. As a result, it is possible to prevent an increase in the area of a semiconductor integrated circuit device having a redundant function (for example, a digital switch integrated circuit) and realize low power consumption, and at the same time, a device equipped with these semiconductor memory circuit devices (for example, a time division digital exchange) ) Large capacity, low power consumption, low price and high reliability.

[0013]

FIG. 1 is a schematic block diagram of a chip of an embodiment of a digital switch integrated circuit to which the present invention is applied. The semiconductor integrated circuit device of this embodiment is a custom logic LSI (Large Scale Integrated Circui).
t) and a dedicated gate array etc. are formed on one semiconductor substrate. In the following circuit diagrams, a MOSFET (metal oxide semiconductor field effect transistor) whose channel (back gate portion) has an arrow is a P-channel type and an N-channel MOSF to which an arrow is not added.
Shown separately from ET. In this specification, MOS
FET is a generic term for an insulated gate field effect transistor.

Each block shown in the drawing is drawn according to the geometrical arrangement on the actual semiconductor substrate on which the semiconductor integrated circuit device is formed. In the semiconductor integrated circuit device of this embodiment, bonding pads PAD are arranged side by side on the periphery of the chip CHP1. Input / output buffer I / O BUFs are arranged side by side inside these bonding pads. An internal logic area LOG and two memory macros RAM1 and RAM2 which are on-chip memories are formed inside the input / output buffer. The memory macros RAM1 and RAM2 are, for example, a speech path memory and a control memory, respectively. The internal logic area is constituted by a gate array, and logic circuits for various signals and data for the memory macro RAM1 and RAM2 are formed. The logic circuit is, for example,
A CPU, MPU, cache controller, bus controller, and the like. Memory macro RAM1 and RA
M2 is an SRAM (Static Random Access Memory) circuit or a DRAM (Dynamic Random Access Memory) circuit. Further, the semiconductor integrated circuit device has a redundant fuse circuit FUS. The configuration and function of the redundant fuse circuit will be described later.

FIG. 2 is a chip schematic block diagram of another embodiment of a digital switch integrated circuit to which the present invention is applied. The difference from FIG. 1 is that the digital switch integrated circuit has eight memory macros RAM1 to RAM7. Memory macro RAM1 and RAM
2 has substantially the same memory capacity. The memory macro RAMs 3 to 5 have a memory capacity different from that of the memory macro RAM 1 and have substantially the same memory capacity. The memory macro RAMs 7 and 8 have different memory capacities from the memory macro RAMs 1 and 5 and have substantially the same memory capacity.

FIG. 3 shows an embodiment of the redundant fuse circuit. The redundant fuse circuit FUS1 has QN1 to
QN4 is an NMOS transistor (N-channel Metal Oxid)
e Semiconductor transistor), F1 to F4 are fuse parts (fuse elements), and INV1 to INV4 are inverter circuits. One of the fuses has a first power supply voltage Vc.
bound to receive c. One of the source / drain paths of each NMOS transistor is coupled to the other of the corresponding fuse part, and the other of the source / drain paths of each NMOS is connected to a second power supply voltage lower than the first power supply voltage.
It is coupled to receive the power supply voltage GND. Each inverter circuit is coupled between the other of the corresponding fuse parts and a corresponding one of the RSL terminal, the BSL1 terminal to the BSL3 terminal. The redundant fuse circuit is composed of a fuse part F1, an inverter INV1 and an NMOS transistor QN1 and indicates whether or not redundant relief is performed.
First fuse circuit for holding value information, and binary information indicating which memory array is used or not used among memory arrays in memory blocks included in each memory macro RAM1 and RAM2 described later. And a second fuse circuit for holding binary information indicating which one of the memory arrays has a defect. The second fuse circuit includes fuse parts F2 to F2.
4, including inverters INV2 to INV4 and NMOS transistors QN2 to QN4. First and second
If each fuse part of the fuse circuit is not cut, Q
The potentials of the drain nodes of N1 to QN4 are at "HIGH" level, and the outputs of the inverters INV1 to INV4 that receive the drain nodes of QN1 to QN4 are "LOW".
It becomes a level. That is, RSL terminal, BSL1 terminal ~
The potential of the BSL3 terminal is set to LOW level. When the fuse portion is cut off, the potentials of the drain nodes of QN1 to QN4 become LOW level, and the inverters INV1 to INV1 whose inputs are the drain nodes of QN1 to QN4.
The output of V4 becomes HIGH level, QN1 to QN4 are turned on, and the outputs of INV1 to INV4 are held at HIGH level. That is, the potentials of the RSL terminal and the BSL1 to BSL3 terminals are set to the HIGH level.

When each memory block includes eight memory arrays and one redundant memory array to input / output 8-bit data, when the level of the RSL terminal is "L", the redundant memory array is not used. Redundant relief is not done,
When the level of the RSL terminal is "H", the redundant memory array is used to perform redundant relief. Also, BSL1 to BSL3
The combination of terminal levels dictates which of the eight memory arrays is unused.
The fuse part is not particularly limited, but is made of aluminum A
It is formed in the vicinity of the chip surface by metal such as 1 and chromium Cr or polysilicon. The fuse portion can be physically cut by applying high energy such as a laser beam.

FIG. 4 is a detailed block diagram of the memory macro RAM 1 included in the semiconductor integrated circuit device of FIG. The memory macro RAM1 includes eight memory blocks BLK1 to BLK8. Up to 8-bit data is simultaneously input to each memory block, and up to 8-bit data is simultaneously output. Therefore, the memory macro is
A maximum of 64 bits of data is input or output simultaneously. That is, the memory macro can have a structure of x64 bits. Di1 to Di64 are write data for the memory blocks BLK1 to BLK8, and are input from a logic circuit formed in the logic area LOG on the same chip or from the outside of the chip. Do1
To Do64 are read data from each of the memory blocks BLK1 to BLK8, and are logical areas L on the same chip.
It is output to the logic circuit formed in the OG or to the outside of the chip.

FIG. 5 is a detailed configuration diagram of the memory macro RAM 1 included in the semiconductor integrated circuit device of FIG. 1 and the memory block of FIG. The memory macro RAM 1 includes a control circuit CON in addition to the memory blocks BLK1 to BLK8.
T, a decoder circuit, and a switching signal generation circuit GEN. The control circuit receives the address signal ADDR, the clock signal CLK and the read / write signal R / W from the logic circuit formed in the logic area LOG on the same chip or from the outside of the chip, and controls the operations of the decoder circuit DEC and the like. To do. The decoder circuit receives the decode address signal from the control circuit and outputs the decode signal dec decoded based on the decode address signal to each memory block BLK.
1 to BLK8. Switching signal generation circuit GEN
Is a redundant fuse circuit FUS formed on the same chip.
RSL terminal, BSL1 terminal or BSL3 terminal, and receives RSL signal, BSL1 signal or BSL3 signal. Further, the switching signal generation circuit GEN is
The predetermined switching signals S1 to S8 based on the signal, the BSL1 signal to the BSL3 signal are output. The memory block 1 receives the first input data Di1 to Di8, respectively.
Select circuits SEL111 to 118, memory array MEMO
RY-ARRAY1-8, MEMORY-ARRAY0
1, sense amplifiers 11 to 19 and second selection circuit SEL1
21 to 128. The memory block 8 has a first selection circuit S for receiving the input data Di56 to Di64.
EL811-818, memory array MEMORY-AR
RAY56 to 64, MEMORY-ARRAY08, sense amplifiers 81 to 89, and second selection circuit SEL821 to
828. The first selection circuit is coupled to the corresponding two adjacent memory arrays of the memory arrays, and transmits the input data to one of the two coupled memory arrays according to at least one of the switching control signals. To do. At least one memory cell included in each of the memory arrays 1 to 64 and MEMORY-ARRAY 01 to 08 is selected according to the decode signal dec. The sense amplifier receives a read signal (read data) from the corresponding memory array and outputs a signal (data) based on the read signal. The second selection circuit is coupled to the corresponding two adjacent sense amplifiers of the sense amplifiers, and selects one of the data based on the read signals from the adjacent memory arrays according to at least one of the switching control signals. It receives one and outputs it as output data.

FIG. 6 shows the memory array MEMOR of FIG.
A detailed circuit diagram of Y-ARRAY1 is shown. In the figure, memory cells MC1 and MC4 having PMOS transistors and NMOS transistors and word lines XS1 to XS are provided.
S256, data line pair D0, / D0 to D16, / D1
6. PMOS (P-channel Metal Oxide Semidoncducotr)
Transistors P1 to P4, NMOS (N-channel Metal O
xide semiconductor transistor N1 to N4, common data line pair CD, / CD, and write amplifier WA.
The memory array has a memory capacity of 256 * 16 = 4K. Word lines XS1 to XS256, gates of PMOS transistors P1 to P4 and NMOS transistor N1
The decode signal dec is supplied to the gates of N4 to
One predetermined memory cell is selected according to the decode signal. Then, predetermined data according to the input data Di1 is written to the selected memory cell via the first selection circuit SEL111, the write amplifier WA, the common data line pair CD, / CD, and the NMOS transistor. Or
Data line, PMOS transistor, common data line pair C
The data according to the data held in the selected memory cell is transmitted to the sense amplifier SA11 via D and / CD.

FIG. 7 shows the memory block BLK1 of FIG.
3 is a block circuit diagram for explaining the transmission paths of the input data and the output data of FIG. In the figure, each of the first selection circuit and the second selection circuit is a first switch element S.
W1 and the second switch element SW2 are included.

FIG. 8 shows a first defect repairing method for the memory array of the memory block of FIG.
In the figure, transmission lines for input data and output data of the memory block BLK1 in the normal mode (redundancy unused mode) in which the fuse part included in the redundant fuse circuit FUS is not blown are shown by thick lines. Memory array MEMORY ARRAY0 shaded in the figure
1 is an unused memory array. In the normal mode, according to at least one of the switching control signals,
The first switch element included in each of the first and second selection circuits is turned off, and the second switch element is turned on. As a result, the memory array MEMORY-ARRA
Y1-8 are used.

FIG. 9 shows a defect relief mode (redundancy use) in which at least one of the fuse parts included in the redundant fuse circuit FUS is cut in the first defect relief method for the memory array of the memory block of FIG. An example of a transmission path of the input data and the output data of the memory block BLK1 in the (mode) is indicated by a thick line.
Memory array MEMORY ARR shaded in the figure
It is assumed that AY4 has a defect. In this case, the input data and the output data are transmitted through the route drawn by the thick line. The first switch elements included in the first and second selection circuits corresponding to the memory arrays above the memory array MEMORY ARRAY4 including a defect are turned on, and the second switch elements are turned on.
The switch element is made non-conductive. Further, the first switch elements included in the first and second selection circuits corresponding to the memory arrays below the memory array MEMORY ARRAY4 including the defect are set to the non-conductive state, and the second switch elements are set to the conductive state. To be done. As a result, the memory array including a defect is not used, and the memory arrays MEMORY-ARRAY1 to 3 and MEMORY- that do not include a defect are used.
ARRAY5-8 and MEMORY-ARRAY1 are used.

By using the first defect relieving method in this way, the number of logic circuit stages in the transmission path of the input data and the output data in the normal mode and the defect relieving mode (switch elements in the first and second selection circuits) (Including the number of stages) are substantially equal. This has the effect of making the access speeds in the defect relief mode and the normal mode equal.

FIG. 10 shows a second defect repairing method for the memory array of the memory block shown in FIG. In the figure, transmission lines for input data and output data of the memory block BLK1 in the normal mode (redundancy unused mode) in which the fuse part included in the redundant fuse circuit FUS is not blown are shown by thick lines. Memory array MEMORY ARRAY shaded in the figure
5 is an unused memory array. According to at least one of the switching control signals, the first switch elements included in the first and second selection circuits corresponding to the memory arrays above the memory array MEMORY ARRAY5 arranged in the center are rendered conductive, and the second switch elements are turned on. The switch element is made non-conductive. In addition, the memory array MEMO
The first switch elements included in the first and second selection circuits corresponding to the memory arrays below the RY ARRAY 5 are turned off, and the second switch elements are turned on. By this, MEMORY-ARRAY1-4
And MEMORY-ARRAY 6-8 are used.

By using the second defect relieving system as described above, in addition to the effect of the first defect relieving system, it is possible to simplify the configuration of the switching signal generating circuit, which will be described in detail later. It is possible to reduce the area.

FIG. 11 shows the switching signal generating circuit G of FIG.
It is a concrete block diagram of EN. The switching signal generation circuit includes a data storage circuit MEM, a second decoding circuit DEC2,
A reset circuit RSC is included. The data storage circuit includes unit storage circuit groups Mem1 to Mem8 including a unit data storage circuit Unit Mem, and each of the unit data storage circuits has a logic “1” (“HIGH” level) or a logic “0” (“LOW”). Holds binary data that is regarded as a (level). Each unit memory circuit group includes eight unit memory circuits. The second decode circuit receives the BSL1 signal to BSL signal 3 from the redundant fuse circuit FUS, and outputs the second decode signals dec21 to 28 to the corresponding unit storage circuit groups. According to the BSL1 signal to the BSL signal 3, a predetermined one of the second decode signals is set to the selection level, and one of the unit memory circuit groups is selected. The data held in the unit storage circuit of the selected unit storage circuit group is transmitted to the reset circuit RSC. The reset circuit includes an AND gate circuit AN including a first input coupled to receive the read data from the unit storage circuit and a second input coupled to receive the RSL signal.
Including D1 to AND8. When the RSL signal is set to the “LOW” level, the reset circuit switches the data held in the unit circuit of the selected unit circuit group from the switching signals s1 to s1.
Output as s8. Switching signal s that is set to "LOW" level when the RSL signal is "HIGH" level
1 to s8 are output. Each unit memory circuit Unit in the figure
"0" and 1 "written in the Mem box are
It indicates that the logical data "0" or the logical "1" is held in the unit memory circuit. To further explain with specific examples, BSL1 signal, BSL2 signal, BSL signal
When the combination of the 3 signal and the RSL signal is “0001”, only the second decode signal dec21 is set to the selection level, the unit memory circuit group Mem1 is selected, and “11111” is selected.
The switching control signals s1 to s8 of 111 ″ are output.
BSL1 signal, BSL2 signal, BSL3 signal and RSL
When the signal combination is "0011", only the second decode signal dec22 is set to the selection level, the unit memory circuit group Mem2 is selected, and the switching control signals s1 to s8 of "01111111" are output. Similarly, when the combination of the BSL1 signal, the BSL2 signal, the BSL3 signal and the RSL signal is “1111”, the second decode signal dec
Only 28 is set to the selection level, and the unit memory circuit group Mem8
Is selected, and the switching control signals s1 to s8 of "00000001" are output. If the memory array MEMORY-ARRAY1 in FIG. 8 is defective, the unit memory circuit group Mem1 is selected and the memory array MEMO is selected.
When the RY-ARRAY8 has a defect, the unit memory circuit group Mem8 is selected. That is, the unit circuit group Mem
1 to Mem8 are the memory array MEMORY-A of FIG.
Each of the RRAYs 1 to 8 holds information for indicating that it has a defect.

FIG. 12 shows the unit memory circuit group Mem of FIG.
2 is a detailed circuit diagram of FIG. The unit memory circuit Unit Mem1 included in the unit memory circuit group Mem1 is one PMO.
S transistor QP1 and one NMOS transistor Q
The unit memory circuit Unit Mem8 including N7 includes one PMOS transistor QP2 and one NMOS transistor QN8. One of the source / drain paths of the PMOS transistors QP1 and QP2 is coupled to receive the first power supply voltage Vcc, and its gate is coupled to the second decode signal dec via the inverter circuit INV7.
21 are coupled to receive the inverted signal. One of source / drain paths of NMOS transistors QN7 and QN8 is coupled to receive second power supply voltage GND, and a gate is coupled to receive second decode signal dec21. The other of the source / drain paths of the PMOS transistor QP1 is insulated from the signal line L1,
For example, it is in a floating state. The other of the source / drain paths of the NMOS transistor QN7 is coupled to the signal line L1 by a contact between layers. The signal line L1 is coupled to one input of the AND gate circuit AND8. The other of the source / drain paths of the PMOS transistor QP2 is coupled to the signal line L8 by a contact between layers. The signal line L8 is coupled to one input of the AND gate circuit AND8. The other of the source / drain paths of the NMOS transistor QN8 is insulated from the signal line L8 and is in a floating state. As a result, the unit memory circuit UnitMem1 is "LOW" when the second decode signal is at "HIGH" level.
The level signal is output to the signal line L1. On the other hand, in the unit memory circuit UnitMem8, the decode signal is "HIGH".
When it is set to the level, it outputs a "HIGH" level signal to the signal line L8.

As described above, the unit memory circuit is Unit
Mem is one PMOS transistor and one NM
It is composed of an OS transistor. The PMOS transistor and the NMOS transistor are redundant fuse circuits FUS.
This is a very small area compared to the area occupied by the fuse portion included in. Therefore, it is possible to reduce the area occupied by the redundant information holding circuit section including the redundant fuse circuit and the switching signal generating circuit. This effect becomes more remarkable as the number of memory arrays included in one memory block increases.

FIG. 13 is a detailed circuit block diagram of the memory block 1 of FIG. In the figure, the latch circuit LATCH11 coupled to the sense amplifiers SA11 to SA19 is shown.
To 19, buffer circuits BUF1 to 8 coupled to the second selection circuits SEL121 to SEL128, and sense amplifier SA
The buffer circuit BUF9 and the exclusive NOR gate circuits ENOR1 to EN7 which are coupled to the buffer 9 are additionally written.
The second selection circuit SEL121 includes a PMOS transistor Q
P3, QN4, NMOS transistors QN9, QN10
And an inverter circuit INV9. Second selection circuit SE
L121 is a PMOS transistor QP3, QN4, N
It includes MOS transistors QN9 and QN10 and an inverter circuit INV10. The second selection circuit SEL122 has P
MOS transistors QP5, QN6, NMOS transistors QN11, QN12 and inverter circuit INV10
including. The second selection circuit SEL128 includes PMOS transistors QP7 and QN8 and an NMOS transistor QN1.
3, QN14 and an inverter circuit INV11.

The source / drain paths of the transistors QP3 and QN9 are coupled between the input of the buffer circuit BUF1 and the latch circuit LATCH11, and the transistor QN
The gate of the transistor QP3 is coupled to the output of the inverter circuit INV9, and the gate of the transistor QP3 is coupled to the inverter circuit IV9.
It is coupled to the input of NV9. The input of the inverter circuit INV9 is coupled to receive the switching control signal s1. The source / drain paths of the transistors QP4 and QN10 are the input of the buffer circuit BUF1 and the latch circuit LATC.
The gate of the transistor QP4 is coupled to the gate of the transistor QN9, and the gate of the transistor QN10 is coupled to the gate of the transistor QP3.

The source / drain paths of the transistors QP5 and QN11 are coupled between the input of the buffer circuit BUF2 and the latch circuit LATCH12, and the transistor QN1 is connected.
The gate of 1 is coupled to the output of the inverter circuit INV10, and the gate of the transistor QP5 is connected to the inverter circuit IV10.
Coupled to the input of NV10. Inverter circuit INV1
The 0 input is coupled to receive the switching control signal s2. The source / drain paths of the transistors QP6 and QN12 are the input of the buffer circuit BUF2 and the latch circuit LA.
The gate of the transistor QP6 is coupled to the gate of the transistor QN11, and the gate of the transistor QN12 is coupled to the gate of the transistor QP5.

The source / drain paths of the transistors QP7 and QN13 are coupled between the input of the buffer circuit BUF8 and the latch circuit LATCH18, and are connected to the transistor QN1.
The gate of the transistor 3 is coupled to the output of the inverter circuit INV11, and the gate of the transistor QP7 is connected to the inverter circuit IV11.
It is coupled to the input of NV11. Inverter circuit INV1
The one input is coupled to receive the switching control signal s8. The source / drain paths of the transistors QP8 and QN14 are the input of the buffer circuit BUF8 and the latch circuit LA.
The gate of the transistor QP8 is coupled to the gate of the transistor QN13, and the gate of the transistor QN14 is coupled to the gate of the transistor QP7. The input of the inverter circuit INV8 is coupled to receive the switching control signal s1, and its output is the sense amplifier SA1 and the memory array MEMORY-.
It is bound to ARRAY1. The exclusive NOR gate circuit ENOR1 has inputs for receiving the switching control signals s1 and s2, the sense amplifier SA12 and the memory array M.
It has an output coupled to EMORY-ARRAY2.
The exclusive NOR gate circuit ENOR2 has an input for receiving the switching control signals s2 and s3 and a sense amplifier S.
A13 and the output coupled to the memory array MEMORY-ARRAY3. The exclusive NOR gate circuit ENOR3 includes an input for receiving the switching control signals s7 and s8, a sense amplifier SA18, and a memory array ME.
It has an output coupled to MORY-ARRAY8. The buffer circuits 1 to 8 output the output data Do1 to Do8. The buffer circuit BUF9 has an input coupled to the switching control signal s8 and an output coupled to the sense amplifier SA19 and the memory array MEMORY-ARRAY9.

The sense amplifiers SA11 to 19 and the second selection circuits SEL121 to 128 have switching control signals s1 to s1.
Each is controlled by the combination of s8. In particular,
The second selection circuit SEL12 (i) (1 ≦ i ≦ 8) has a latch circuit LATCH1 (i + 1) and a buffer circuit B when the switching control signal s (i) is at “H” (“HIGH”) level.
UF (i) is controlled to be electrically connected, and when the switching control signal s (i) is at "L" (LOW) level, the latch circuit LATCH1 (i) and the buffer circuit BUF (i) are electrically connected. Control to connect to the sense amplifier SA1.
(I) (i = 1, 9) and memory array MEMORY-
ARRAY (i) (i = 1, 9) is a switching control signal s
When (i) is at "H" level, it is in a non-operating state. In the sense amplifier SA1 (i) (2≤i≤8), the switching control signal s (i-1) is at "H" level and the switching control signal s (i) is
Is "L" level or the switching control signal s (i-1) is "
When it is at L "level and the switching control signal s (i) is at" H "level, it is in a non-operation state. For example, the memory array ME.
When the MORY-ARAY4 is defective, the switching control signals s1 to s8 are set to "00011111". As a result, the defective memory array MEMORY-AR
It is possible to perform defect relief on AY4.
Sense amplifiers corresponding to memory arrays that are defective or otherwise unused are inverter circuits INV8, ENOR1-7.
And ST which is an output signal from the buffer circuit BUF9
When the C1 signal to the STC9 signal are set to "L" level,
The first power supply voltage and the second power supply voltage smaller than the first power supply voltage are not supplied. As a result, the operation of the sense amplifier corresponding to the unused memory array having a defect is stopped. Therefore, low power consumption of the semiconductor memory circuit device is realized.

FIG. 14 shows the memory array MEM of FIG.
It is an example of a specific circuit diagram of ORY-ARRAY1. In the figure, a first input coupled to the word line WL1 for receiving the decode signal dec and a second input for receiving the STC1 signal,
An AND gate circuit AND9 having an output coupled to the word line WL11, a first input coupled to the word line WL2 receiving the decode signal dec and a second input receiving the STC1 signal, and an output coupled to the word line WL12 are provided. It includes an AND gate circuit AND12 and a memory cell coupled to word lines WL11 and WL12. When the level of the STC1 signal is "L" level, the word line WL11
The levels of WL12 and WL12 are fixed to the "L" level which is a non-selection level regardless of the level of the decode signal dec. This prevents the memory cells included in the unused memory array from being selected due to a defect or the like. As a result, the power consumption of the unused memory array can be reduced.

FIG. 15 shows the memory array MEMO of FIG.
It is an example of a specific circuit diagram of RY-ARRAY1. The difference between FIG. 14 and FIG. 14 is that in FIG.
A source / drain path coupled to the power supply voltage GND and an NMOS receiving a gate for receiving the STC1 signal.
This is a point including the transistor QN15. Transistor Q
N15 is, when the STC1 signal is set to "L" level,
It is turned off. Therefore, the second memory cell
The power supply voltage supply is stopped. As a result, it is possible to further reduce the power consumption of the unused memory array.

FIG. 16 is an embodiment of the detailed circuit block diagram of FIG. In this embodiment, the redundant fuse circuit FUS is used.
Has a first fuse circuit including one fuse portion and a second fuse circuit including five fuse portions. First
The fuse circuit has an RSL terminal, and the second fuse circuit has a BSL1 terminal to a BSL5 terminal. The memory macros RAM1 and RAM2 include eight memory blocks, and each memory block has a maximum of 32 memory arrays and one redundant memory array. The redundant fuse circuit FUS is provided commonly to the memory macros 1 and 2,
The RSL terminal and the BSL1 to BSL5 terminals are coupled to the memory macros 1 and 2. Memory macro R
When there is a defect in the memory array in a certain memory block in AM1, the memory array corresponding to each memory block of the memory macro RAM1 and the memory memory array included in the memory macro RAM2 and corresponding memory memory array of each memory block 8 * 2 in total. = 16 memory arrays are simultaneously replaced by redundant memory arrays. As a result, it is possible to replace the defective memory array with the redundant memory array regardless of which of the memory macros 1 and 2 has the defective memory array. That is, it is possible to reduce the occupied area of the redundant fuse circuit as compared with the case where the redundant fuse circuit is independently provided for each memory macro unit.

FIG. 17 is an embodiment of the detailed circuit block diagram of FIG. In this embodiment, the redundant fuse circuit FUS is used.
Has a first fuse circuit including three fuse parts and a second fuse circuit including five fuse parts. First
The fuse circuit has RSL1 terminals to RSL6 terminals, and the second fuse circuit has BSL1 terminals to BSL5 terminals.
Has terminals. Each of the memory macros 1, 2 and 6 includes eight memory blocks, each memory block having a maximum of 32 memory arrays and one redundant memory array. The three fuse parts of the first fuse circuit are respectively memory macro RAM1, RAM2 and R.
The RSL1 terminal is connected to the memory macro RAM1, the RSL2 terminal is connected to the memory macro RAM2, and the RSL6 terminal is connected to the memory macro RAM6. The second fuse circuit is provided commonly to the memory macros 1, 2 and 6, and the BSL1 terminal to the BSL5 terminal are connected to the memory macros RAM1 and RAM2.
And RAM6. Memory macro RAM1
When there is a defect in a memory array of a certain memory block included in the memory macro RAM1, it is possible to replace only the corresponding eight memory arrays included in each of the eight memory blocks included in the memory macro RAM1 with the redundant memory array. It As a result, the degree of freedom in redundant relief is improved.

FIG. 18 is an example of a detailed circuit block diagram of FIG. In this embodiment, the redundant fuse circuit FUS is 3
It has a first fuse circuit including one fuse portion and a second fuse circuit including fifteen fuse portions. The first fuse circuit has RSL1 to RSL6 terminals, and a second fuse circuit
The fuse circuit has BSL1 terminals to BSL15 terminals. Memory macro RAM1, RAM2 and RAM6
Each of which includes eight memory blocks, each memory block having a maximum of 32 memory arrays and one redundant memory array. The three fuse parts of the first fuse circuit are provided respectively corresponding to the memory macros RAM1, RAM2, and RAM6, the RSL1 terminal is coupled to the memory macro RAM1, the RSL2 terminal is coupled to the memory macro RAM2, and the RSL6 terminal. Are coupled to the memory macro RAM 6. The second fuse circuit is 3
It is divided into one group and each has five fuse parts. Each group has a memory macro R
A corresponding to AM1, RAM2 and RAM6, B
SL1 terminal or BSL5 terminal is memory macro RAM1
, BSL6 terminals to BSL10 terminals are connected to the memory macro RAM 2, and BSL11 terminals to BSL15 terminals are connected to the memory macro RAM 6. As a result, if a memory array included in the memory macro RAM1 among the memory arrays included in the memory macro RAM1, RAM2, and RAM6 is defective, the memory macro RAM1
It is possible to replace only the corresponding eight memory arrays of each memory block with a redundant memory array. Furthermore, an arbitrary memory array included in an arbitrary memory block of the memory macro RAM 1 and a memory macro RA
Even when an arbitrary memory array included in an arbitrary memory block of M2 and an arbitrary memory array included in an arbitrary memory block of the memory macro RAM 6 have a defect at the same time, these defective memory arrays are replaced by redundant memory arrays. Can be replaced with. This allows
The degree of freedom of redundant relief is further improved.

FIG. 19 is an embodiment of the detailed circuit block diagram of FIG. In this embodiment, the redundant fuse circuit FUS is used.
Is a first fuse circuit including two fuse parts and 10
It has the 2nd fuse circuit which has individual fuse parts. The first fuse circuit has an RSL1 terminal and an RSL6 terminal, and the second fuse circuit has a BSL1 terminal to a BSL1 terminal.
It has 10 terminals. Each of the memory macros RAM1, RAM2, and RAM6 includes eight memory blocks, and each memory block has a maximum of 32 memory arrays and one redundant memory array. One of the two fuse parts of the first fuse circuit is
Each of the other fuse units is provided in common to the memory macros RAM1 and RAM2, and the other fuse unit is the memory macro RA.
It is provided corresponding to M6. The RSL1 terminal is coupled to the memory macro RAM1 and RAM2, and is connected to the RSL6.
The terminal is coupled to the memory macro RAM 6. Second
The fuse circuit is divided into two groups, each having five fuse parts. One of the groups is commonly provided to the memory macros RAM1 and RAM2, and the BSL1 terminal to the BSL5 terminal are coupled to the memory macros RAM1 and RAM2. The other one of the groups is provided corresponding to the memory macro RAM 6, and the BSL6 terminal to the BSL10 terminal are coupled to the memory macro RAM 6.

FIG. 20 is an embodiment of the detailed circuit block diagram of FIG. In this embodiment, the redundant fuse circuit FUS is used.
Has a first fuse circuit including two fuse parts and a second fuse circuit including five fuse parts. First
The fuse circuit has an RSL1 terminal and an RSL2 terminal, and the second fuse section has a BSL1 terminal to a BSL5 terminal. Each of the memory macros RAM1 to RAM4 includes eight memory blocks, and each memory block has a maximum of 32 memory arrays and one redundant memory array. One of the two fuse parts of the first fuse circuit is provided commonly to the memory macros RAM1 and RAM2, and the other fuse part is provided.
One fuse part is a memory macro RAM3 and a RAM
4 are commonly provided. The RSL1 terminal is
RS connected to the memory macros RAM1 and RAM2
The L3 terminal is coupled to the memory macro RAM3 and RAM4. The second fuse circuit is a memory macro RA
The terminals BSL1 to BSL5 are commonly provided for the M1 to RAM4 and the memory macros RAM1 to RAM are used.
Connected to four.

FIG. 21 is an embodiment of a schematic chip block diagram of a semiconductor memory circuit device including a memory macro. The difference between FIG. 2 and this figure is that the redundant fuse circuits FUS are separately arranged at two locations, and each is formed substantially at a corner of the chip. The redundant fuse circuit is arranged apart from the memory macro RAMs 1 to 6 and the internal logic area LOG. Thus, when the fuse portion included in the redundant fuse circuit is irradiated with the laser configuration to electrically disconnect the wiring, the work is reliably performed without damaging the memory macro RAMs 1 to 6 and the internal logic area LOG. Is possible. Further, the number of signal wirings for connecting the redundant fuse circuit FUS and the switching signal generation circuit included in the memory macro can be reduced.
As a result, the area of the signal wiring can be reduced.

FIG. 22 is an embodiment of a schematic chip block diagram of a semiconductor memory circuit device including a memory macro. The difference between FIG. 2 and this figure is that the redundant fuse circuits are separately arranged at two places, and each is substantially closer to the center of the chip than the input / output circuit and is formed at a corner of the chip. is there.

FIG. 23 shows a modification of the circuits included in the first and second fuse circuits of FIG. In the figure, a fuse portion (fuse element) having one end connected to the first power supply voltage Vcc, an input coupled to the other end of the fuse portion, and R
An NMOS having an inverter circuit INV12 having an output coupled to the SL terminal (or BSL terminal), a source drain path having one end coupled to the input of the inverter circuit, and a gate coupled to the output of the inverter circuit INV12. A transistor QN16 and an NMOS transistor QN15 having a source / drain path coupled between the other end of the source / drain path of the NMOS transistor QN16 and the second power supply voltage GND and a gate receiving the standby test control signal SIDS. . As a result, by setting the standby test control signal SIDS to the “L” level during the standby current test, the NMOS transistor QN15 is made non-conductive,
The source-drain path of the NMOS transistor QN16 and the second power supply voltage can be electrically disconnected. This makes it possible to perform the first and second standby tests.
It is possible to cut off the leak current of the fuse circuit.

FIG. 24 shows a modification of the first and second fuse circuits of FIG. The difference from FIG. 3 is that an NMOS transistor QN18 having a gate for receiving the signal φSIDS is added. After cutting the fuse portion F8, a pulse signal such as the signal φSIDS is applied. If the fuse part F8 is completely cut, N
The input of the inverter is set to the ground potential by the MOS transistor QN18. However, when the fuse portion F8 is not completely cut off, when a pulse signal such as the signal φSIDS is applied, the NMOS transistor QN18 is provided between the power supply potential Vcc and the ground terminal GND.
Current flows through. By measuring this current, it is possible to confirm whether or not the fuse portion F8 is completely cut.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the semiconductor integrated circuit device of FIG. 1 includes the speech path memory and the control memory, but the invention is not limited to this. In FIG. 4, the number of memory blocks included in the memory macro is not limited. The number of input / output data of the memory block is not limited by the embodiment.
In FIG. 6, the memory cell is a CMOS type static type, but may be a high dielectric load type static type. Furthermore, the memory cell may be of a dynamic type, or may be a FRAM (Ferromagnetc Random Access Mem).
ory) and other memory cell configurations.
Further, although it is described in FIG. 6 that 16 data line pairs are commonly coupled to one common data line pair,
The number of data line pairs coupled to the pair of common data lines is not limited to this and may be any number. In FIG.
The configuration of the switching signal generation circuit is not limited to this embodiment, and for example, the second decoder may include the BSL1 signal and BSL2 signal.
The configuration may be such that it receives the signal, the BSL3 signal, and the RSL signal, and outputs nine second decoded signals.
Further, the number of unit storage circuits included in the data storage circuit is not limited, and the pattern of data held in the unit storage circuit is arbitrary. In FIG. 13, the latch circuit may not be included.

In the above description, the invention made mainly by the present invention is applied to a static RAM used as a speech path memory or the like incorporated in a time-division digital switch integrated circuit, which is a usage statement which is a background of sparseness. Although the case has been described, the present invention is not limited thereto, and the present invention can be applied to, for example, a static RAM alone or a gate array integrated circuit device.

[0048]

According to the present invention, a memory array including data lines, word lines and memory cells, means for holding defect information for indicating a defective memory array among the memory arrays, and switching based on the defect information. A switching signal generating circuit for outputting a signal, and a switching signal generating circuit provided corresponding to two adjacent memory arrays of the memory arrays and electrically coupled to one of the two adjacent memory arrays according to the switching signal. A semiconductor memory circuit device is configured by the selection circuit. The defect information is a plurality of binary information, and the number of switching signals is larger than the number of binary information. First to sense amplifier provided corresponding to unused memory array or unused memory array
Alternatively, the supply of the second power supply voltage is stopped. The means for holding the defect information includes a fuse element for holding specific information by physically processing it by irradiating a laser beam or the like, and the switching signal generating circuit is a RO
Includes M (Read Only Memory). As a result, the number of fuse elements can be reduced, and the total area occupied by the switching signal generation circuit and the fuse elements can be reduced. Further, it is possible to reduce the power consumption of the unused memory array and sense amplifier. As a result, it is possible to prevent an increase in the area of a semiconductor integrated circuit device having a redundant function and to realize low power consumption, and also to increase the capacity and the capacity of a device (for example, a time division digital exchange) equipped with these semiconductor memory circuit devices. It is possible to promote power consumption, price reduction, and high reliability.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a chip of an embodiment of a digital switch integrated circuit to which the present invention is applied.

FIG. 2 is a chip schematic block diagram of another embodiment of a digital switch integrated circuit to which the present invention is applied.

FIG. 3 is an example of a redundant fuse circuit.

FIG. 4 is a detailed configuration diagram of a memory macro RAM1 included in the semiconductor integrated circuit device of FIG.

5 is a detailed configuration diagram of a memory macro RAM 1 included in the semiconductor integrated circuit device of FIG. 1 and a memory block of FIG. 4;

FIG. 6 is a diagram of the memory array MEMORY-A of FIG. 5;
It is a detailed circuit diagram of RRAY1.

7 is a block circuit diagram for explaining a transmission path of input data and output data of the memory block BLK1 of FIG.

8 is an explanatory diagram of a defect relief system for the memory array of the memory block of FIG. 7;

9 is an explanatory diagram of a defect relief system for the memory array of the memory block of FIG. 7;

10 is an explanatory diagram of a defect relief system for the memory array of the memory block of FIG. 7;

11 is a switching signal generation circuit GE of FIG.
It is a concrete block diagram of N.

12 is a unit memory circuit group Mem1 of FIG.
3 is a detailed circuit diagram of FIG.

FIG. 13 is a detailed circuit block diagram of the memory block 1 of FIG.

FIG. 14 is a diagram of the memory array MEMOR of FIG. 13;
It is an example of a specific circuit diagram of Y-ARRAY1.

FIG. 15 is a diagram of the memory array MEMOR of FIG. 13;
It is an example of a specific circuit diagram of Y-ARRAY1.

16 is an example of a detailed circuit block diagram of FIG. 2;

17 is an example of a detailed circuit block diagram of FIG. 2. FIG.

FIG. 18 is an example of a detailed circuit block diagram of FIG. 2.

19 is an example of a detailed circuit block diagram of FIG. 2;

20 is an example of a detailed circuit block diagram of FIG. 2. FIG.

FIG. 21 is an embodiment of a schematic block diagram of a chip of a semiconductor memory circuit device including a memory macro.

FIG. 22 is an example of a schematic chip block diagram of a semiconductor memory circuit device including a memory macro.

FIG. 23 is a modification example of a circuit included in the first and second fuse circuits of FIG. 3.

FIG. 24 is a modification example of the circuit included in the first and second fuse circuits of FIG. 3.

[Explanation of symbols]

I / O BUS: Input / output buffer CHP1: Chip PAD: Bonding pad LOG: Internal logic area FUS: Redundant fuse circuit RAM1-8: Memory macro F1-F4: Fuse part (fuse element) INV1-INV4, 7-12: Inverter Circuit N1 to N4, QN1 to QN4, QN7 to QN16: NM
OS transistors P1 to P4, QP1 to QP8: PMOS transistors BLK1 to BLK8: Memory block GEN: Switching signal generation circuit CONT: Control circuit DEC: Decoder circuit DEC2: Second decoder circuit SEL111 to SEL828: Selection circuit SA11 to 89: Sense amplifier WA: Write amplifier MC, MC1 to MC4: Memory cells SW1 and SW2: Switch element MEM: Data storage circuit Mem1 to Mem8: Unit storage circuit group RSC: Reset circuit AND1 to AND8: AND gate circuit Unit Mem: Unit data storage circuit LATCH11 -19: Latch circuit BUF1-9: Buffer circuit ENOR1-7: Exclusive NOR gate circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoichi Sato 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Kan Shimono, Kodaira, Tokyo 5-20-1 Jitsumizu Honcho, Ichi, Japan, within Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor Masami Hasegawa 5-20-1, Kamimizuhoncho, Kodaira, Tokyo Metropolitan Government I Engineering Co., Ltd. (72) Inventor Yoshio Iioka 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd. (72) Inventor Hisashi Kobayashi Kodaira, Tokyo 5-20-1 Jousuihonmachi Hitate Cho El SII Engineering Co., Ltd. (72) Inventor Nunokawa Right 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Masao Mizukami 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center ( 72) Inventor Kozaburo Kurita 2326 Imai, Hitachi, Ltd., Ome, Tokyo Metropolitan area Device development center, Hitachi, Ltd. (72) Masatoshi Kawashima 2326, Imai, Ome city, Tokyo, Hitachi Ltd. Device development center, Hitachi, Ltd.

Claims (7)

[Claims] 1. A data line, a plurality of word lines, and a plurality of memory cells, each of which is coupled to the one data line and a corresponding one of the plurality of word lines. A plurality of memory arrays, a means for holding defect information for designating a memory array having a defect among the plurality of memory arrays, a plurality of switching signals receiving the defect information, and based on the defect information And a switching signal generating circuit for outputting the two adjacent memory arrays of the plurality of memory arrays, and adjacent two corresponding memory cells according to at least one of the plurality of switching signals.
A semiconductor memory circuit device formed on one semiconductor substrate having a plurality of selection circuits electrically coupled to one of two memory arrays, wherein the defect information is a plurality of binary information. A semiconductor memory circuit device, wherein the number of the plurality of switching signals is larger than the number of the plurality of binary information. 2. The memory cells according to claim 1, wherein the plurality of memory cells included in the plurality of memory arrays are of a static type, and supplied with a first power supply voltage and a second power supply voltage smaller than the first power supply voltage. The plurality of memory cells included in at least one of the plurality of memory arrays include at least one of the first power supply voltage and the second power supply voltage according to at least one of the plurality of switching signals. A semiconductor memory circuit device characterized by being separated from one. 3. The switching signal generating circuit according to claim 1, wherein the switching signal generating circuit receives the defect information and outputs a plurality of decoding signals, and the switching circuits receive the plurality of decoding signals. A data storage circuit for outputting a signal, wherein the data storage circuit includes a plurality of data storage groups provided corresponding to the plurality of decoded signals, and each of the data storage groups is A plurality of unit data storage circuits for outputting the data stored in each of the plurality of decode signals, and a plurality of switching signal lines for transmitting the plurality of switching signals. , Each of the unit data storage circuits has a source voltage coupled between a first voltage and a corresponding one of the plurality of switching signal lines. P-channel MOS having a gate for receiving a signal based on the corresponding one of the in-path and the plurality of decoded signals
A source drain path coupled between the FET, a second voltage less than the first voltage and a corresponding one of the plurality of switching signal lines, and a corresponding one of the plurality of decoded signals. A semiconductor memory circuit device comprising: an N-channel MOSFET having a gate for receiving a signal. 4. A data line, a plurality of word lines, and a plurality of memory cells, each of which is coupled to the one data line and a corresponding one of the plurality of word lines. A plurality of memory arrays, a means for holding defect information for designating a memory array having a defect among the plurality of memory arrays, a plurality of switching signals receiving the defect information, and based on the defect information And a switching signal generation circuit for outputting the two, and read from two adjacent memory arrays of the plurality of memory arrays, which are respectively provided corresponding to the two adjacent memory arrays of the plurality of memory arrays. Two input terminals for receiving signals, respectively, and the above two according to at least one of the plurality of switching signals.
A semiconductor memory circuit device formed on one semiconductor substrate having a plurality of selection circuits each having an output terminal for outputting a signal based on one of the read signals input to one input terminal. The defect information is a plurality of binary information, and the number of the plurality of switching signals is larger than the number of the plurality of binary information. 5. A plurality of data lines, a plurality of word lines, and a plurality of memory cells, each of which is coupled to the one data line and a corresponding one of the plurality of word lines. And a memory array of, respectively provided corresponding to the plurality of memory arrays,
A plurality of sense amplifiers including an output terminal for outputting a signal based on a signal read from one of the plurality of memory cells included in the corresponding memory array; Means for holding defect information for indicating a defective memory array; a switching signal generation circuit for receiving the defect information and outputting a plurality of switching signals based on the defect information; Two input terminals that are respectively provided corresponding to two adjacent sense amplifiers of the sense amplifiers and that are respectively coupled to output terminals of two adjacent sense amplifiers of the plurality of sense amplifiers; An output for outputting a signal based on one of the signals input to the two input terminals according to at least one of the switching signals. A semiconductor memory circuit device formed on one semiconductor substrate having a plurality of selection circuits having terminals, wherein the defect information is a plurality of binary information, and the number of the plurality of switching signals is A semiconductor memory circuit device characterized by being larger than the number of a plurality of binary information. 6. The plurality of sense amplifiers according to claim 3, wherein the plurality of sense amplifiers are coupled so that a first power supply voltage and a second power supply voltage smaller than the first power supply voltage are supplied. At least one of the amplifiers is disconnected from at least one of the first power supply voltage and the second power supply voltage according to at least one of the plurality of switching signals. apparatus. 7. A data line, a plurality of word lines, and a plurality of memory cells, each of which is coupled to the one data line and a corresponding one of the plurality of word lines. A plurality of memory arrays; a means for holding defect information for indicating a defective memory array among the plurality of memory arrays; and a plurality of switching units that receive the defect information and, based on the defect information, A switching signal generating circuit for outputting a signal, and a switching signal generating circuit provided respectively corresponding to two adjacent memory arrays of the plurality of memory arrays. Two input terminals for receiving read signals respectively, and two input terminals according to at least one of the plurality of switching signals.
A plurality of first selection circuits each having an output terminal for outputting a signal based on one of the read signals input to one input terminal, and two adjacent memory arrays of the plurality of memory arrays In accordance with at least one of the plurality of switching signals and an input terminal for receiving one of the plurality of write signals, respectively, in response to the write signal input to the input terminal. A semiconductor memory circuit device formed on one semiconductor substrate having a plurality of second selection circuits each having an output terminal for outputting a signal based on the one of two corresponding memory arrays, The defect information is a plurality of binary information, and the number of the plurality of switching signals is larger than the number of the plurality of binary information. .