JPH08505725A - 命令実行を制御するため命令にタグを割り当てるシステム及び方法 - Google Patents
命令実行を制御するため命令にタグを割り当てるシステム及び方法Info
- Publication number
- JPH08505725A JPH08505725A JP6516016A JP51601694A JPH08505725A JP H08505725 A JPH08505725 A JP H08505725A JP 6516016 A JP6516016 A JP 6516016A JP 51601694 A JP51601694 A JP 51601694A JP H08505725 A JPH08505725 A JP H08505725A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- instructions
- tag
- register file
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title description 22
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003542 behavioural effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 特許請求の範囲は以下の通りである。 1.命令にタグを割り当てるシステムであって、該システムは、 実行する命令を格納するメモリ・ユニットと、 前記メモリ・ユニットに接続され、実行する前に前記命令をデコードするた めの命令取り出しユニットと、 前記命令取り出しユニットに接続され、デコードされた命令を格納するため のレジスタ・ファイルと、 前記レジスタ・ファイルに接続され、デコードされた命令にタグを付けるた めのタグを保持するための複数のスロットから成る待ち行列と、 前記レジスタ・ファイル、及び、前記待ち行列に接続され、 (a)デコードされた命令にタグを割り当て、 (b)実行された命令の完了を監視し、そして (c)実行された命令の完了時に待ち行列のタグを進めるための、 制御ユニットから成り、さらに 前記レジスタ・ファイルは、デコードされた命令を、その命令に割り当てられた タグで決められたレジスタ・ファイル中のアドレス位置に格納することを特徴と するシステム。 2.請求項第1項のシステムであって、 前記レジスタ・ファイルは、複数の読み出しアドレス可能ポート及びそれに 対応した読み出し出力ポートを含み、 前記のスロットは各々、対応する前記読み出しアドレス可能ポートの1個に 接続され、 デコードされた命令は、そのデコードされた命令に割り当てられたタグによ って読み出し可能状態にされる読み出し出力ポートから読み出されることを特徴 とするシステム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/999,648 US5604912A (en) | 1992-12-31 | 1992-12-31 | System and method for assigning tags to instructions to control instruction execution |
US07/999,648 | 1992-12-31 | ||
PCT/US1993/012309 WO1994016385A1 (en) | 1992-12-31 | 1993-12-16 | System and method for assigning tags to instructions to control instruction execution |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08505725A true JPH08505725A (ja) | 1996-06-18 |
JP3531167B2 JP3531167B2 (ja) | 2004-05-24 |
Family
ID=25546575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51601694A Expired - Lifetime JP3531167B2 (ja) | 1992-12-31 | 1993-12-16 | 命令実行を制御するため命令にタグを割り当てるシステム及び方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5604912A (ja) |
EP (1) | EP0677188B1 (ja) |
JP (1) | JP3531167B2 (ja) |
KR (1) | KR100295081B1 (ja) |
DE (1) | DE69305366T2 (ja) |
WO (1) | WO1994016385A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021166030A (ja) * | 2020-04-07 | 2021-10-14 | 晶心科技股▲ふん▼有限公司Andes Technology Corporation | 読み取りシフタを備えたプロセッサおよびそれを用いた制御方法 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539911A (en) * | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5493687A (en) | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
DE69311330T2 (de) * | 1992-03-31 | 1997-09-25 | Seiko Epson Corp., Tokio/Tokyo | Befehlsablauffolgeplanung von einem risc-superskalarprozessor |
EP0638183B1 (en) * | 1992-05-01 | 1997-03-05 | Seiko Epson Corporation | A system and method for retiring instructions in a superscalar microprocessor |
US5628021A (en) | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
WO1994016384A1 (en) * | 1992-12-31 | 1994-07-21 | Seiko Epson Corporation | System and method for register renaming |
US5604912A (en) * | 1992-12-31 | 1997-02-18 | Seiko Epson Corporation | System and method for assigning tags to instructions to control instruction execution |
US5822575A (en) * | 1996-09-12 | 1998-10-13 | Advanced Micro Devices, Inc. | Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction |
US6035424A (en) * | 1996-12-09 | 2000-03-07 | International Business Machines Corporation | Method and apparatus for tracking processing of a command |
US5948098A (en) * | 1997-06-30 | 1999-09-07 | Sun Microsystems, Inc. | Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines |
US6237083B1 (en) | 1998-02-13 | 2001-05-22 | Advanced Micro Devices, Inc. | Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence |
US6883090B2 (en) * | 2001-05-17 | 2005-04-19 | Broadcom Corporation | Method for cancelling conditional delay slot instructions |
US6785804B2 (en) * | 2001-05-17 | 2004-08-31 | Broadcom Corporation | Use of tags to cancel a conditional branch delay slot instruction |
US6859874B2 (en) * | 2001-09-24 | 2005-02-22 | Broadcom Corporation | Method for identifying basic blocks with conditional delay slot instructions |
US20030041073A1 (en) * | 2001-08-21 | 2003-02-27 | Collier Josh D. | Method and apparatus for reordering received messages for improved processing performance |
US6813704B1 (en) * | 2001-12-20 | 2004-11-02 | Lsi Logic Corporation | Changing instruction order by reassigning only tags in order tag field in instruction queue |
US7398375B2 (en) * | 2002-04-04 | 2008-07-08 | The Regents Of The University Of Michigan | Technique for reduced-tag dynamic scheduling and reduced-tag prediction |
US7734901B2 (en) * | 2005-10-31 | 2010-06-08 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
US7711934B2 (en) * | 2005-10-31 | 2010-05-04 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US7594079B2 (en) | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US9946547B2 (en) * | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
US10229066B2 (en) * | 2016-09-30 | 2019-03-12 | Arm Limited | Queuing memory access requests |
US11709681B2 (en) | 2017-12-11 | 2023-07-25 | Advanced Micro Devices, Inc. | Differential pipeline delays in a coprocessor |
US11567554B2 (en) * | 2017-12-11 | 2023-01-31 | Advanced Micro Devices, Inc. | Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics |
CN111966406B (zh) * | 2020-08-06 | 2021-03-23 | 北京微核芯科技有限公司 | 乱序处理器中乱序执行队列的调度方法和装置 |
Family Cites Families (28)
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US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
US5255384A (en) * | 1985-02-22 | 1993-10-19 | Intergraph Corporation | Memory address translation system having modifiable and non-modifiable translation mechanisms |
JPH0762823B2 (ja) * | 1985-05-22 | 1995-07-05 | 株式会社日立製作所 | デ−タ処理装置 |
US4903196A (en) * | 1986-05-02 | 1990-02-20 | International Business Machines Corporation | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor |
JP2684362B2 (ja) * | 1986-06-18 | 1997-12-03 | 株式会社日立製作所 | 可変長データの記憶方式 |
US4811296A (en) * | 1987-05-15 | 1989-03-07 | Analog Devices, Inc. | Multi-port register file with flow-through of data |
US4992938A (en) * | 1987-07-01 | 1991-02-12 | International Business Machines Corporation | Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers |
JP2736092B2 (ja) * | 1989-01-10 | 1998-04-02 | 株式会社東芝 | バッファ装置 |
US5067069A (en) * | 1989-02-03 | 1991-11-19 | Digital Equipment Corporation | Control of multiple functional units with parallel operation in a microcoded execution unit |
US5125083A (en) * | 1989-02-03 | 1992-06-23 | Digital Equipment Corporation | Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system |
US5142633A (en) * | 1989-02-03 | 1992-08-25 | Digital Equipment Corporation | Preprocessing implied specifiers in a pipelined processor |
US5109495A (en) * | 1989-02-03 | 1992-04-28 | Digital Equipment Corp. | Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor |
US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
US5487156A (en) * | 1989-12-15 | 1996-01-23 | Popescu; Valeri | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched |
US5251306A (en) * | 1990-01-16 | 1993-10-05 | Advanced Micro Devices, Inc. | Apparatus for controlling execution of a program in a computing device |
US5120083A (en) * | 1990-03-19 | 1992-06-09 | Henkels & Mccoy, Inc. | Expansion joint for conduit for cables |
US5214763A (en) * | 1990-05-10 | 1993-05-25 | International Business Machines Corporation | Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism |
DE69127936T2 (de) * | 1990-06-29 | 1998-05-07 | Digital Equipment Corp | Busprotokoll für Prozessor mit write-back cache |
US5655096A (en) * | 1990-10-12 | 1997-08-05 | Branigin; Michael H. | Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution |
JP2911278B2 (ja) * | 1990-11-30 | 1999-06-23 | 松下電器産業株式会社 | プロセッサ |
US5261071A (en) * | 1991-03-21 | 1993-11-09 | Control Data System, Inc. | Dual pipe cache memory with out-of-order issue capability |
US5355457A (en) * | 1991-05-21 | 1994-10-11 | Motorola, Inc. | Data processor for performing simultaneous instruction retirement and backtracking |
US5345569A (en) * | 1991-09-20 | 1994-09-06 | Advanced Micro Devices, Inc. | Apparatus and method for resolving dependencies among a plurality of instructions within a storage device |
JPH0621466Y2 (ja) * | 1991-11-11 | 1994-06-08 | キャピーインターナショナル株式会社 | 担 架 |
US5285527A (en) * | 1991-12-11 | 1994-02-08 | Northern Telecom Limited | Predictive historical cache memory |
US5398330A (en) * | 1992-03-05 | 1995-03-14 | Seiko Epson Corporation | Register file backup queue |
US5628021A (en) * | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
US5604912A (en) * | 1992-12-31 | 1997-02-18 | Seiko Epson Corporation | System and method for assigning tags to instructions to control instruction execution |
-
1992
- 1992-12-31 US US07/999,648 patent/US5604912A/en not_active Expired - Lifetime
-
1993
- 1993-12-16 EP EP94904480A patent/EP0677188B1/en not_active Expired - Lifetime
- 1993-12-16 DE DE69305366T patent/DE69305366T2/de not_active Expired - Lifetime
- 1993-12-16 JP JP51601694A patent/JP3531167B2/ja not_active Expired - Lifetime
- 1993-12-16 KR KR1019950702704A patent/KR100295081B1/ko not_active IP Right Cessation
- 1993-12-16 WO PCT/US1993/012309 patent/WO1994016385A1/en active IP Right Grant
-
1997
- 1997-02-13 US US08/799,462 patent/US5892963A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021166030A (ja) * | 2020-04-07 | 2021-10-14 | 晶心科技股▲ふん▼有限公司Andes Technology Corporation | 読み取りシフタを備えたプロセッサおよびそれを用いた制御方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0677188A1 (en) | 1995-10-18 |
US5892963A (en) | 1999-04-06 |
KR100295081B1 (ko) | 2001-09-17 |
KR960700475A (ko) | 1996-01-20 |
DE69305366T2 (de) | 1997-02-20 |
JP3531167B2 (ja) | 2004-05-24 |
US5604912A (en) | 1997-02-18 |
WO1994016385A1 (en) | 1994-07-21 |
EP0677188B1 (en) | 1996-10-09 |
DE69305366D1 (de) | 1996-11-14 |
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